Synchronous rectification control device and method, flyback switching power supply

Abstract

The present invention discloses a synchronous rectification control device and method, and a flyback switching power supply. The synchronous rectification control device includes: a primary MOS transistor, a transformer, a secondary MOS transistor, a primary control chip, and a secondary control circuit. The primary control chip is used to control the primary MOS transistor to conduct at the valley position, excite the primary inductor of the transformer, increase the primary current, and then control the primary MOS transistor to shut down, ending the excitation of the primary inductor. The secondary control circuit is used to control the secondary MOS transistor to be turned on for the first time after the excitation of the primary inductor ends and during the secondary demagnetization process of the transformer, and to control the secondary MOS transistor to be turned on for the second time during the resonant stage after the demagnetization ends, so as to reduce the drain voltage of the primary MOS transistor before it is turned on again. Utilizing the solution of the present invention, the source-drain voltage of the primary MOS transistor at the time of turn-on can be reduced, the turn-on loss can be reduced, and the temperature rise of the primary MOS transistor can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a synchronous rectification control device and method. Background Art

[0002] A flyback switching power supply uses a high-frequency flyback transformer to isolate the input and output circuits. Its operating principle is that when the switch is on, the high-frequency transformer's primary winding stores energy. When the switch is off, the energy in the primary winding is released through the secondary winding to power the load. Due to its simple control and streamlined peripheral circuit structure, flyback switching power supplies are widely used in various applications. Typical applications include, but are not limited to, mobile phone chargers, laptop adapters, built-in power supplies for household appliances, and auxiliary power supplies for industrial power supplies. This type of switching power supply effectively controls current and voltage, improving power conversion efficiency. It is also known for its compact size and lightweight design, providing reliable power support for the stable operation of various electronic devices.

[0003] In the field of fast charging or adapter applications, existing flyback switching power supplies choose to use discontinuous conduction mode (DCM) in some low-power scenarios without strict efficiency requirements. That is, during the switching cycle, the inductor current always reaches 0, that is, when the power switch is closed, the inductor current is 0. The traditional mainstream solutions in the market are mostly quasi-resonant (QR) mode. QR mode is a mode between traditional resonant converters and hard switching. It optimizes energy conversion efficiency by controlling the on-time of the switch, while reducing switching losses and electromagnetic interference (EMI). It controls the primary-side MOS tube to turn on at the bottom of the valley, which can effectively reduce turn-on losses. Compared with the DCM mode, its EMI performance is also better.

[0004] like Figure 1 The figure shows the structure of a traditional synchronous rectifier flyback system. C1 is the input capacitor and C2 is the output capacitor. VIN is the input voltage and VOUT is the output voltage. The working process can be divided into three stages: (1) primary side excitation; (2) secondary side demagnetization; (3) LC resonance (or QR quasi-resonance). The specific process is as follows:

[0005] The primary-side control chip 11 controls the primary MOS transistor Q1 to conduct at the valley position. This conduction process excites the primary inductor of the transformer T, causing the excitation current to rise. Afterward, the primary MOS transistor Q1 is turned off, completing the excitation process. The secondary-side control chip 12 includes a switch control module and a driver module. When the primary-side excitation ends, the secondary side begins to demagnetize, accompanied by a decrease in the demagnetization current. The switch control module and the driver module process the analog signals of the drain terminal DRAIN of the secondary MOS transistor Q2 and the system output voltage VOUT, turning on the secondary MOS transistor Q2 at the appropriate position to reduce losses during the demagnetization process. When demagnetization is complete, the secondary MOS transistor Q2 is turned off. After a period of time (with both the primary and secondary MOS transistors off), LC resonance occurs (L refers to the transformer inductance, and C refers to the equivalent parasitic capacitance Cds of the primary and secondary MOS transistors and the transformer).

[0006] like Figure 2 Figure 2 shows a schematic diagram of the source-drain voltage curve of the primary MOS transistor near the turn-on moment when the conventional QR mode is used. At the moment the primary MOS transistor is turned on, its drain-source voltage difference Vds_pri drops directly from its valley voltage VDS1 to zero. The energy stored in the parasitic capacitance Cds is dissipated in the primary MOS transistor at the turn-on moment, causing the primary MOS transistor to heat up. In severe cases, this can affect the lifespan of the primary MOS transistor and circuit performance.

[0007] Therefore, how to reduce the turn-on loss of the primary MOS tube and lower the temperature rise of the primary MOS tube is an important issue that the industry needs to solve. Summary of the Invention

[0008] Embodiments of the present invention provide a synchronous rectification control device and method, and a flyback switching power supply to solve the problem in the prior art that when a conventional QR mode is turned on, the primary MOS tube has high turn-on loss, which causes the primary MOS tube to rise in temperature.

[0009] In one aspect, an embodiment of the present invention provides a synchronous rectification control device, comprising: a primary-side MOS transistor, a transformer, a secondary-side MOS transistor, a primary-side control chip, and a secondary-side control circuit;

[0010] The primary-side control chip is used to control the primary-side MOS transistor to conduct at the valley position, excite the primary-side inductor of the transformer, increase the primary-side current, and then control the primary-side MOS transistor to turn off, so that the excitation of the primary-side inductor ends;

[0011] The secondary side control circuit is used to control the secondary side MOS transistor to be turned on for the first time during the secondary side demagnetization process of the transformer after the excitation of the primary side inductor is completed, and to control the secondary side MOS transistor to be turned on for the second time during the resonance stage after the demagnetization is completed, so as to reduce the drain terminal voltage of the primary side MOS transistor before it is turned on again.

[0012] Optionally, the secondary side control circuit includes:

[0013] a switch control module, configured to output a first control signal during the demagnetization process of the secondary side of the transformer to control the secondary side MOS transistor to be turned on at a first moment for a first duration;

[0014] a secondary turn-on enabling module, configured to output a second control signal during a resonance phase after the secondary side of the transformer is demagnetized, to control the secondary side MOS transistor to be turned on for a second time at a second moment; the second moment being later than the first moment;

[0015] an anti-misoperational opening module, configured to detect whether the drain-source voltage difference waveform of the secondary MOS tube is distorted, and output a distortion detection result signal to the secondary opening enabling module to control the timing when the secondary opening enabling module outputs the second control signal;

[0016] A driving module is used to drive the secondary-side MOS transistor to turn on or off according to the first control signal and the second control signal.

[0017] Optionally, the switch control module, the driving module, the secondary opening enabling module, and the anti-misoperational opening module are packaged in the same chip.

[0018] Optionally, the switch control module and the drive module are packaged together as a secondary side control chip; the anti-misoperation module and the secondary opening enabling module are packaged together as a secondary opening control chip.

[0019] Optionally, the secondary-side MOS transistor and the secondary-side control circuit are packaged in the same chip.

[0020] Optionally, the device further includes: a protocol module, configured to regulate the output voltage VOUT so that the output voltage VOUT meets a set standard.

[0021] Optionally, the device further includes: a protocol module, configured to regulate the output voltage VOUT so that the output voltage VOUT meets a set standard; the protocol module is encapsulated in the secondary opening control chip.

[0022] Optionally, the device further includes: a protocol module, configured to regulate the output voltage VOUT so that the output voltage VOUT meets a set standard; the protocol module and the secondary-side control circuit are packaged in the same chip.

[0023] Optionally, the secondary side control circuit includes:

[0024] An auxiliary MOS tube, connected in parallel with the secondary MOS tube;

[0025] a synchronous rectification control chip, configured to control the secondary-side MOS transistor to be turned on at a first moment and for a first duration during the demagnetization process of the secondary side of the transformer;

[0026] The secondary opening control chip is used to control the auxiliary MOS tube to be turned on for a second time period at a second moment after the secondary MOS tube is turned off during the resonance stage after the secondary side demagnetization of the transformer is completed.

[0027] Optionally, the secondary-side MOS transistor is packaged in the synchronous rectification control chip.

[0028] Optionally, the auxiliary MOS tube is packaged in the secondary opening control chip.

[0029] Optionally, the auxiliary MOS transistor and the secondary MOS transistor are packaged in the same chip.

[0030] Optionally, the synchronous rectification control chip includes:

[0031] a switch control module, configured to output a first control signal during the demagnetization process of the secondary side of the transformer to control the secondary side MOS transistor to be turned on at a first moment for a first duration;

[0032] The first driving module is used to drive the secondary-side MOS transistor to turn on or off according to the first control signal.

[0033] Optionally, the secondary activation control chip includes:

[0034] a secondary turn-on enabling module, configured to output a second control signal during a resonance phase after the secondary side demagnetization of the transformer is completed, so as to control the auxiliary MOS transistor to be turned on for a second time period at a second moment after the secondary side MOS transistor is turned off;

[0035] an anti-misoperational opening module, configured to detect whether the drain-source voltage difference waveform of the secondary MOS tube is distorted, and output a distortion detection result signal to the secondary opening enabling module to control the timing when the secondary opening enabling module outputs the second control signal;

[0036] The second driving module is used to drive the auxiliary MOS tube to turn on or off according to the second control signal.

[0037] Optionally, the device further includes: a protocol module, used to regulate the output voltage VOUT so that the output voltage VOUT meets the set standard; the protocol module is independent of the synchronous rectification control chip and the secondary opening control chip; or the protocol module is encapsulated in the synchronous rectification control chip; or the protocol module is encapsulated in the secondary opening control chip.

[0038] Optionally, the anti-misoperational opening module controls the secondary opening enabling module to output the second control signal through a state machine.

[0039] On the other hand, an embodiment of the present invention further provides a flyback switching power supply, comprising the synchronous rectification control device.

[0040] On the other hand, an embodiment of the present invention further provides a synchronous rectification control method, the method comprising:

[0041] The primary MOS tube is controlled to conduct at the valley bottom position to excite the primary inductor of the transformer, causing the primary current to rise. Then the primary MOS tube is controlled to be turned off to end the excitation of the primary inductor.

[0042] After the excitation of the primary inductor is completed, during the demagnetization process of the secondary side of the transformer, controlling the secondary side MOS transistor to be turned on for the first time;

[0043] In the resonance stage after demagnetization, the secondary MOS transistor is controlled to be turned on for the second time, so as to reduce the drain voltage of the primary MOS transistor before it is turned on again.

[0044] The synchronous rectification control device and method, and the flyback switching power supply provided by the embodiments of the present invention control the primary MOS transistor to turn on at the valley bottom position through a primary-side control chip, excite the primary inductor of the transformer, increase the primary current, and then control the primary MOS transistor to turn off, so that the excitation of the primary inductor ends. After the excitation of the primary inductor ends, the secondary-side control circuit controls the secondary MOS transistor to be turned on once more during the resonance stage after the secondary side of the transformer is demagnetized, thereby effectively reducing the drain voltage of the primary MOS transistor before it is turned on again, reducing the turn-on loss of the primary MOS transistor, reducing the temperature rise of the primary MOS transistor, and improving system efficiency.

[0045] Furthermore, by providing an anti-misoperational opening module in the secondary-side control circuit, even when the drain-source voltage difference waveform of the secondary-side MOS tube is distorted, it can effectively ensure that the secondary-side MOS tube is turned on again at the appropriate time, thereby minimizing the turn-on loss of the primary-side MOS tube.

[0046] Furthermore, the modules in the secondary-side control circuit and the secondary-side MOS transistors can be integrated in a variety of ways to better meet different application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a schematic diagram of the structure of a traditional synchronous rectification flyback system;

[0048] Figure 2 This is a schematic diagram of the curve of the source-drain voltage of the primary MOS tube near the turn-on moment when the conventional QR mode is turned on;

[0049] Figure 3 1 is a schematic structural diagram of a synchronous rectification control device provided by an embodiment of the present invention;

[0050] Figure 4 Schematic diagram of related signals of the primary-side MOS transistor and the secondary-side MOS transistor at different stages in the synchronous rectification control device provided by an embodiment of the present invention;

[0051] Figure 5 The second opening mechanism is introduced in the embodiment of the present invention. Figure 2 The diagram shows a comparison of the curves of the source-drain voltage of the primary MOS tube near the turn-on moment when the conventional QR mode is turned on;

[0052] Figure 6 1 is a schematic diagram of a specific structure of a synchronous rectification control device provided by an embodiment of the present invention;

[0053] Figure 7 1 is another specific structural diagram of the synchronous rectification control device provided by an embodiment of the present invention;

[0054] Figure 8 1 is another specific structural diagram of the synchronous rectification control device provided by an embodiment of the present invention;

[0055] Figure 9 1 is another specific structural diagram of the synchronous rectification control device provided by an embodiment of the present invention;

[0056] Figure 10 2 is a schematic diagram showing the principle of detecting the distortion of the drain-source voltage difference waveform of a secondary-side MOS tube according to an embodiment of the present invention;

[0057] Figure 11 1 is a schematic diagram of state changes of a state machine when a state machine is used to implement the function of a secondary opening enabling module in an embodiment of the present invention;

[0058] Figure 12 This is a waveform diagram of the forward locking operation of the secondary-side MOS tube using a state machine for adaptive step-by-step secondary opening in an embodiment of the present invention;

[0059] Figure 13 This is a waveform diagram of the reverse locking operation of the secondary-side MOS tube using a state machine for adaptive step-by-step secondary opening in an embodiment of the present invention;

[0060] Figure 14 This is a flow chart of a synchronous rectification control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0062] To address the problem in existing QR-mode flyback switching power supplies where, at the moment the primary MOS tube is turned on, the energy stored in the parasitic capacitance of the primary MOS tube is dissipated in the primary MOS tube, causing the primary MOS tube temperature to rise, embodiments of the present invention provide a synchronous rectification control device and method, and a flyback switching power supply. By introducing a secondary turn-on mechanism for the secondary MOS tube, losses during the turn-on process of the primary MOS tube are further reduced, thereby improving system efficiency and reducing the temperature rise of the primary MOS tube.

[0063] like Figure 3 , which is a structural diagram of a synchronous rectification control device provided by an embodiment of the present invention.

[0064] This synchronous rectification control device includes a primary MOS transistor Q1, a transformer T, a secondary MOS transistor Q2, a primary control chip 21, and a secondary control circuit 22. Capacitors C1 and C2 serve as the input and output capacitors, respectively. VIN represents the input voltage, and VOUT represents the output voltage. The secondary control circuit 22 includes a drain terminal DRAIN, a gate terminal GATE, a ground terminal GND, and an output terminal VOUT (for ease of description, the output voltage will also be referred to as VOUT in the following description). These terminals are connected to the drain, gate, ground, and source of the secondary MOS transistor Q2, respectively. The source of the secondary MOS transistor Q2 is grounded.

[0065] In this embodiment, the primary-side control chip 21 is used to control the primary-side MOS transistor Q1 to turn on at a valley position (i.e., a position where the drain voltage of the primary-side MOS transistor Q1 is zero), thereby exciting the primary inductor of the transformer T and causing the primary current to increase, and then controlling the primary-side MOS transistor Q1 to turn off, thereby terminating the excitation of the primary inductor. The secondary-side control circuit 22 is used to control the secondary-side MOS transistor Q2 to turn on for the first time after the excitation of the primary inductor is completed and during the demagnetization process of the secondary side of the transformer T, and to control the secondary-side MOS transistor Q2 to turn on for the second time during the resonance phase after the demagnetization of the secondary side of the transformer T is completed, thereby generating a backflow current to reduce the drain voltage of the primary MOS transistor Q1 before it is turned on again, thereby reducing the turn-on loss of the primary MOS transistor and reducing the temperature rise of the primary MOS transistor. Specifically, after the secondary inductor demagnetization begins, the secondary control circuit 22 controls the secondary MOS transistor Q2 to be turned on for the first time by detecting the drain voltage of the secondary MOS transistor Q2, and turns off the secondary MOS transistor Q2 before the secondary inductor demagnetization is completed. In the resonance stage after the secondary side demagnetization of the transformer is completed, the secondary control circuit 22 controls the secondary MOS transistor Q2 to be turned on once more by detecting the drain voltage of the secondary MOS transistor Q2, and turns off the secondary MOS transistor Q2 after being turned on for a certain period of time.

[0066] In some embodiments, the synchronous rectification control device may further include a protocol module 30 for regulating the output voltage VOUT so that the output voltage VOUT meets a set standard.

[0067] Figure 4 A schematic diagram showing related signals of the primary-side MOS transistor and the secondary-side MOS transistor at different stages in the synchronous rectification control device provided by an embodiment of the present invention is shown.

[0068] Among them, Vds_pri represents the drain-source voltage difference of the primary MOS tube, and Vds_sec represents the drain-source voltage difference of the secondary MOS tube.

[0069] In phase 1 (t0-t1), the excitation phase: the control signal Sign1 controls the primary MOS transistor to start conducting when the drain-source voltage difference is close to 0, exciting the primary inductor of the transformer. At time t1, the control signal Sign1 controls the primary MOS transistor to turn off, and the excitation ends. During this process, the secondary MOS transistor is turned off.

[0070] In phase 2 (t1-t2), the demagnetization phase: after the primary inductance excitation of the transformer is completed, the control signal Sign2 controls the secondary MOS tube to be turned on for the first time, and before the demagnetization is completed at time t2, the secondary MOS tube is turned off.

[0071] In phase 3, i.e., the resonant phase after demagnetization: in the resonant phase after demagnetization, the secondary MOS transistor is turned on for the second time by the control signal Sign3, generating a backflow current, thereby reducing the drain voltage of the primary MOS transistor Q1 before it is turned on again.

[0072] Compared with the existing QR mode control mechanism, the synchronous rectification control device provided by the embodiment of the present invention introduces a secondary turn-on mechanism to the secondary MOS tube, so that before the primary MOS tube is turned on, the drain voltage of the primary MOS tube Q1 is reduced, thereby reducing its turn-on loss and improving system efficiency. Figure 5 Explain clearly.

[0073] Reference Figure 5 , is to introduce the secondary opening mechanism and Figure 2 The figure shows a comparison diagram of the curves of the source-drain voltage of the primary MOS tube near the turn-on moment when the conventional QR mode is turned on.

[0074] Figure 5 (a) is above Figure 2 (b) is a schematic diagram of the curve of the source-drain voltage of the primary MOS tube near the turn-on time when the conventional QR mode is used for turn-on, and (c) is a schematic diagram of the curve of the source-drain voltage of the primary MOS tube near the turn-on time when the secondary MOS tube is turned on for the second time.

[0075] The loss at the moment the primary MOS tube is turned on can be represented by the following formula:

[0076] ;

[0077] in, Represents the parasitic capacitance of the primary MOS tube, Indicates the voltage difference between the drain and source of the primary MOS tube.

[0078] Reference Figure 5 In (a) and (b), when the primary MOS transistor is turned on, the two-way turn-on mechanism is used to reduce the voltage difference between the drain and source of the primary MOS transistor from the current position VDS1 (VDS1 is approximately VIN-N×VOUT, where N is the turns ratio of the primary-to-secondary transformer) to VDS2 (VDS2 is close to 0). This can reduce the turn-on loss of the primary MOS transistor and effectively improve system efficiency.

[0079] In specific implementation, Figure 3 The secondary side control circuit 22 in the synchronous rectification control device shown can have various structural modes, which are described below with examples.

[0080] like Figure 6 FIG. 1 is a schematic diagram of a specific structure of a synchronous rectification control device provided by an embodiment of the present invention.

[0081] The primary control chip 21 is used to control the primary MOS transistor Q1 to conduct at the valley position, excite the primary inductor of the transformer T, increase the primary current, and then control the primary MOS transistor Q1 to turn off, so that the primary inductor excitation ends.

[0082] The secondary side control circuit 22 includes: a switch control module 201, a secondary opening enabling module 204, an anti-misoperational opening module 203, and a driving module 202.

[0083] The switch control module 201 is used to output a first control signal during the demagnetization process of the secondary side of the transformer T to control the secondary side MOS transistor Q2 to be turned on at a first moment and for a first duration;

[0084] The secondary turn-on enabling module 204 is configured to output a second control signal during the resonance phase after the secondary side of the transformer T is demagnetized, so as to control the secondary side MOS transistor Q2 to be turned on for a second time at a second moment; the second moment is delayed from the first moment;

[0085] The anti-mistaken-start module 203 is configured to detect whether there is distortion in the drain-source voltage difference waveform of the secondary MOS transistor and output a distortion detection result signal to the secondary-start enabling module 204 to control the timing when the secondary-start enabling module 204 outputs the second control signal. The anti-mistaken-start module 203 can better ensure the secondary-start timing of the secondary MOS transistor Q2 and avoid erroneous startup at an inappropriate time.

[0086] The driving module 202 is configured to drive the secondary MOS transistor Q2 to turn on or off according to the first control signal and the second control signal.

[0087] The first turn-on time of the secondary MOS transistor Q2 (ie, the first moment) is determined by the switch control module 201 according to the detection result of the drain voltage of the secondary MOS transistor Q2 , which is the same as the prior art and is not limited in this embodiment of the present invention.

[0088] The second turn-on time of the secondary MOS transistor Q2 (ie, the second moment) is determined by the detection result of the secondary MOS transistor drain-source voltage difference waveform by the anti-misoperation module 203 , which will be described in detail later.

[0089] In this embodiment, after the primary side excitation of the transformer T is completed, the secondary side first begins to demagnetize, accompanied by a decrease in the demagnetization current. The switch control module 201 processes the analog signals at the drain terminal DRAIN and the output terminal of the secondary MOS transistor Q2, and turns on the secondary MOS transistor Q2 for a certain duration at an appropriate position (i.e., the first moment), thereby reducing losses in the secondary MOS transistor Q2 during the demagnetization process. Then, in the resonance phase after the secondary side demagnetization is completed, the anti-misoperation module 203 and the secondary-operation enabling module 204 process the analog signals at the drain terminal DRAIN and the output terminal of the secondary MOS transistor Q2, and turns on the secondary MOS transistor Q2 for a certain duration at another appropriate position (i.e., the second moment), thereby generating a reverse current in the secondary inductor of the transformer T. After the secondary MOS transistor Q2 is turned off, the primary inductor of the transformer T experiences a reverse current, forcing the drain charge of the primary MOS transistor Q1 to transfer to the input power supply. Before the primary MOS transistor Q1 is turned on, the drain voltage of the primary MOS transistor Q1 drops to a lower level.

[0090] In some embodiments, the switch control module 201, secondary opening enabling module 204, driving module 202, and anti-misoperational opening module 203 can be packaged in the same chip, which can be referred to as an adaptive step-by-step secondary side control chip for ease of description. Figure 6 As shown, the chip includes the following ports: a drain terminal DRAIN, a gate terminal GATE, a ground terminal GND, and an output terminal VOUT, which are respectively connected to the drain, gate, ground, and source of the secondary MOS transistor Q2.

[0091] In some embodiments, the secondary MOS transistor Q2 may be packaged into the adaptive step-by-step secondary control chip.

[0092] like Figure 7As shown, the switch control module 201 includes an input terminal and an output terminal; the anti-misoperation module 203 includes an input terminal and an output terminal; the secondary opening enabling module 204 includes a leakage voltage sampling terminal P1, a detection control terminal P2 and an output terminal P3; the driving module 202 includes two input terminals and one output terminal, the two input terminals being a driving control terminal and a function control terminal respectively; the driving control terminal is connected to the output terminal of the switch control module 201, and the function control terminal is connected to the output terminal P3 of the secondary opening enabling module 204.

[0093] In addition, the input end of the switch control module 201, the input end of the anti-misoperation module 203, and the leakage voltage sampling end P1 of the secondary opening enabling module 204 are all connected to the drain end DRAIN of the chip; the output end of the anti-misoperation module 203 is connected to the detection control end P2 of the secondary opening enabling module 204.

[0094] It should be noted that each of the above modules is powered by a stable power supply obtained by pre-processing the output terminal VOUT, and is connected to a common ground with the output terminal VOUT.

[0095] like Figure 7 As shown, in some embodiments, the protocol module 30 may be integrated into the adaptive step-by-step secondary-side control chip 23 to further improve the chip integration.

[0096] like Figure 8 , which is another specific structural diagram of the synchronous rectification control device provided by an embodiment of the present invention.

[0097] and Figure 6 The difference between the illustrated embodiment and the illustrated embodiment is that, in this embodiment, the switch control module 201 and the drive module 202 are packaged in the same chip, which is referred to as the secondary side control chip 31 for the convenience of description; the anti-misoperational opening module 203 and the secondary opening enabling module 204 are packaged in the same chip, which is referred to as the secondary opening control chip 32 for the convenience of description.

[0098] The secondary-side control chip 31 includes the following ports: a drain terminal DRAIN, a gate terminal GATE, a ground terminal GND, and an output terminal VOUT, which are respectively connected to the drain, gate, ground, and source of the secondary-side MOS transistor Q2. The secondary-side enable control chip 32 includes the following ports: a drain terminal DRAIN, a ground terminal GND, and an output terminal VOUT, which are respectively connected to the drain, ground, and source of the secondary-side MOS transistor Q2. Furthermore, the secondary-side control chip 31 includes an input control port VCTRL connected to the function control terminal of the driver module 202; the secondary-side enable control chip 32 also includes an output control port VCTRL connected to the output terminal of the secondary enable module 204.

[0099] In this structure, the secondary side control chip 31 is basically the same as the secondary side control chip used in the traditional synchronous rectification flyback system, so that it can be implemented by only leading out a functional control port (ie the control port VCTRL) on the traditional structure drive module.

[0100] In some embodiments, the protocol module 30, the anti-misoperation module 203, and the secondary activation enabling module 204 can be packaged together in the same chip. For ease of description, this chip is referred to as an adaptive step secondary activation function protocol chip 33. The ports of the adaptive step secondary activation function protocol chip 33 are the same as those of the secondary activation control chip 32, and are not further described here.

[0101] like Figure 9 , which is another specific structural diagram of the synchronous rectification control device provided by an embodiment of the present invention.

[0102] The synchronous rectification control device of this embodiment includes: a primary MOS transistor Q1, a transformer T, a secondary MOS transistor Q2, an auxiliary MOS transistor Q3, a synchronous rectification control chip 41, and a secondary opening control chip 42. Among them, the auxiliary MOS transistor Q3, the synchronous rectification control chip 41, and the secondary opening control chip 42 are used as Figure 3 The secondary side control circuit 22 in.

[0103] The auxiliary MOS transistor Q3 is connected in parallel with the secondary MOS transistor Q2.

[0104] The synchronous rectification control chip 41 is used to control the secondary side MOS transistor Q2 to be turned on at a first moment and for a first duration during the demagnetization process of the secondary side of the transformer T;

[0105] The secondary turn-on control chip 42 is used to control the auxiliary MOS transistor Q3 to turn on for a second duration at a second moment after the secondary MOS transistor Q2 is turned off during the resonance phase after the secondary side of the transformer T is demagnetized.

[0106] In this embodiment, the synchronous rectification control chip 41 includes: a switch control module 201 and a first drive module 221, both of which have the same functions. Figure 6 Similar to the embodiment shown, that is, the switch control module 201 is used to output a first control signal during the demagnetization process of the secondary side of the transformer T to control the secondary side MOS transistor Q2 to be turned on for a first duration at a first moment; the first driving module 221 is used to drive the secondary side MOS transistor Q2 to be turned on or off according to the first control signal.

[0107] The secondary opening control chip 42 includes: an anti-mis-opening module 203, a secondary opening enabling module 204, and a second driving module 222.

[0108] The secondary turn-on enabling module 204 is configured to output a second control signal during the resonance phase after the secondary side demagnetization of the transformer T is completed, so as to control the auxiliary MOS transistor Q3 to be turned on for a second duration at a second moment after the secondary side MOS transistor Q2 is turned off;

[0109] The anti-misoperational switching module 203 is configured to detect whether there is distortion in the drain-source voltage difference waveform of the secondary MOS transistor, and output a distortion detection result signal to the secondary switching-on enabling module 204 to control the timing at which the secondary switching-on enabling module 204 outputs the second control signal, thereby ensuring that the auxiliary MOS transistor Q3 is switched on at an appropriate position.

[0110] The second driving module 222 is used to drive the auxiliary MOS transistor Q3 to turn on or off according to the second control signal.

[0111] Relative to Figure 6 The embodiment shown, Figure 9 In the synchronous rectification control device shown, the secondary turn-on mechanism is implemented by two MOS transistors connected in parallel on the secondary side and their corresponding drive circuits. This structure can directly add the secondary turn-on function to conventional flyback systems without modifying the existing chip. It also expands the application scope of this solution beyond MOS synchronous rectification flyback systems to include, but not limited to, flyback systems using passive rectification with power diodes.

[0112] Reference Figure 9 The synchronous rectification control chip 41 is fully compatible with existing conventional synchronous rectification control chips.

[0113] In some embodiments, the auxiliary MOS transistor Q3 , the anti-misoperation module 203 , the secondary operation enabling module 204 , and the second driving module 222 may be packaged in the same chip 43 to further improve the chip integration.

[0114] In some embodiments, the secondary MOS transistor Q2 may be packaged in the synchronous rectification control chip 41 .

[0115] In some embodiments, the auxiliary MOS transistor Q3 may be further sealed in the secondary turn-on control chip 42 .

[0116] In some embodiments, the secondary MOS transistor Q2 and the auxiliary MOS transistor Q3 may be packaged in the same chip.

[0117] like Figure 9 As shown, in some embodiments, the synchronous rectification control device may further include a protocol module 30. In a specific implementation, the protocol module 30 may be an independent chip, or be packaged in a synchronous rectification control chip 41; or be packaged in a secondary opening control chip 42, which is not limited in this embodiment of the present invention.

[0118] Under normal circumstances, within a synchronous rectification circuit, the drain-source voltage difference Vds_sec of the secondary MOS transistor undergoes n (the value of n depends on the actual circuit and can be designed based on actual needs) low pulses before reaching a high pulse. Ideally, if the Vds_sec waveform remains stable throughout each cycle, the timing of the secondary turn-on, the second moment described above, can also be maintained at the same point in each switching cycle. However, in actual circuit applications, the actual operating environment may affect the circuit, resulting in distortion of one or more low pulses in the Vds_sec waveform.

[0119] In the above embodiments, the mis-start prevention module 203 detects whether there is distortion in the waveform of the drain-source voltage difference Vds_sec of the secondary MOS transistor. For example, the distortion can be determined by analyzing the width, area, slope, etc. of the waveform, and outputs a distortion detection result signal to the secondary start-up enabling module 204. Accordingly, the secondary start-up enabling module 204 can ensure that the second control signal is output at an appropriate position in a switching cycle based on the distortion detection result signal.

[0120] The following combination Figure 10 The detection principle of the anti-misoperation module 203 for detecting whether the waveform of the drain-source voltage difference Vds_sec of the secondary MOS tube is distorted is described in detail.

[0121] like Figure 10 As shown, (a) is a schematic diagram of the Vds_sec waveform under normal conditions; (b) is a schematic diagram of the Vds_sec waveform under distortion. For the convenience of description, Figure 10 Only one low pulse wave and one high pulse wave in one switching cycle are shown.

[0122] based on Figure 10 The signal characteristics of the Vds_sec waveform when it is distorted are shown. In specific implementation, the anti-misoperational module 203 can detect whether the Vds_sec waveform is distorted in a variety of ways, which are described below with examples.

[0123] Example 1: The mis-start prevention module 203 may determine whether Vds_sec is distorted by detecting whether the voltage difference Vds_sec waveform exceeds a certain multiple of the output voltage VOUT for a duration t.

[0124] Specifically, refer to Figure 10 As shown in (b), it is determined whether the time t during which Vds_sec exceeds X times VOUT is greater than a first set time t1; if it does not exceed t1, it is considered that there is distortion; if it exceeds t1, it is considered that it is a normal high pulse wave;

[0125] Here, X may vary depending on the actual application environment. For example, a typical value may be: 2.0≤X≤4.

[0126] Example 2: The mis-start prevention module 203 may determine whether Vds_sec is distorted by detecting the magnitude of the volt-second product s of the voltage difference Vds_sec waveform.

[0127] Specifically, it is determined whether the volt-second product s obtained by integrating Vds_sec during the time period when it exceeds X times VOUT is greater than a first reference value s1; if it does not exceed s1, it is considered that there is distortion; if it exceeds s1, it is considered to be a normal high pulse wave;

[0128] Here, X may vary depending on the actual system environment. For example, a typical value may be: 2.0≤X≤4.

[0129] Example 3: The mis-start prevention module 203 may determine whether Vds_sec is distorted by detecting the magnitude of the falling edge slope k of the voltage difference Vds_sec waveform.

[0130] Specifically, it is determined whether the falling edge slope k after Vds_sec exceeds X times VOUT is greater than a first reference slope value k1; if it does not exceed k1, it is considered that there is distortion; if it exceeds k1, it is considered to be a normal high pulse wave.

[0131] The specific implementation of each of the above-mentioned methods may adopt some corresponding conventional circuits, which is not limited in the embodiment of the present invention.

[0132] It should be noted that, in actual applications, the detection of the secondary MOS tube drain-source voltage difference Vds_sec waveform by the anti-misoperational opening module 203 is not limited to the above three methods, and other implementation methods are also possible. The intended function is to effectively distinguish the distorted waveform while normally realizing the anti-misoperational opening function. The specific method can be selected according to the actual system environment.

[0133] It should be noted that the gate drive voltage value when the secondary MOS tube is turned on for the second time may be different from the gate drive voltage value when the conventional SR is turned on, thereby optimizing the effect of the secondary MOS tube being turned on for the second time.

[0134] Based on the detection result of the anti-misoperation module 203 , the secondary-operation enabling module 204 can secondary-operate the secondary-side MOS transistor at an appropriate position.

[0135] In some non-limiting embodiments, the anti-misoperational opening module 203 analyzes and processes the drain terminal DRAIN analog signal to distinguish characteristic information such as low pulse waves, distorted low pulse waves, and high pulse waves; the secondary opening enabling module 204 can use different state machines such as a fully increasing finite state machine, a fully decreasing finite state machine, and an adaptive increasing and decreasing finite state machine to implement the above functions.

[0136] Taking an adaptive increment-decrement finite state machine as an example, this state machine includes a total of n legal states (n low pulses of the secondary MOS transistor drain-source voltage differential Vds_sec waveform) starting from state S1 and increasing sequentially to state Sn. This state machine can achieve transitions between different states based on a step counter. It should be noted that when the secondary turn-on control begins, the state machine can be in any of these states.

[0137] As shown in Table 1 below, the detection results of the drain-source voltage difference Vds_sec waveform of the anti-mistaken-start module 203 and the state transition vectors corresponding to the four situations in which the secondary start-up enabling module 204 determines whether to issue a secondary start-up signal (i.e., the second control signal described above) in this cycle based on the judgment result of the anti-mistaken-start module 203 are shown, as well as the step counter actions corresponding to the transition vectors.

[0138] Table 1

[0139]

[0140] like Figure 11 The following is a schematic diagram of different state changes of the state machine.

[0141] For all states, when the transfer vector is detected to be 01, the current state is directly retained and the secondary activation mode is exited until the transfer vector is detected to be 00, 10 or 11.

[0142] For all states, when the transition vector is detected to be 10, the step count value remains unchanged.

[0143] For states S2 to Sn-1, when the detected transfer vector is 11, the state is transferred to the next state in increments; when the detected transfer vector is 00, the state is transferred to the previous state in decrement.

[0144] For state S1, when the transfer vector is detected to be 11, it transfers to state S2; when the transfer vector is detected to be 00, it maintains the current state and exits the secondary activation mode until the transfer vector is detected to be 10 or 11.

[0145] For state Sn, when the transfer vector is detected to be 11, the current state is maintained and the secondary activation mode is exited until the transfer vector is detected to be 00 or 10; when the transfer vector is 00, the state is transferred to state Sn-1.

[0146] It should be noted that, during the entire control cycle, the secondary MOS transistor Q2 is simultaneously controlled by the switch control module 201, and only when the secondary MOS transistor Q2 is not in the on state controlled by the switch control module 201, the anti-misoperational-start module 203 will output the distortion detection signal and convert the second control signal output by the secondary-on enabling module 204 into an actual gate drive voltage Vgs to drive the secondary MOS transistor Q2 to be turned on for the second time, or to drive the auxiliary MOS transistor Q3 to be turned on.

[0147] By using the above state machine, it is possible to avoid turning on the secondary MOS transistor twice at the wrong time, ensuring that the secondary MOS transistor can be turned on twice at the appropriate position in each switching cycle until it is locked. Figure 12 and Figure 13 This is explained in detail.

[0148] like Figure 12 , which is a waveform diagram of the forward locking operation of the secondary-side MOS tube by adaptively stepping twice on the secondary-side MOS tube using the state machine in an embodiment of the present invention.

[0149] Figure 12 The curves in FIG are schematic diagrams of the internal waveforms of a flyback switching power supply including the secondary MOS tube secondary turn-on function when performing forward adaptive step tracking. Among them:

[0150] Waveform 141 is the source-drain voltage difference waveform Vds_pri of the primary MOS tube;

[0151] Waveform 142 is the secondary side MOS tube source-drain voltage difference waveform Vds_sec;

[0152] Waveform 143 is the primary MOS transistor gate drive voltage waveform PWM;

[0153] Waveform 144 is the waveform Vctrl of the secondary-side MOS transistor secondary turn-on enable signal (i.e., the second control signal mentioned above);

[0154] Waveform 145 is the switch control module driving voltage waveform SR.

[0155] Depend on Figure 12 As can be seen, as the position of the distorted secondary MOS transistor source-drain voltage difference waveform Vds_sec changes, the position of the secondary MOS transistor secondary turn-on enable signal Vctrl also changes. After n switching cycles, the secondary turn-on enable module can correctly capture the bottom of the Vds_sec waveform. Once the waveform is no longer distorted and remains stable, the position of the secondary MOS transistor secondary turn-on enable signal Vctrl also becomes relatively fixed and no longer changes.

[0156] like Figure 13, which is a waveform diagram of the reverse locking operation of the secondary-side MOS tube by adaptively stepping twice and turning it on using a state machine in an embodiment of the present invention.

[0157] Figure 13 The curves in FIG are schematic diagrams of internal waveforms of a flyback switching power supply including a secondary MOS tube secondary turn-on function when performing reverse adaptive step tracking. Among them:

[0158] Waveform 146 is the primary MOS tube source-drain voltage difference waveform Vds_pri;

[0159] Waveform 147 is the secondary side MOS tube source-drain voltage difference waveform Vds_sec;

[0160] Waveform 148 is the primary MOS transistor gate drive voltage waveform PWM;

[0161] Waveform 149 is the secondary-side MOS transistor secondary turn-on enable waveform Vctrl (i.e., the second control signal mentioned above);

[0162] Waveform 150 is the switch control module driving voltage waveform SR.

[0163] Reference Figure 13 It can be seen that in the first switching cycle, the secondary turn-on enabling module can correctly capture the bottom of the Vds_sec waveform. In the second to n-2 switching cycles, due to load changes, the primary side is turned on before the system generates the secondary turn-on enabling signal Vctrl. During this stage, the step count value inside the state machine continuously decreases with each cycle. In the n-1 switching cycle, the secondary turn-on enabling module is about to generate the Vctrl turn-on enabling signal, but it overlaps with the next cycle, and only one turn-on is actually generated. After n switching cycles, the secondary turn-on enabling module can correctly capture the bottom of the secondary MOS tube source-drain voltage difference waveform Vds_sec. The secondary MOS tube is stably turned on twice in each switching cycle without waveform distortion.

[0164] The synchronous rectification control device provided in an embodiment of the present invention selects an appropriate time to perform an additional turn-on of the secondary MOS tube before the primary MOS tube is turned on. This action transfers the remaining energy in the primary quasi-resonant system back to the power supply, effectively reducing the source-drain voltage of the primary MOS tube at the turn-on moment, thereby reducing turn-on loss and lowering the temperature rise of the primary MOS tube.

[0165] Accordingly, an embodiment of the present invention further provides a flyback switching power supply including the above-mentioned synchronous rectification control device, which has the advantages of low switching loss and high efficiency compared to traditional flyback switching power supplies.

[0166] Accordingly, an embodiment of the present invention further provides a synchronous rectification control method, such as Figure 14FIG. 1 is a flow chart of the method, comprising the following steps:

[0167] In step S141, the primary MOS transistor is controlled to be turned on at the valley bottom position to excite the primary inductor of the transformer, causing the primary current to increase, and then the primary MOS transistor is controlled to be turned off to terminate the excitation of the primary inductor;

[0168] In step S142 , after the primary inductor excitation is completed and during the secondary demagnetization process of the transformer, the secondary MOS transistor is controlled to be turned on for the first time.

[0169] In step S143 , the secondary MOS transistor is controlled to be turned on for the second time in the resonance stage after the demagnetization is completed, so as to reduce the drain voltage of the primary MOS transistor before it is turned on again.

[0170] The synchronous rectification control method provided by the embodiment of the present invention can effectively reduce the turn-on loss of the primary-side MOS tube and improve system efficiency by introducing a secondary turn-on mechanism.

[0171] In the present invention, unless otherwise expressly specified or limited, ordinal numbers, such as "first" and "second," are used only to distinguish and describe related objects and should not be understood to indicate or imply the relative importance or order of the related objects. In addition, ordinal numbers do not represent the number of related objects.

[0172] "Multiple" includes two or more, and other quantifiers are similar.

[0173] The terms "or" and "and / or" in the present invention are used to describe the relationship between associated objects, which means non-exclusive inclusion. For example, "A and / or B" can include: "A alone", "B alone", or "A and B".

[0174] In the several embodiments provided by the present invention, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the module division is merely a logical functional division, and actual implementation may employ other division methods, which are not limited by the present invention.

[0175] In addition, the functional modules in the various embodiments of the present invention may be integrated into a single processing unit, or may be separate physical units, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware and software functional units.

[0176] An integrated unit implemented as a hardware and software functional unit can be implemented in the form of a processor calling software; for example, a system includes a processor connected to a memory, the memory storing instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or the functions of each module of the system, where the processor is, for example, a general-purpose processor such as a CPU or a microprocessor, and the memory is memory within the system or memory outside the system. The above software can be stored in a computer-readable storage medium.

[0177] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A synchronous rectification control device, characterized in that: The device includes: a primary-side MOS tube, a transformer, a secondary-side MOS tube, a primary-side control chip, and a secondary-side control circuit; The primary-side control chip is used to control the primary-side MOS transistor to conduct at the valley position, excite the primary-side inductor of the transformer, increase the primary-side current, and then control the primary-side MOS transistor to turn off, so that the excitation of the primary-side inductor ends; The secondary-side control circuit is configured to control the secondary-side MOS transistor to be turned on for the first time during the secondary-side demagnetization process of the transformer after the excitation of the primary-side inductor is completed, and to turn off the secondary-side MOS transistor before the secondary-side demagnetization is completed; and to control the secondary-side MOS transistor to be turned on for the second time by detecting the drain voltage of the secondary-side MOS transistor during the resonance phase after the secondary-side demagnetization is completed, so as to reduce the drain voltage of the primary-side MOS transistor before it is turned on again; The secondary side control circuit includes: a switch control module, configured to output a first control signal during the demagnetization process of the secondary side of the transformer to control the secondary side MOS transistor to be turned on at a first moment for a first duration; a secondary turn-on enabling module, configured to output a second control signal during a resonance phase after the secondary side of the transformer is demagnetized, to control the secondary side MOS transistor to be turned on for a second time at a second moment; the second moment being later than the first moment; an anti-mistaken-start module, configured to detect whether there is distortion in the drain-source voltage difference waveform of the secondary MOS tube, and output a distortion detection result signal to the secondary opening enabling module; and perform a logical judgment based on the second control signal output by the secondary opening enabling module in the current cycle and the distortion detection result signal output by the anti-mistaken-start module in the current cycle, so as to control the timing when the secondary opening enabling module outputs the second control signal in the next cycle; A driving module is used to drive the secondary-side MOS transistor to turn on or off according to the first control signal and the second control signal.

2. The synchronous rectification control device according to claim 1, characterized in that: The switch control module, the driving module, the secondary opening enabling module, and the anti-misoperational opening module are sealed in the same chip.

3. The synchronous rectification control device according to claim 1, wherein: The switch control module and the drive module are packaged together as a secondary side control chip; the anti-misoperation module and the secondary opening enabling module are packaged together as a secondary opening control chip.

4. The synchronous rectification control device according to claim 1, characterized in that: The secondary side MOS transistor and the secondary side control circuit are sealed in the same chip.

5. The synchronous rectification control device according to claim 2, 3 or 4, characterized in that: The device further comprises: The protocol module is used to regulate the output voltage VOUT so that the output voltage VOUT meets the set standard.

6. The synchronous rectification control device according to claim 3, characterized in that: The device further comprises: A protocol module, configured to regulate the output voltage VOUT so that the output voltage VOUT meets a set standard; The protocol module is encapsulated in the secondary activation control chip.

7. The synchronous rectification control device according to claim 4, characterized in that: The device further comprises: A protocol module, configured to regulate the output voltage VOUT so that the output voltage VOUT meets a set standard; The protocol module and the secondary side control circuit are packaged in the same chip.

8. The synchronous rectification control device according to claim 1, wherein: The secondary side control circuit includes: An auxiliary MOS tube, connected in parallel with the secondary MOS tube; a synchronous rectification control chip, configured to control the secondary-side MOS transistor to be turned on at a first moment and for a first duration during the demagnetization process of the secondary side of the transformer; The secondary opening control chip is used to control the auxiliary MOS tube to be turned on for a second time period at a second moment after the secondary MOS tube is turned off during the resonance stage after the secondary side demagnetization of the transformer is completed.

9. The synchronous rectification control device according to claim 8, characterized in that: The secondary side MOS tube is packaged in the synchronous rectification control chip.

10. The synchronous rectification control device according to claim 8, characterized in that: The auxiliary MOS tube is packaged in the secondary opening control chip.

11. The synchronous rectification control device according to claim 8, characterized in that: The auxiliary MOS transistor and the secondary MOS transistor are sealed in the same chip.

12. The synchronous rectification control device according to any one of claims 8 to 11, characterized in that: The synchronous rectification control chip includes: a switch control module, configured to output a first control signal during the demagnetization process of the secondary side of the transformer to control the secondary side MOS transistor to be turned on at a first moment for a first duration; The first driving module is used to drive the secondary-side MOS transistor to turn on or off according to the first control signal.

13. The synchronous rectification control device according to claim 12, wherein: The secondary opening control chip includes: a secondary turn-on enabling module, configured to output a second control signal during a resonance phase after the secondary side demagnetization of the transformer is completed, so as to control the auxiliary MOS transistor to be turned on for a second time period at a second moment after the secondary side MOS transistor is turned off; an anti-misoperational opening module, configured to detect whether the drain-source voltage difference waveform of the secondary MOS tube is distorted, and output a distortion detection result signal to the secondary opening enabling module to control the timing when the secondary opening enabling module outputs the second control signal; The second driving module is used to drive the auxiliary MOS tube to turn on or off according to the second control signal.

14. The synchronous rectification control device according to claim 12, wherein: The device further comprises: A protocol module, configured to regulate the output voltage VOUT so that the output voltage VOUT meets a set standard; The protocol module is independent of the synchronous rectification control chip and the secondary activation control chip; or the protocol module is encapsulated in the synchronous rectification control chip; or the protocol module is encapsulated in the secondary activation control chip.

15. The synchronous rectification control device according to claim 13, wherein: The anti-misoperational opening module controls the secondary opening enabling module to output the second control signal through a state machine.

16. A flyback switching power supply, characterized in that: The synchronous rectification control device comprises the synchronous rectification control device according to any one of claims 1 to 15.

17. A synchronous rectification control method, characterized in that: The method comprises: The primary MOS tube is controlled to conduct at the valley bottom position to excite the primary inductor of the transformer, causing the primary current to rise. Then the primary MOS tube is controlled to be turned off to end the excitation of the primary inductor. After the excitation of the primary inductor is completed, during the demagnetization process of the secondary side of the transformer, a first control signal is generated to control the secondary side MOS transistor to be turned on for the first time, and the secondary side MOS transistor is turned off before the secondary side demagnetization is completed; In the resonance stage after the secondary side demagnetization is completed, the drain terminal voltage of the secondary side MOS tube is detected to determine whether the drain-source voltage difference of the secondary side MOS tube is distorted. A second control signal is generated based on the detection result to control the secondary side MOS tube to be turned on for a second time, so as to reduce the drain terminal voltage of the primary side MOS tube before it is turned on again. In addition, a logical judgment is performed based on the second control signal generated in the current cycle and the distortion detection result of the current cycle to control the timing of generating the second control signal in the next cycle.

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