Operational amplifier

Abstract

The application discloses an operational amplifier, comprising: a first input stage circuit comprising a first differential pair of PMOS transistors for generating a first differential current signal corresponding to a voltage difference between a positive input signal and a negative input signal; the second input stage circuit comprises a second differential pair of NMOS transistors, and the second differential pair is used for generating a second differential current signal corresponding to the voltage difference of the positive input signal and the negative input signal; and the switching circuit is connected between the second input stage circuit and the input end of the operational amplifier. Wherein the switching circuit is used for conducting a connection path between the input end of the operational amplifier and the second differential pair only when the input common-mode voltage is greater than the reference voltage, so that the second input stage circuit does not contribute extra noise and offset voltage when the operational amplifier works normally, and the common-mode rejection ratio of the circuit is not influenced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to an operational amplifier. Background Art

[0002] In integrated circuit design, the input common-mode range of an operational amplifier is a key parameter that directly affects its performance in different applications. In traditional op amp design, when the input common-mode range of the op amp has a certain margin from the power supply / ground rail, a pair of input transistors is usually used to meet the input common-mode range requirements. However, in some special application scenarios, the input signal may exceed the calibrated common-mode input range, which may cause the input transistor to be cut off, thereby causing the op amp output to be unstable and phase inversion problems.

[0003] To solve this problem, a pair of auxiliary input tubes with smaller size and current can be introduced. This design idea is similar to a simplified version of the handover structure, which aims to ensure that the output polarity of the op amp remains correct when the input signal exceeds the common mode range. Although the introduction of this auxiliary input tube can effectively avoid phase inversion and improve the stability and reliability of the op amp in a wide input range, the introduction of an additional auxiliary input tube may lead to an increase in chip area.

[0004] like Figure 1 As shown, the operational amplifier 100 of the prior art adds an additional NMOS input pair (i.e., NMOS transistors Mn1 and Mn2) on the basis of the traditional PMOS input pair (i.e., PMOS transistors Mp1 and Mp2). The input terminals of the NMOS input pair and the PMOS input pair are connected together to form a normally-on auxiliary input structure, and the bias current of the NMOS input pair Mn1 and Mn2 can be set to be relatively small. This design enables the circuit to work normally without distinguishing between high and low input common-mode levels. Among them, NMOS transistors Mn1 and Mn2 can withstand higher voltages as high-voltage tubes, transistor Mn4 can provide a stable bias current for the NMOS input pair as a tail current source, and transistor Mn3 can improve the circuit's pressure resistance as a cascode tube of transistor Mn4, and protect transistor Mn4 from damage. The existing structure uses three high-voltage transistors, namely NMOS transistors Mn1, Mn2 and Mn3. The high-voltage transistors will occupy a relatively large chip area, and using high-voltage transistors as input pairs will result in poor matching performance compared to low-voltage transistors, which will further result in relatively large offset voltage and noise contribution equivalent to the input end. In addition, the common-mode rejection ratio (CMRR) of this structure will also be reduced. Summary of the invention

[0005] In view of this, an object of the present invention is to provide an operational amplifier that can not only save chip area, but also reduce the offset voltage and noise equivalent to the input terminal, and improve the common mode rejection ratio of the circuit.

[0006] According to one aspect of the present invention, an operational amplifier is provided, comprising: a first input stage circuit, comprising a first differential pair of PMOS transistors, the first differential pair being used to generate a first differential current signal corresponding to a voltage difference between a positive input signal and a negative input signal; a second input stage circuit, comprising a second differential pair of NMOS transistors, the second differential pair being used to generate a second differential current signal corresponding to a voltage difference between a positive input signal and a negative input signal; an amplifier stage circuit, used to generate a differential output signal according to the first differential current signal or the second differential current signal; an output stage circuit, used to provide an output signal at an output node according to the differential output signal; and a switch circuit, connected between the second input stage circuit and an input terminal of the operational amplifier, used to control whether to activate the second input stage circuit according to an input common mode voltage of the input terminal, wherein when the input common mode voltage is less than a reference voltage, the switch circuit disconnects a connection path between the input terminal of the operational amplifier and the second differential pair, and when the input common mode voltage is greater than the reference voltage, the switch circuit connects a connection path between the input terminal of the operational amplifier and the second differential pair.

[0007] Optionally, within the operating range of the operational amplifier, only one of the first input stage circuit and the second input stage circuit is in an operating state.

[0008] Optionally, the first input stage circuit includes: the first differential pair, including a first PMOS transistor and a second PMOS transistor, the control end of the first PMOS transistor is used to connect to the positive input signal, and the control end of the second PMOS transistor is connected to the negative input signal; a Cascode tube adapted to be connected to the first differential pair, including a third PMOS transistor and a fourth PMOS transistor, the first ends of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the second ends of the first PMOS transistor and the second PMOS transistor, the control ends of the third PMOS transistor and the fourth PMOS transistor are connected to a first bias voltage, and the second ends of the third PMOS transistor and the fourth PMOS transistor are used to output the first differential current signal; and a fifth PMOS transistor and a sixth PMOS transistor connected in series between the power supply voltage and the first ends of the first PMOS transistor and the second PMOS transistor, the control end of the fifth PMOS transistor is connected to the second bias voltage, and the control end of the sixth PMOS transistor is connected to the third bias voltage.

[0009] Optionally, it also includes: a floating ground generating circuit for generating a floating ground voltage as a bias voltage of the switching circuit, wherein the second input stage circuit includes: the second differential pair, including a first NMOS transistor and a second NMOS transistor, the control end of the first NMOS transistor is connected to the positive input signal via the switching circuit, the control end of the second NMOS transistor is connected to the negative input signal via the switching circuit, the first ends of the first NMOS transistor and the second NMOS transistor are used to output the second differential current signal; and a third NMOS transistor connected in series between the second ends of the first NMOS transistor and the second NMOS transistor and the floating ground voltage, the control end of the third NMOS transistor is connected to a fourth bias voltage.

[0010] Optionally, the floating ground generating circuit includes: a first reverse diode, the cathode of the first reverse diode is connected to the power supply voltage; a seventh PMOS transistor constituting a source follower, the first end of the seventh PMOS transistor is connected to the anode of the first reverse diode; an eighth PMOS transistor and a second reverse diode connected in series, the first end of the eighth PMOS transistor is connected to the power supply voltage, the control end and the second end of the eighth PMOS transistor are connected to the cathode of the second reverse diode, and the anode of the second reverse diode is connected to the control end of the seventh PMOS transistor; a first current source, the first current source is connected between the control end of the seventh PMOS transistor and a reference ground; a first resistor, the first resistor is connected between the second end of the seventh PMOS transistor and the reference ground; a first voltage stabilizing capacitor, the first voltage stabilizing capacitor is connected between the power supply voltage and the control end of the seventh PMOS transistor; and a second voltage stabilizing capacitor, the second voltage stabilizing capacitor is connected between the power supply voltage and the first end of the seventh PMOS transistor and outputs the floating ground voltage.

[0011] Optionally, the second input stage circuit also includes: a plurality of fourth NMOS transistors connected in series between the control terminal and the second terminal of the first NMOS transistor, each of the fourth NMOS transistors being connected to form a MOS diode structure; and a plurality of fifth NMOS transistors connected in series between the control terminal and the second terminal of the second NMOS transistor, each of the fifth NMOS transistors being connected to form a MOS diode structure.

[0012] Optionally, substrates of the first NMOS transistor, the second NMOS transistor, the plurality of fourth NMOS transistors, and the plurality of fifth NMOS transistors are connected to the floating ground voltage.

[0013] Optionally, the switching circuit includes: a ninth PMOS transistor, a first end of the ninth PMOS transistor being connected to the positive input signal, a control end of the ninth PMOS transistor being connected to the floating ground voltage, and a second end of the ninth PMOS transistor being connected to the control end of the first NMOS transistor; and a tenth PMOS transistor, a first end of the tenth PMOS transistor being connected to the negative input signal, a control end of the tenth PMOS transistor being connected to the floating ground voltage, and a second end of the tenth PMOS transistor being connected to the control end of the second NMOS transistor.

[0014] Optionally, the amplifier stage circuit includes: at least two groups of common-source and common-gate structures, and the intermediate nodes of the at least two groups of common-source and common-gate structures respectively receive the first differential current signal or the second differential current signal; the output stage circuit includes: a push-pull common-source structure capable of achieving rail-to-rail output, and an output stage bias module that controls the push-pull common-source structure to achieve class AB operation.

[0015] Optionally, the push-pull common source structure includes a PMOS output tube and an NMOS output tube, and the output stage bias module includes: an eleventh PMOS transistor and a twelfth PMOS transistor, the first end of the eleventh PMOS transistor is connected to the control end of the PMOS output tube, the second end of the eleventh PMOS transistor is connected to the first end of the twelfth PMOS transistor, the control end of the twelfth PMOS transistor is connected to a fifth bias voltage, and the second end of the twelfth PMOS transistor is connected to the control end of the NMOS output tube; a sixth NMOS transistor and a seventh NMOS transistor, the first end of the sixth NMOS transistor is connected to the control end of the PMOS output tube, the control end of the sixth NMOS transistor is connected to the sixth bias voltage, and the sixth NMOS transistor is connected to the control end of the NMOS output tube. The second end of the tube is connected to the first end of the seventh NMOS transistor, and the second end of the seventh NMOS transistor is connected to the control end of the NMOS output tube; a thirteenth PMOS transistor, a fourteenth PMOS transistor and a second current source are connected in series between the power supply voltage and the reference ground, the thirteenth PMOS transistor and the fourteenth PMOS transistor are connected to form a MOS diode, and the first end of the second current source is connected to the control end of the eleventh PMOS transistor; and a third current source, an eighth NMOS transistor and a ninth NMOS transistor are connected in series between the power supply voltage and the reference ground, the eighth NMOS transistor and the ninth NMOS transistor are connected to form a MOS diode, and the second end of the third current source is connected to the control end of the seventh NMOS transistor.

[0016] In summary, the operational amplifier of the embodiment of the present invention includes a first input stage circuit having a PMOS differential pair, a second input stage circuit having an NMOS differential pair, and a switch circuit. The switch circuit is used to conduct the connection path between the input terminal of the operational amplifier and the differential pair of the second input stage circuit only when the input common mode voltage is greater than the reference voltage, so that the second input stage circuit does not contribute additional noise and offset voltage when the operational amplifier works normally, and does not affect the common mode rejection ratio of the circuit. In addition, the NMOS differential pair of the second input stage circuit of this embodiment can use low-voltage transistors, which will not increase the area of ​​the circuit additionally, which is conducive to reducing the circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic circuit diagram of an operational amplifier according to the prior art is shown.

[0019] Figure 2 A schematic structural diagram of an operational amplifier according to an embodiment of the present invention is shown.

[0020] Figure 3 FIG. 4 is a schematic circuit diagram of a first input stage circuit according to an embodiment of the present invention.

[0021] Figure 4 FIG. 4 is a schematic circuit diagram showing a second input stage circuit and a switch circuit according to an embodiment of the present invention.

[0022] Figure 5 A schematic circuit diagram of a floating ground generating circuit according to an embodiment of the present invention is shown.

[0023] Figure 6 A schematic circuit diagram showing an amplifier stage circuit and an output stage circuit according to an embodiment of the present invention is shown.

[0024] Figure 7 A schematic circuit diagram of an output stage bias module according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuit, a programmable circuit, a state machine circuit and / or an element that can store instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0027] In the present application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first current terminal, the second current terminal and the control terminal of a P-type MOSFET are the source, the drain and the gate, respectively, and the first current terminal, the second current terminal and the control terminal of an N-type MOSFET are the drain, the source and the gate, respectively.

[0028] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0029] Figure 2 2 shows a schematic structural diagram of an operational amplifier 200 according to an embodiment of the present invention. Figures 3 to 6 The schematic circuit diagrams of the various modules in the operational amplifier 200 of the embodiment of the present invention are shown respectively. Figures 2 to 6 The operational amplifier 200 according to the embodiment of the present invention is described in detail.

[0030] refer to Figure 2 The operational amplifier 200 involved in this embodiment includes a first input stage circuit 210, a second input stage circuit 220, an amplifier stage circuit 230, an output stage circuit 240, a switch circuit 250 and a floating ground generating circuit 260.

[0031] Among them, the first input stage circuit 210 and the second input stage circuit 220 are also called pre-stage circuits, which are generally high-performance differential amplifier circuits with dual-end inputs, and respectively include differential transistor pairs for inputting positive input signals INP and negative input signals INN. The differential transistor pairs are used to amplify the input positive input signals INP and negative input signals INN, thereby outputting a differential current signal corresponding to the voltage difference between the positive input signal INP and the negative input signal INN to the amplifier stage circuit 220.

[0032] Furthermore, the transistor types of the differential transistor pairs included in the first input stage circuit 210 and the second input stage circuit 220 of this embodiment are different. For example, when the first input stage circuit 210 includes PMOS transistors, the second input stage circuit 220 includes NMOS transistors; when the first input stage circuit includes NMOS transistors, the second input stage circuit 220 includes PMOS transistors.

[0033] In one embodiment, the first input stage circuit 210 includes two P-type (i.e., P-channel) metal oxide semiconductor field effect transistors (i.e., PMOS) Mp1 and Mp2, and can operate in a relatively low input voltage range, and the second input stage circuit 220 includes two N-type (i.e., N-channel) metal oxide semiconductor field effect transistors (i.e., NMOS), and can operate in a relatively high input voltage range. Each differential transistor pair is biased by a bias current at the source of the transistors connected together, and when connected to the input node, the two gates of the selected differential transistor pair are connected to the differential input terminals (i.e., INP and INN) of the operational amplifier, and the output of the differential transistor pair is at the drain.

[0034] The switch circuit 250 is used to be connected between the differential input terminal of the operational amplifier and the second input stage circuit 220, and activate the second input stage circuit 220 according to the input common mode voltage at the input. For example, when the input common mode voltage of the operational amplifier is less than the reference voltage, the switch circuit 250 disconnects the path between the second input stage circuit 220 and the input terminal, so that the second input stage circuit 220 does not work; and when the input voltage is greater than the reference voltage, the switch circuit 250 conducts the path between the second input stage circuit 220 and the input terminal, so that the second input stage circuit 220 is activated. By setting the switch circuit 250, the second input stage circuit 220 can be used as an "auxiliary input stage circuit" of the first input stage circuit 210. When the input common mode voltage is within the normal application range, the first input stage circuit 210 works normally, and the second input stage circuit 220 will not be activated, so that it will not contribute additional noise and offset voltage in the circuit, and will not affect the common mode rejection ratio of the circuit. In addition, the differential transistor pair in the second input stage circuit 220 can use low-voltage transistors, which will not increase the area of ​​the circuit. Only when the input common-mode voltage exceeds the normal application range, the first input stage circuit 210 cannot work normally, and the second input stage circuit 220 will be activated at this time, ensuring that the output polarity of the operational amplifier can still be correct when the PMOS main input pair cannot work.

[0035] The floating ground generating circuit 260 is used to output a floating ground voltage V to the operational amplifier. HGNDAs the floating ground of the power rail of the operational amplifier. In one embodiment, the floating ground voltage V generated by the floating ground generating circuit 260 is HGND =VCC-5V (wherein VCC is the power supply voltage of the circuit). In addition, the floating ground generating circuit 260 is also used to provide the floating ground voltage V to the switch circuit 250. HGND , as the bias voltage of the switch circuit 250. In one embodiment, the floating ground voltage V HGND The reference voltage is adjusted according to the voltage value of the reference voltage, thereby changing the operating voltage range of the second input stage circuit 220.

[0036] In this embodiment, the first input stage circuit 210 may adopt Figure 3 As shown in the structure, the second input stage circuit 220 and the switch circuit 250 can adopt Figure 4 The structure shown. Figure 3 As shown, the first input stage circuit 210 includes PMOS transistors Mp1 to Mp6. Among them, PMOS transistors Mp1 and Mp2 constitute a differential transistor pair of the first input stage circuit 210, the gate of PMOS transistor Mp1 is connected to the positive input signal INP, and the gate of PMOS transistor Mp2 is connected to the negative input signal INN. PMOS transistors Mp3 and Mp4 constitute a cascode high-voltage tube of the differential transistor pair Mp1 and Mp2, which is used to improve the circuit's pressure resistance, the source of PMOS transistor Mp3 is connected to the drain of PMOS transistor Mp1, the source of PMOS transistor Mp4 is connected to the drain of PMOS transistor Mp2, the gates of PMOS transistors Mp3 and Mp4 are connected to the bias voltage VP3, and the drains of PMOS transistors Mp3 and Mp4 are respectively connected to the differential nodes A and B of the amplifier stage circuit 230 to provide it with differential current signals Ia and Ib after amplification. PMOS transistors Mp5 and Mp6 are connected in series between the power supply voltage VCC and the sources of PMOS transistors Mp1 and Mp2. The gate of PMOS transistor Mp5 is used to input bias voltage VP1, and the gate of PMOS transistor Mp6 is used to input bias voltage VP1C. PMOS transistor Mp5 is used as a tail current source to provide a current corresponding to bias voltage VP1 to PMOS transistors Mp1 and Mp2. PMOS transistor Mp6 is a cascode high-voltage tube of PMOS transistor Mp5, which is used to improve the circuit's ability to withstand high voltage.

[0037] like Figure 4As shown, the second input stage circuit 220 includes NMOS transistors Mn1 to Mn3. Among them, the NMOS transistors Mn1 and Mn2 constitute a differential transistor pair of the second input stage circuit 220, the gate of the NMOS transistor Mn1 is connected to the positive input signal INP through the switch circuit 250, and the gate of the NMOS transistor Mn2 is connected to the negative input signal INN through the switch circuit 250. The drain of the NMOS transistor Mn3 is connected to the source of the NMOS transistors Mn1 and Mn2, and the source of the NMOS transistor Mn3 is connected to the floating ground voltage V HGND The gate of the NMOS transistor Mn3 is used to input the bias voltage VN1, and the NMOS transistor Mn3 is used as a tail current source for providing a current corresponding to the bias voltage VN1 to the NMOS transistors Mn1 and Mn2. The drains of the NMOS transistors Mn1 and Mn2 are respectively connected to the differential nodes C and D of the amplifier stage circuit 230 to provide the differential current signals Ic and Id after amplification. In this embodiment, the input signal can be a voltage signal, such as Figure 3 and Figure 4 The input voltages INP and INN are shown; in other embodiments, the input signal may also be a signal in other forms (for example, a current signal), and the input signal in other forms may be converted into a voltage signal by a voltage conversion device.

[0038] In this embodiment, the switch circuit 250 can be implemented by a plurality of MOS transistors. Figure 4 As shown, the switch circuit 250 includes PMOS transistors Mp7 and Mp8, the drain of the PMOS transistor Mp7 is connected to the positive input signal INP, the source of the PMOS transistor Mp7 is connected to the gate of the NMOS transistor Mn1, the drain of the PMOS transistor Mp8 is connected to the negative input signal INN, the source of the PMOS transistor Mp8 is connected to the gate of the NMOS transistor Mn2, and the gates of the PMOS transistors Mp7 and Mp8 are connected to the floating ground voltage V HGND In this embodiment, the PMOS transistors Mp7 and Mp8 can be implemented by high-voltage transistors. When the input common-mode voltage is less than the reference voltage (ie, V HGND +V GS , where V GS When the input common mode voltage is greater than the reference voltage (i.e., V HGND +V GS), PMOS transistors Mp7 and Mp8 are turned on. As the input common-mode voltage continues to rise, when the source voltages of NMOS transistors Mn1 and Mn2 rise to a level that enables NMOS transistor M3 to provide tail current, NMOS transistors Mn1 and Mn2 can distribute the tail current according to the voltages of the differential input terminals INP and INN, thereby participating in the polarity judgment of the operational amplifier.

[0039] In addition, in this embodiment, the tail current transistor Mn3 in the second input stage circuit 220 operates at a floating ground voltage V HGND The voltage rail is not the reference ground voltage VSS voltage rail, so that all transistors in the second input stage circuit 220 operate at VCC~V HGND Within the voltage range, the use of high-voltage cascode transistors can be avoided, which is beneficial to further reduce the circuit area.

[0040] Furthermore, in order to avoid the problem that the gate terminal voltage of the differential transistor pair Mn1 and Mn2 is too low when the input common-mode voltage is lower than the reference voltage, resulting in device damage, the second input stage circuit 220 also includes a plurality of clamping transistors Mn4 to Mn7. Among them, the plurality of clamping transistors Mn4 to Mn7 are implemented by NMOS transistors, and the NMOS transistors Mn4 and Mn5 are connected in series between the gate and source of the NMOS transistor Mn1, and the gates and drains of the NMOS transistors Mn4 and Mn5 are short-circuited together to form a MOS diode structure. The NMOS transistors Mn6 and Mn7 are connected in series between the gate and source of the NMOS transistor Mn2, and the NMOS transistors Mn6 and Mn7 are also connected to form a MOS diode structure. The substrates of the NMOS transistors Mn4 to Mn7 are all connected to the floating ground voltage V HGND on, through its parasitic body diode (i.e., Figure 4 The diodes D1 and D2 (shown by the dashed lines) clamp the gate voltages of the NMOS transistors Mn1 and Mn2 to V HGND -0.7V. At the same time, when the input common-mode voltage is low, since the PMOS transistors Mp7 and Mp8 are turned off, the NMOS transistors Mn4 to Mn7 will not consume current in the circuit. Therefore, when the input common-mode voltage is low, the gate voltage of the NMOS transistors Mn1 and Mn2 will be limited to (V HGND +V GS ~V HGND -0.7V) range, thus ensuring that the NMOS transistors Mn1 and Mn2 will not be damaged and improving the stability of the circuit.

[0041] Furthermore, in this embodiment, the substrates of the differential transistor pair Mn1 and Mn2 in the second input stage circuit 220 may also be connected to the floating ground voltage V HGND Thus, the differential transistor pair Mn1 and Mn2 and the clamp transistors Mn4 to Mn7 can be connected in the same loop, saving circuit area.

[0042] It can be seen that compared with the prior art, the present application uses only two high-voltage transistors Mp7 and Mp8, which can reduce the use of one high-voltage transistor, and the differential transistor pair and the clamping transistor in the second input stage circuit 220 can be connected to the floating ground voltage V HGND The MOS tubes are placed in a ring, which can avoid the substrates of the low-voltage transistors Mn1 and Mn2 of the second input stage circuit being independent of all other low-voltage MOS tubes, because doing so in a high-voltage process would result in a large area overhead, so the present application can greatly reduce the area and cost of the circuit. In addition, the area of ​​the differential transistor pair in the second input stage circuit 220 of the present application can be smaller than that of the prior art, and the size selection is more flexible, and will not contribute additional power consumption in the circuit. In addition, by reasonably controlling the value of the reference level, the second input stage circuit of the present application will not contribute additional noise and offset voltage in the circuit, nor will it affect the common mode rejection ratio of the circuit.

[0043] It should be noted that the low-voltage MOS transistors and high-voltage MOS transistors in this article are generally relative. For example, transistors can be divided into high-voltage transistors or low-voltage transistors according to the turn-on threshold of the MOS transistor. For example, the turn-on threshold of the low-voltage MOS transistor is generally around 0.7V, while the turn-on threshold of the high-voltage MOS transistor is generally around 1.2V.

[0044] Furthermore, if Figure 5 The floating ground generating circuit of the present invention is shown in a circuit schematic diagram, which aims to generate a floating ground voltage V that is 5V lower than the power supply voltage VCC. HGND , so that the power supply voltage VCC and the floating ground voltage V HGND The second input stage circuit can be designed using ordinary CMOS circuits. Figure 5As shown, the floating ground generating circuit 260 includes PMOS transistors Mp9 and Mp10, capacitors C1 and C2, diodes D3 and D4, a current source I1, and a resistor R1. Among them, the PMOS transistor Mp9, the diode D3, and the current source I1 are connected between the power supply voltage VCC and the ground, and the PMOS transistor Mp9 is connected to form a MOS diode structure, that is, the source of the PMOS transistor Mp9 is connected to the power supply voltage VCC, the gate and drain of the PMOS transistor Mp9 are connected to the cathode of the diode D3, the anode of the diode D3 is connected to the first end of the current source I1, and the second end of the current source I1 is connected to the ground. The cathode of the diode D4 is connected to the power supply voltage VCC, the anode is connected to the source of the PMOS transistor Mp10, the gate of the PMOS transistor Mp10 is connected to the node A1 between the diode D3 and the current source I1, the drain of the PMOS transistor Mp10 is connected to the first end of the resistor R1, and the second end of the resistor R1 is connected to the ground. The capacitor C1 is connected between the power supply voltage VCC and the gate of the PMOS transistor Mp10, and the capacitor C2 is connected between the power supply voltage VCC and the source of the PMOS transistor Mp10, and outputs a floating ground voltage V HGND .

[0045] exist Figure 5 In the circuit, the PMOS transistor Mp10 is a source follower transistor, which is generally a high-voltage PMOS transistor. The capacitors C1 and C2 are voltage-stabilizing capacitors. The diodes D3 and D4 are Zener diodes. When the power supply voltage VCC is higher than about 6.5V, the diode D3 is in a reverse bias state, and its reverse bias voltage is about 5.5V. Therefore, the voltage of the A1 node can be VCC-5.5V-Vgs_Mp9. After passing through the source follower transistor Mp10, a low-voltage floating ground V of about VCC-5V can be obtained. HGND . Diode D4 is used to clamp and ensure V HGND It will not be too much lower than VCC.

[0046] Continue to refer Figure 2, the operational amplifier 200 of the present application also includes an amplifier stage circuit 230 and an output stage circuit 240. Among them, the amplifier stage circuit 230 is the main amplifier circuit of the operational amplifier, and its function is to obtain a pair of differential output signals Pgate and Ngate according to the two differential current signals provided by the first input stage circuit 210 or the second input stage circuit 220. The output stage circuit 240 receives the differential output signals Pgate and Ngate, and realizes rail-to-rail output. For example, the output stage circuit 240 can adopt a push-pull common source structure that can provide an output of approximately full swing, and its biasing method adopts a floating bias structure of Class AB. Specifically, the floating bias structure of Class AB is used to control the static operating current of the push-pull common source structure and realize the AB class working mode, so that the push-pull common source output structure can provide a rail-to-rail output signal OUT according to the two output signals Pgate and Ngate provided by the amplifier stage circuit 230.

[0047] Furthermore, the class AB working mode is to have a smaller static current flowing through the output stage circuit in static state, and to be able to output a larger current to the load in dynamic state, and to have a higher output efficiency and smaller crossover distortion.

[0048] Figure 6 Schematic circuit diagram of an amplifier stage circuit and an output stage circuit according to an embodiment of the present invention is shown. Figure 6As shown, the amplifier stage circuit 230 includes four groups of common source and common gate structure circuits, which are Mn8, Mn9, Mn10 and Mn11 of NMOS transistor type and Mp11, Mp12, Mp13 and Mp14 of PMOS transistor type. Among them, the gates of PMOS transistors Mp11 and Mp12 are connected to the bias voltage VP2, the gates of PMOS transistors Mp13 and Mp14 are connected to the bias voltage VP2C, the gates of NMOS transistors Mn8 and Mn9 are connected to the bias voltage VN2, and the gates of NMOS transistors Mn10 and Mn11 are connected to the drain of NMOS transistor Mn8. The sources of the PMOS transistors Mp11 and Mp12 are connected to the power supply voltage VCC, the drains of the PMOS transistors Mp11 and Mp12 are connected to the sources of the PMOS transistors Mp13 and Mp14, respectively, and there are differential nodes C and D connected to the differential transistor pair in the second input stage circuit 220 between the PMOS transistors Mp12 and Mp14 and between the PMOS transistors Mp11 and Mp13, respectively, and the drain of the PMOS transistor Mp14 is used to provide an output signal Pgate to the output stage circuit 240. The sources of the NMOS transistors Mn10 and Mn11 are connected to the ground VSS, the drains of the NMOS transistors Mn10 and Mn11 are connected to the sources of the NMOS transistors Mn8 and Mn9, respectively, and there are differential nodes A and B connected to the differential transistor pair in the first input stage circuit 210 between the NMOS transistors Mn9 and Mn11 and between the NMOS transistors Mn8 and Mn10, respectively, the drain of the NMOS transistor Mn8 is connected to the drain of the PMOS transistor Mp13 via the high-voltage PMOS transistor Mp15, and the drain of the NMOS transistor Mn9 is used to provide an output signal Ngate to the output stage circuit 240. The gate of the PMOS transistor Mp15 is connected to the bias voltage VP3.

[0049] The output stage circuit 240 includes a PMOS output tube Mpout and an NMOS output tube Mnout which are sequentially connected in series to the power supply voltage VCC, the gate of the PMOS output tube Mpout is connected to the signal Pgate, the gate of the NMOS output tube Mnout is connected to the signal Ngate, and the intermediate node of the output tubes Mpout and Mnout is used to provide the output signal OUT. The output stage circuit 240 also includes an output stage bias module 241, which is used to provide a gate bias signal to the output tubes Mpout and Mnout to control the size of the static current of the push-pull common source structure and realize the AB class working mode.

[0050] Figure 7 FIG. 2 shows a schematic circuit diagram of an output stage bias module according to an embodiment of the present invention. Figure 7As shown, the output stage bias module 241 includes current sources IBP and IBN, PMOS transistors Mp16 to Mp19, and NMOS transistors Mn12 to Mn15. Among them, NMOS transistor Mn15 and PMOS transistor Mp18 are floating bias structures composed of parallel NMOS and PMOS, current source IBP and PMOS transistors Mp16 and Mp17 form a bias circuit of PMOS transistor Mp18, current source IBN and NMOS transistors Mn12 and Mn13 form a bias circuit of NMOS transistor Mn15, PMOS transistor Mp19 and NMOS transistor Mn14 are high-voltage transistors, which mainly improve the circuit's pressure resistance. Specifically, the source of the PMOS transistor Mp18 is connected to the gate of the PMOS output tube Mpout and the differential output signal Pgate, the drain of the PMOS transistor Mp18 is connected to the source of the PMOS transistor Mp19, the drain of the PMOS transistor Mp19 is connected to the gate of the NMOS output tube Mnout and the differential output signal Ngate, and the gate of the PMOS transistor Mp19 is connected to the bias voltage VP3. The drain of the NMOS transistor Mn14 is connected to the PMOS output tube Mpout and the differential output signal Pgate, the gate of the NMOS transistor Mn14 is connected to the bias voltage VN3, the source of the NMOS transistor Mn14 is connected to the drain of the NMOS transistor Mn15, and the source of the NMOS transistor Mn15 is connected to the gate of the NMOS output tube Mnout and the differential output signal Ngate. PMOS transistors Mp16 and Mp17 are connected to form a MOS diode structure and are connected in series with a current source IBP between the power supply voltage VCC and the ground. One end of the current source IBP is connected to the gate of the PMOS transistor Mp18 to provide a bias voltage thereto. NMOS transistors Mn12 and Mn13 are connected to form a MOS diode structure and are connected to a current source IBN between the power supply voltage VCC and the ground. One end of the current source IBN is connected to the gate of the NMOS transistor Mn15 to provide a bias voltage thereto. Figure 7 Among them, PMOS transistors Mp16 and Mp19, NMOS transistors Mn13 and Mn14 are high-voltage transistors, and the remaining transistors are low-voltage transistors.

[0051] It is understandable that the operational amplifier provided in the embodiment of the present invention can be used in different application scenarios. In other circuits of the present invention, a chip is also provided, and the chip is, for example, an integrated circuit chip such as an audio power amplifier chip or a radio frequency chip. The operational amplifier provided in the embodiment of the present invention can be integrated into the chip. The specific structure of the operational amplifier in the integrated circuit chip is not described in detail here.

[0052] In addition, the above-mentioned operational amplifier with wide swing input and output can also be used in electronic devices as an important component of radio frequency integrated circuits or audio power amplifier circuits. Among them, the electronic devices mentioned here refer to devices that can be used in mobile environments and support multiple communication formats such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, including mobile phones, laptops, tablet computers, car computers, etc. In addition, the technical solution provided by the present invention is also applicable to other occasions where radio frequency integrated circuits are applied, such as communication base stations, etc.

[0053] In summary, the operational amplifier of the embodiment of the present invention includes a first input stage circuit having a PMOS differential pair, a second input stage circuit having an NMOS differential pair, and a switch circuit. The switch circuit is used to conduct the connection path between the input terminal of the operational amplifier and the differential pair of the second input stage circuit only when the input common mode voltage is greater than the reference voltage, so that the second input stage circuit does not contribute additional noise and offset voltage when the operational amplifier works normally, and does not affect the common mode rejection ratio of the circuit. In addition, the NMOS differential pair of the second input stage circuit of this embodiment can use low-voltage transistors, which will not increase the area of ​​the circuit additionally, which is conducive to reducing the circuit cost.

[0054] Furthermore, the tail current transistor in the second input stage circuit of this embodiment operates at a floating ground voltage V HGND voltage rail, rather than the reference ground voltage VSS voltage rail, so that all transistors in the second input stage circuit operate at VCC~V HGND Within the voltage range, the use of high-voltage cascode transistors can be avoided, which is beneficial to further reduce the circuit area.

[0055] Furthermore, the second input stage circuit of this embodiment also includes a plurality of clamping transistors connected between the gate and source of the NMOS differential pair. The gate voltage of the NMOS differential pair is clamped near a set value by the clamping transistors, thereby ensuring that the NMOS differential pair will not be damaged when the input common-mode voltage is low, which is beneficial to improving the stability of the circuit.

[0056] It should be noted that although in this article, the device is described as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, it can be understood by those skilled in the art that complementary devices can also be realized according to the present invention. It can be understood by those skilled in the art that the conductivity type refers to the mechanism by which the conduction occurs, such as conduction by holes or electrons, so the conductivity type does not involve the doping concentration but the doping type, such as P-type or N-type. It can be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating the action that occurs immediately when the start-up action begins, but there may be some small but reasonable one or more delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It is well established in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the desired goal of exactness as described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

[0057] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0058] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. An operational amplifier, comprising: A first input stage circuit, comprising a first differential pair of PMOS transistors, the first differential pair being used to generate a first differential current signal corresponding to a voltage difference between a positive input signal and a negative input signal; A second input stage circuit, comprising a second differential pair of NMOS transistors, the second differential pair being used to generate a second differential current signal corresponding to a voltage difference between a positive input signal and a negative input signal; an amplifier stage circuit, configured to generate a differential output signal according to the first differential current signal or the second differential current signal; an output stage circuit, configured to provide an output signal at an output node according to the differential output signal; as well as a switch circuit, connected between the second input stage circuit and the input terminal of the operational amplifier, and used to control whether to activate the second input stage circuit according to the input common mode voltage of the input terminal, Among them, when the input common-mode voltage is less than the reference voltage, the switch circuit disconnects the connection path between the input end of the operational amplifier and the second differential pair, and when the input common-mode voltage is greater than the reference voltage, the switch circuit connects the connection path between the input end of the operational amplifier and the second differential pair.

2. The operational amplifier according to claim 1, wherein: Within the operating range of the operational amplifier, only one of the first input stage circuit and the second input stage circuit is in an operating state.

3. The operational amplifier according to claim 1, wherein: The first input stage circuit comprises: The first differential pair includes a first PMOS transistor and a second PMOS transistor, wherein the control terminal of the first PMOS transistor is used to be connected to the positive input signal, and the control terminal of the second PMOS transistor is connected to the negative input signal; a cascode transistor adapted to be connected to the first differential pair, comprising a third PMOS transistor and a fourth PMOS transistor, wherein first ends of the third PMOS transistor and the fourth PMOS transistor are respectively connected to second ends of the first PMOS transistor and the second PMOS transistor, control ends of the third PMOS transistor and the fourth PMOS transistor are connected to a first bias voltage, and second ends of the third PMOS transistor and the fourth PMOS transistor are used to output the first differential current signal; and A fifth PMOS transistor and a sixth PMOS transistor are connected in series between a power supply voltage and the first ends of the first PMOS transistor and the second PMOS transistor, a control end of the fifth PMOS transistor is connected to a second bias voltage, and a control end of the sixth PMOS transistor is connected to a third bias voltage.

4. The operational amplifier according to claim 1, wherein: Also includes: A floating ground generating circuit is used to generate a floating ground voltage to serve as a bias voltage of the switch circuit. Wherein, the second input stage circuit comprises: the second differential pair comprises a first NMOS transistor and a second NMOS transistor, the control end of the first NMOS transistor is connected to the positive input signal via the switch circuit, the control end of the second NMOS transistor is connected to the negative input signal via the switch circuit, and the first ends of the first NMOS transistor and the second NMOS transistor are used to output the second differential current signal; and A third NMOS transistor is connected in series between the second terminals of the first NMOS transistor and the second NMOS transistor and the floating ground voltage, and a control terminal of the third NMOS transistor is connected to a fourth bias voltage.

5. The operational amplifier according to claim 4, wherein: The floating ground generating circuit comprises: a first reverse-connected diode, wherein a cathode of the first reverse-connected diode is connected to a power supply voltage; a seventh PMOS transistor constituting a source follower, wherein a first terminal of the seventh PMOS transistor is connected to an anode of the first reverse diode; an eighth PMOS transistor and a second reverse diode connected in series, wherein a first terminal of the eighth PMOS transistor is connected to the power supply voltage, a control terminal and a second terminal of the eighth PMOS transistor are connected to a cathode of the second reverse diode, and an anode of the second reverse diode is connected to the control terminal of the seventh PMOS transistor; A first current source, the first current source is connected between the control terminal of the seventh PMOS transistor and a reference ground; a first resistor, wherein the first resistor is connected between the second end of the seventh PMOS transistor and the reference ground; A first voltage stabilizing capacitor connected between the power supply voltage and the control terminal of the seventh PMOS transistor; and A second voltage-stabilizing capacitor is connected between the power supply voltage and the first end of the seventh PMOS transistor and outputs the floating ground voltage.

6. The operational amplifier according to claim 4, wherein: The second input stage circuit further includes: a plurality of fourth NMOS transistors connected in series between the control terminal and the second terminal of the first NMOS transistor, each of the fourth NMOS transistors being connected to form a MOS diode structure; and A plurality of fifth NMOS transistors are connected in series between the control terminal and the second terminal of the second NMOS transistor, and each of the fifth NMOS transistors is connected to form a MOS diode structure.

7. The operational amplifier according to claim 6, wherein: Substrates of the first NMOS transistor, the second NMOS transistor, the fourth NMOS transistors, and the fifth NMOS transistors are connected to the floating ground voltage.

8. The operational amplifier according to claim 5, wherein: The switch circuit comprises: a ninth PMOS transistor, a first terminal of the ninth PMOS transistor being connected to the positive input signal, a control terminal of the ninth PMOS transistor being connected to the floating ground voltage, and a second terminal of the ninth PMOS transistor being connected to the control terminal of the first NMOS transistor; and A tenth PMOS transistor, wherein a first terminal of the tenth PMOS transistor is connected to the negative input signal, a control terminal of the tenth PMOS transistor is connected to the floating ground voltage, and a second terminal of the tenth PMOS transistor is connected to the control terminal of the second NMOS transistor.

9. The operational amplifier according to claim 1, wherein: The amplifier stage circuit comprises: at least two groups of common-source and common-gate structures, wherein intermediate nodes of the at least two groups of common-source and common-gate structures respectively receive the first differential current signal or the second differential current signal, The output stage circuit comprises: a push-pull common source structure capable of realizing rail-to-rail output, and an output stage bias module for controlling the push-pull common source structure to realize a class AB working mode.

10. The operational amplifier according to claim 9, wherein: The push-pull common source structure includes a PMOS output tube and an NMOS output tube, and the output stage bias module includes: an eleventh PMOS transistor and a twelfth PMOS transistor, wherein a first end of the eleventh PMOS transistor is connected to the control end of the PMOS output tube, a second end of the eleventh PMOS transistor is connected to a first end of the twelfth PMOS transistor, a control end of the twelfth PMOS transistor is connected to a fifth bias voltage, and a second end of the twelfth PMOS transistor is connected to the control end of the NMOS output tube; a sixth NMOS transistor and a seventh NMOS transistor, wherein a first end of the sixth NMOS transistor is connected to the control end of the PMOS output tube, the control end of the sixth NMOS transistor is connected to a sixth bias voltage, a second end of the sixth NMOS transistor is connected to the first end of the seventh NMOS transistor, and a second end of the seventh NMOS transistor is connected to the control end of the NMOS output tube; a thirteenth PMOS transistor, a fourteenth PMOS transistor and a second current source connected in series between a power supply voltage and a reference ground, the thirteenth PMOS transistor and the fourteenth PMOS transistor being connected to form a MOS diode, and a first end of the second current source being connected to a control end of the eleventh PMOS transistor; and A third current source, an eighth NMOS transistor and a ninth NMOS transistor are connected in series between the power supply voltage and the reference ground, the eighth NMOS transistor and the ninth NMOS transistor are connected to form a MOS diode, and the second end of the third current source is connected to the control end of the seventh NMOS transistor.

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