BMC signal receiving circuit and device

Abstract

The invention discloses a BMC (Baseboard Management Controller) signal receiving circuit and a BMC signal receiving device, which are used for overcoming the noise interference problem in the BMC signal receiving process and improving the BMC signal receiving efficiency. The circuit comprises a reference voltage circuit, a first low-pass filter circuit and a hysteresis comparator circuit. Inputting the BMC signal to a first low-pass filter circuit, and filtering the BMC signal by the first low-pass filter circuit; the hysteresis comparator circuit obtains the voltage of the filtered BMC signal and a target reference voltage output by the reference voltage circuit, compares the two voltages, outputs a level signal according to a comparison result, and feeds back the level signal to the reference voltage circuit; wherein the target reference voltage is one of two switchable reference voltages set by the reference voltage circuit; the reference voltage circuit detects whether the level of the level signal changes or not, if yes, the output target reference voltage is switched into the other reference voltage in the two reference voltages, and if not, the output target reference voltage is kept.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a BMC signal receiving circuit and device. Background Art

[0002] When the charger is connected to the POS device for BMC signal transmission, it is very susceptible to noise interference, which directly causes glitches or abnormal fluctuations in the BMC signal captured by the POS device, reducing the purity and stability of the BMC signal. In addition, when the charging cable of the charger transmits power efficiently, it will generate electromagnetic fields, which may cause the signal to drift on the ground plane, resulting in deviations in the voltage value captured by the POS device, causing BMC signal distortion.

[0003] It is difficult for existing POS devices on the market to eliminate these problems of abnormal BMC signal reception, which greatly reduces the transmission efficiency and accuracy of BMC signals received by POS devices, thereby reducing the user's charging experience. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a BMC signal receiving circuit and device, which are used to overcome the noise interference problem in the process of receiving BMC signals and improve the receiving efficiency of BMC signals.

[0005] The technical solution provided in this application is described below:

[0006] The first aspect of the present application provides a BMC signal receiving circuit, including:

[0007] A reference voltage circuit, a first low-pass filter circuit and a hysteresis comparator circuit;

[0008] Inputting the BMC signal to a first low-pass filter circuit, the first low-pass filter circuit filters the BMC signal, and inputting the filtered BMC signal to a hysteresis comparator circuit;

[0009] The hysteresis comparator circuit obtains the voltage of the filtered BMC signal and the target reference voltage outputted thereto by the reference voltage circuit, compares the voltage of the filtered BMC signal with the target reference voltage, outputs a level signal according to the comparison result, and feeds the level signal back to the reference voltage circuit, wherein the target reference voltage is one of two switchable reference voltages set by the reference voltage circuit;

[0010] The reference voltage circuit detects whether the level of the level signal changes. If so, the output target reference voltage is switched to the other of the two reference voltages; otherwise, the output target reference voltage is maintained.

[0011] Optionally, the first low-pass filter circuit includes a resistor R2 and a capacitor C2;

[0012] The BMC signal is input to one end of the resistor R2, the other end of the resistor R2 is connected in series with one end of the capacitor C2, and the other end of the capacitor C2 is grounded; an output end is provided at the connection between the resistor R2 and the capacitor C2, and the output end is connected to the hysteresis comparator circuit.

[0013] Optionally, the hysteresis comparator circuit includes a PMOS tube M3, a PMOS tube M4, a PMOS tube M9, a PMOS tube M11, an NMOS tube M5, an NMOS tube M6, an NMOS tube M8, an NMOS tube M10 and an NMOS tube M12;

[0014] The target reference voltage is input to the gate of the PMOS tube M3, and the filtered BMC signal is input to the gate of the PMOS tube M4;

[0015] The source of the PMOS tube M3 is connected to the source of the PMOS tube M4, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the gate of the NMOS tube M5 and the gate of the NMOS tube M6, and the sources of the NMOS tubes M5 and M6 are grounded;

[0016] The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M8, and the source of the NMOS tube M8 is grounded;

[0017] The drain of the NMOS tube M8 is connected to the gate of the PMOS tube M9 and the gate of the NMOS tube M10; the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10, and an output terminal RX_N is provided at the intersection, and the output terminal RX_N is connected to the gates of the PMOS tube M11 and the NMOS tube M12; the drain of the PMOS tube M11 and the drain of the NMOS tube M12 are connected, and an output terminal RX is provided at the intersection; the level signal is fed back to the reference voltage circuit through the output terminal RX_N and the output terminal RX; the sources of the NMOS tubes M10 and M12 are both grounded;

[0018] Optionally, the reference voltage circuit includes an NMOS tube M13 and an NMOS tube M14; the level signal includes a first level signal and a second level signal;

[0019] A reference voltage is input to the drain of the NMOS tube M13, and another reference voltage is input to the drain of the NMOS tube M14; after the first level signal is input to the PMOS tube M11 and the NMOS tube M12, it is converted into a second level signal;

[0020] The first level signal is input to the gate of the NMOS tube M13 through the output terminal RX_N, and the second level signal is input to the gate of the NMOS tube M14 through the output terminal RX;

[0021] The source of the NMOS transistor M13 and the source of the NMOS transistor M14 output the target reference voltage to the hysteresis comparator circuit.

[0022] Optionally, a second low-pass filter circuit is connected between the reference voltage circuit and the hysteresis comparator circuit;

[0023] The second low-pass filter circuit includes a resistor R1 and a capacitor C1, the target reference voltage is input to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; an output end is provided at the connection between the resistor R1 and the capacitor C1, and the output end is connected to the hysteresis comparator circuit.

[0024] Optionally, the BMC signal receiving circuit further includes a bias circuit for providing a driving voltage and a driving current for all circuits;

[0025] The bias circuit includes: a bias current source I_bias, a PMOS tube M1, a PMOS tube M2 and a PMOS tube M7;

[0026] One end of the bias current source I_bias is connected to the drain of the PMOS tube M1, the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the gate of the PMOS tube M7; the other end of the bias current source I_bias is connected to the ground;

[0027] The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and the source of the PMOS tube M7;

[0028] The drain of the PMOS tube M2 is connected to the source of the PMOS tube M3 and the source of the PMOS tube M4; the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M8, the gate of the PMOS tube M9 and the gate of the NMOS tube M10.

[0029] Optionally, the reference voltage includes a 0.33V voltage and a 0.48V voltage.

[0030] A second aspect of the present application provides a BMC signal receiving device, including:

[0031] A reference voltage unit, used for switching between two reference voltages and outputting a target reference voltage;

[0032] A first filtering unit, used for filtering the BMC signal and inputting the filtered BMC signal to the comparator unit;

[0033] The comparator unit is used to compare the voltage of the filtered BMC signal with the target reference voltage and output a level signal according to the comparison result.

[0034] It can be seen from the above technical solutions that this application has the following advantages:

[0035] The first low-pass filter circuit can filter out the noise in the BMC signal and remove the glitches or abnormal fluctuations in the BMC signal during transmission, thereby ensuring the integrity of the BMC signal; the reference voltage circuit can realize automatic switching of two reference voltages according to the output level; at the same time, the hysteresis comparator circuit solves the problem of signal reflection, crosstalk or ground plane drift during efficient transmission of electric energy through its unique hysteresis characteristics, thereby ensuring accurate transmission and reception of signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A flow chart of an embodiment of a BMC signal receiving circuit provided by the present application;

[0038] Figure 2 The schematic diagram of the BMC signal receiving circuit provided by this application;

[0039] Figure 3 This is a schematic diagram of the structure of the BMC signal receiving device provided in this application. DETAILED DESCRIPTION

[0040] It should be noted that the BMC signal receiving circuit provided in this application can be applied to a terminal or a system, for example, the terminal can be a smart phone or a computer, a tablet computer, a smart TV, a smart watch, a portable computer terminal or a fixed terminal such as a desktop computer. For the convenience of explanation, this application uses the terminal as an example for explanation.

[0041] See also Figure 1 , Figure 1 An embodiment of a BMC signal receiving circuit provided in the present application includes:

[0042] S101, inputting a BMC signal to a first low-pass filter circuit, the first low-pass filter circuit filters the BMC signal, and inputting the filtered BMC signal to a hysteresis comparator circuit;

[0043] The original BMC signal contains signals of various frequency components, including useful signals and noise. The function of the first low-pass filter circuit is to filter the BMC signal to remove high-frequency noise and interference therein.

[0044] First, the BMC signal is input into the first low-pass filter circuit. After filtering, a filtered BMC signal is obtained. The filtered BMC signal is smoother and has lower noise content, providing a more accurate signal source for subsequent comparison and conversion signals.

[0045] S102, the hysteresis comparator circuit obtains the voltage of the filtered BMC signal and the target reference voltage outputted thereto by the reference voltage circuit, compares the voltage of the filtered BMC signal with the target reference voltage, outputs a level signal according to the comparison result, and feeds the level signal back to the reference voltage circuit, wherein the target reference voltage is one of two switchable reference voltages set by the reference voltage circuit;

[0046] The hysteresis comparator circuit is a comparator circuit with hysteresis characteristics, which can still produce a stable output state when the input signal changes; the function of the reference voltage circuit is to select a suitable target reference voltage output. In this application, two reference voltages are set, and a suitable reference voltage is selected as the target reference voltage. The target reference voltage is dynamically switched according to the output level signal. Different target reference voltages are selected to compare with the BMC signal to determine the state of the BMC signal.

[0047] After the first low-pass filter circuit filters the BMC signal, the hysteresis comparator circuit obtains the voltage of the filtered BMC signal and the target reference voltage, and compares the voltage of the filtered BMC signal with the target reference voltage.

[0048] If the voltage of the BMC signal is higher than the target reference voltage, the hysteresis comparator circuit outputs a high level; if the voltage of the BMC signal is lower than the target reference voltage, the hysteresis comparator circuit outputs a low level. Due to the existence of the hysteresis characteristic, when the BMC signal fluctuates around the target reference voltage, the output level signal of the hysteresis comparator circuit can remain stable to avoid frequent switching.

[0049] S103 , the reference voltage circuit detects whether the level of the level signal changes. If so, the output target reference voltage is switched to the other of the two reference voltages; otherwise, the output target reference voltage is maintained.

[0050] The reference voltage circuit detects whether the current output level of the hysteresis comparator circuit changes, and the change of the output level is the basis for switching the reference voltage.

[0051] When it is determined that the output level of the hysteresis comparator circuit has changed (for example, from a high level to a low level or from a low level to a high level), the current target reference voltage is switched to the other of the two reference voltages. For example, the reference voltage includes a 0.33V voltage and a 0.48V voltage. If the reference voltage in step S102 is 0.33V, the reference voltage can be switched from 0.33V to 0.48V in step S103; similarly, if the reference voltage in step S102 is 0.48V, the reference voltage can be switched from 0.48V to 0.33V in step S103.

[0052] In this embodiment, the first low-pass filter circuit can filter out the noise in the BMC signal and remove the glitches or abnormal fluctuations in the BMC signal during the transmission process, thereby ensuring the integrity of the BMC signal; the reference voltage circuit can realize automatic switching of two reference voltages according to the output level; at the same time, the hysteresis comparator circuit solves the problem of signal reflection, crosstalk or ground plane drift during efficient transmission of electric energy through its unique hysteresis characteristics, thereby ensuring accurate transmission and reception of signals.

[0053] The BMC signal receiving circuit provided by this application is described in detail below. Figure 2 , Figure 2 The schematic diagram of the BMC signal receiving circuit includes: a reference voltage circuit, a first low-pass filter circuit and a hysteresis comparator circuit;

[0054] The first low-pass filter circuit includes a resistor R2 and a capacitor C2;

[0055] The BMC signal is input to one end of the resistor R2, the other end of the resistor R2 is connected in series with one end of the capacitor C2, and the other end of the capacitor C2 is grounded; an output end is provided at the connection between the resistor R2 and the capacitor C2, and the output end is connected to the hysteresis comparator circuit;

[0056] The hysteresis comparator circuit includes a PMOS tube M3, a PMOS tube M4, a PMOS tube M9, a PMOS tube M11, an NMOS tube M5, an NMOS tube M6, an NMOS tube M8, an NMOS tube M10 and an NMOS tube M12;

[0057] The target reference voltage is input to the gate of the PMOS tube M3, and the filtered BMC signal is input to the gate of the PMOS tube M4;

[0058] The source of the PMOS tube M3 is connected to the source of the PMOS tube M4, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the gate of the NMOS tube M5 and the gate of the NMOS tube M6, and the sources of the NMOS tubes M5 and M6 are grounded;

[0059] The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M8, and the source of the NMOS tube M8 is grounded;

[0060] The drain of the NMOS tube M8 is connected to the gate of the PMOS tube M9 and the gate of the NMOS tube M10; the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10, and an output terminal RX_N is provided at the intersection, and the output terminal RX_N is connected to the gates of the PMOS tube M11 and the NMOS tube M12; the drain of the PMOS tube M11 and the drain of the NMOS tube M12 are connected, and an output terminal RX is provided at the intersection; the level signal is fed back to the reference voltage circuit through the output terminal RX_N and the output terminal RX; the sources of the NMOS tubes M10 and M12 are both grounded;

[0061] The reference voltage circuit includes an NMOS tube M13 and an NMOS tube M14; the level signal includes a first level signal and a second level signal;

[0062] A reference voltage is input to the drain of the NMOS tube M13, and another reference voltage is input to the drain of the NMOS tube M14; after the first level signal is input to the PMOS tube M11 and the NMOS tube M12, it is converted into a second level signal;

[0063] The first level signal is input to the gate of the NMOS tube M13 through the output terminal RX_N, and the second level signal is input to the gate of the NMOS tube M14 through the output terminal RX;

[0064] The source of the NMOS transistor M13 and the source of the NMOS transistor M14 output the target reference voltage to the hysteresis comparator circuit.

[0065] Specifically, a second low-pass filter circuit is connected between the reference voltage circuit and the hysteresis comparator circuit; the second low-pass filter circuit includes a resistor R1 and a capacitor C1, the target reference voltage is input to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; an output end is provided at the connection between the resistor R1 and the capacitor C1, and the output end is connected to the hysteresis comparator circuit.

[0066] The first low-pass filter circuit and the second low-pass filter circuit are both low-pass filters composed of simple resistors and capacitors. They are mainly used to filter out interference from the USB high-speed signal routing of the cable to avoid affecting the integrity of the BMC signal. Resistors R1 and R2 play a role in limiting the current. The resistance value of the resistor determines the size of the DC current passing through the filter, and also affects the cutoff frequency of the filter. Capacitors C1 and C2 form obstacles to AC signals in the circuit. The capacitance value of the capacitor determines the attenuation degree of the filter to the high-frequency signal, and also affects the cutoff frequency of the filter.

[0067] When a BMC signal containing multiple frequency components is input to the low-pass filter, capacitors C1 and C2 will hinder the AC signal, while resistors R1 and R2 allow current to pass. For low-frequency signals, the blocking effect of capacitors C1 and C2 is small, so low-frequency signals can pass through the low-pass filter relatively easily. For high-frequency signals, the blocking effect of capacitors C1 and C2 is large, and high-frequency signals will be blocked or attenuated by capacitors C1 and C2, so they cannot pass through the low-pass filter or only pass through with a small amplitude.

[0068] The reference voltage from the system or circuit is connected to one end of the resistor R1, and then connected to the non-inverting input end of the hysteresis comparator circuit after passing through the first low-pass filter circuit; the BMC signal from the power supply end needs to be sent to one end of the resistor R2 through the CC cable, and then connected to the inverting input end of the hysteresis comparator circuit after passing through the second low-pass filter circuit. The first low-pass filter circuit and the second low-pass filter circuit make the reference voltage and BMC signal smoother, reduce noise interference, make the signal change more continuous and stable, and effectively filter out these high-frequency noises, improve the signal-to-noise ratio, and make the signal clearer and more reliable.

[0069] The gate of the PMOS tube M3 is set as the non-inverting input terminal of the hysteresis comparator circuit, and the gate of the PMOS tube M4 is set as the inverting input terminal of the hysteresis comparator circuit.

[0070] When there is no BMC signal transmission or the BMC signal transmission changes from high level to low level, the input voltage of the inverting input terminal is 0, and the reference voltage connected to the non-inverting input terminal is greater than 0V, then the PMOS tube M3 is turned off, the PMOS tube M4 is turned on, and the drain of the PMOS tube M4, the drain of the NMOS tube M6 and the gate of the NMOS tube M8 are connected in series, and the middle node is A; the NMOS tube M6 is turned off, and the high level is input from point A to the gate of the NMOS tube M8; the NMOS tube M8 is turned on, and the drain of the NMOS tube M8, the gates of the PMOS tube M9 and the NMOS tube M10 are connected in series, and the middle node is B; The level at point B is pulled low, causing the PMOS tube M9 to turn on and the NMOS tube M10 to turn off; the drains of the PMOS tube M9 and the NMOS tube M10 are connected to the output terminal RX_N, and output a high level; the output terminal RX_N is simultaneously connected to the gates of the PMOS tube M11 and the NMOS tube M12, then the PMOS tube M11 is turned on and the NMOS tube M12 is turned off, and the drains of the PMOS tube M11 and the NMOS tube M12 are connected to the output terminal RX; since the reference voltage connected to the in-phase input terminal is always greater than 0V, the output terminal RX output always maintains a low level and outputs the processed BMC signal to the terminal.

[0071] If the BMC signal transmission changes from low level to high level, when the BMC signal input to the inverting input terminal is lower than the input reference voltage of the non-inverting input terminal, the output terminal RX_N outputs a high level, and the output terminal RX continues to maintain a low level; when the BMC signal input to the inverting input terminal is higher than the input reference voltage of the non-inverting input terminal, the output terminal RX_N outputs a low level, and the output terminal RX continues to maintain a high level.

[0072] The target reference voltage is switched according to the output terminal RX and the output terminal RX_N. The output terminal RX outputs a level signal to control the on / off of the NMOS tube M14. The output terminal RX_N outputs a level signal to control the on / off of the NMOS tube M13.

[0073] When the level at point A is pulled high, the output terminal RX_N outputs a high level signal, and the output terminal RX outputs a low level signal, then the NMOS tube M13 is turned on, and the NMOS tube M14 is turned off.

[0074] When the level at point A is pulled low, the output terminal RX_N outputs a low level signal, and the output terminal RX outputs a high level signal, then the NMOS tube M13 is turned off, and the NMOS tube M14 is turned on.

[0075] The two reference voltages are automatically switched according to the on and off of the NMOS tube M13 and the NMOS tube M14.

[0076] Please read further Figure 2 , in some embodiments of the present application, further comprising: a bias circuit for providing a driving voltage and a driving current for all circuits; the bias circuit comprises: a bias current source I_bias, a PMOS tube M1, a PMOS tube M2 and a PMOS tube M7;

[0077] One end of the bias current source I_bias is connected to the drain of the PMOS tube M1, the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the gate of the PMOS tube M7; the other end of the bias current source I_bias is connected to the ground;

[0078] The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and the source of the PMOS tube M7;

[0079] The drain of the PMOS tube M2 is connected to the source of the PMOS tube M3 and the source of the PMOS tube M4; the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M8, the gate of the PMOS tube M9 and the gate of the NMOS tube M10.

[0080] The bias current source I_bias is a current source circuit (such as a constant current source, a current mirror, etc.) used to provide a stable current source. This current will be used as a bias current to set the circuit's operating point through the subsequent PNP transistor; the function of the PMOS tube M1 is to convert the input voltage into a voltage bias, which will be used to set the operating point of the subsequent transistors; the PMOS tube M2 further amplifies the voltage bias provided by the PMOS tube M1 and outputs a larger current or voltage through its drain. The function of the PMOS tube M7 may be to further amplify or adjust the bias current or bias voltage to meet the needs of the entire circuit system.

[0081] Working principle of bias circuit: When the bias current source I_bias provides a stable current, this current passes through the drain-gate path of PMOS tube M1, generating a voltage drop. This voltage drop is used as the drain voltage of PMOS tube M1 and is output to the gate of M2 through the gate of M1. After PMOS tube M2 receives this voltage bias, its drain current begins to flow and generates a larger voltage drop or current output. This output is again used as the gate voltage or current source of PMOS tube M7.

[0082] Through this cascade method, the bias circuit can provide a stable and controllable bias current or bias voltage to the subsequent circuit.

[0083] In some embodiments of the present application, the reference voltage includes a 0.33V voltage and a 0.48V voltage.

[0084] The input level range of the BMC signal is between 0.2V and 1.1V. Within this range, the hysteresis comparator circuit usually selects a threshold voltage in the middle for setting. If the threshold is set too high, it may affect the communication quality; conversely, if it is set too low, it will weaken the anti-interference performance of the hysteresis comparator circuit. According to the specific requirements of the USB standard for signal rise time and fall time, it is concluded that these two voltage values ​​meet the expected design standards.

[0085] See also Figure 3 , the present application provides a BMC signal receiving device, the device comprising:

[0086] A reference voltage unit 301, used for switching between two reference voltages and outputting a target reference voltage;

[0087] A first filtering unit 302, configured to filter the BMC signal and input the filtered BMC signal to the comparator unit;

[0088] The comparator unit 303 is used to compare the voltage of the filtered BMC signal with the target reference voltage, and output a level signal according to the comparison result.

[0089] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0090] In the embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0091] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0092] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0093] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk, etc. Various media that can store program codes.

Claims

1. A BMC signal receiving circuit, characterized in that: include: A reference voltage circuit, a first low-pass filter circuit and a hysteresis comparator circuit; Inputting the BMC signal to the first low-pass filter circuit, the first low-pass filter circuit filters the BMC signal, and inputting the filtered BMC signal to the hysteresis comparator circuit; The hysteresis comparator circuit obtains the voltage of the filtered BMC signal and the target reference voltage outputted thereto by the reference voltage circuit, compares the voltage of the filtered BMC signal with the target reference voltage, outputs a level signal according to the comparison result, and feeds the level signal back to the reference voltage circuit, wherein the target reference voltage is one of two switchable reference voltages set by the reference voltage circuit; The reference voltage circuit detects whether the level of the level signal changes. If so, the target reference voltage to be output is switched to the other of the two reference voltages; otherwise, the target reference voltage is kept output.

2. The BMC signal receiving circuit according to claim 1, characterized in that: The first low-pass filter circuit includes a resistor R2 and a capacitor C2; The BMC signal is input to one end of the resistor R2, the other end of the resistor R2 is connected in series with one end of the capacitor C2, and the other end of the capacitor C2 is grounded; an output end is provided at the connection between the resistor R2 and the capacitor C2, and the output end is connected to the hysteresis comparator circuit.

3. The BMC signal receiving circuit according to claim 1, characterized in that: The hysteresis comparator circuit includes a PMOS tube M3, a PMOS tube M4, a PMOS tube M9, a PMOS tube M11, an NMOS tube M5, an NMOS tube M6, an NMOS tube M8, an NMOS tube M10 and an NMOS tube M12; The target reference voltage is input to the gate of the PMOS tube M3, and the filtered BMC signal is input to the gate of the PMOS tube M4; The source of the PMOS tube M3 is connected to the source of the PMOS tube M4, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the gate of the NMOS tube M5 and the gate of the NMOS tube M6, and the sources of the NMOS tubes M5 and M6 are grounded; The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M8, and the source of the NMOS tube M8 is grounded; The drain of the NMOS tube M8 is connected to the gate of the PMOS tube M9 and the gate of the NMOS tube M10; the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10, and an output terminal RX_N is provided at the intersection, and the output terminal RX_N is connected to the gates of the PMOS tube M11 and the NMOS tube M12; the drain of the PMOS tube M11 and the drain of the NMOS tube M12 are connected, and an output terminal RX is provided at the intersection; the level signal is fed back to the reference voltage circuit through the output terminal RX_N and the output terminal RX; the sources of the NMOS tubes M10 and M12 are both grounded.

4. The BMC signal receiving circuit according to claim 3, characterized in that: The reference voltage circuit includes an NMOS tube M13 and an NMOS tube M14; the level signal includes a first level signal and a second level signal; A reference voltage is input to the drain of the NMOS tube M13, and another reference voltage is input to the drain of the NMOS tube M14; the first level signal is input to the PMOS tube M11 and the NMOS tube M12, and then converted into a second level signal; The first level signal is input to the gate of the NMOS tube M13 through the output terminal RX_N, and the second level signal is input to the gate of the NMOS tube M14 through the output terminal RX; The source of the NMOS transistor M13 and the source of the NMOS transistor M14 output the target reference voltage to the hysteresis comparator circuit.

5. The BMC signal receiving circuit according to claim 1, characterized in that: A second low-pass filter circuit is connected between the reference voltage circuit and the hysteresis comparator circuit; The second low-pass filter circuit includes a resistor R1 and a capacitor C1, the target reference voltage is input to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; an output end is provided at the connection between the resistor R1 and the capacitor C1, and the output end is connected to the hysteresis comparator circuit.

6. The BMC signal receiving circuit according to claim 1, characterized in that: The BMC signal receiving circuit also includes a bias circuit for providing a driving voltage and a driving current for all circuits; The bias circuit includes: a bias current source I_bias, a PMOS tube M1, a PMOS tube M2 and a PMOS tube M7; One end of the bias current source I_bias is connected to the drain of the PMOS tube M1, the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the gate of the PMOS tube M7; the other end of the bias current source I_bias is grounded; The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and the source of the PMOS tube M7; The drain of the PMOS tube M2 is connected to the source of the PMOS tube M3 and the source of the PMOS tube M4; the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M8, the gate of the PMOS tube M9 and the gate of the NMOS tube M10.

7. The BMC signal receiving circuit according to claim 1, characterized in that: The reference voltage includes a 0.33V voltage and a 0.48V voltage.

8. A BMC signal receiving device, characterized in that: The device comprises: A reference voltage unit, used for switching between two reference voltages and outputting a target reference voltage; A first filtering unit, used for filtering the BMC signal and inputting the filtered BMC signal to the comparator unit; The comparator unit is used to compare the voltage of the filtered BMC signal with the target reference voltage and output a level signal according to the comparison result.

Images