Digital filter structure for sigma-delta ADC downsampling

Abstract

The invention discloses a digital filter structure for sigma-delta ADC downsampling, which adopts an all-digital method to construct a third-order single-ring feed-forward system, and integrates an integral-comb cascade filter, a compensation filter and a half-band filter in series. Wherein the integral-comb cascade filter is of a recursive structure formed by connecting multiple stages of integrators in series, downsampling multiple programming is supported, and the parallelism degree and the hardware utilization rate are improved by advancing the position of a delay unit. The compensation filter adopts odd-order integrator multi-branch parallel, so that the resource occupation is reduced, and the processing speed is remarkably improved; the half-band filter adjusts the coefficient position by using a retiming technology, reduces the delay of a critical path, improves the highest frequency of the system, reduces the calculation amount through a symmetric structure and a multiplexing extraction path, and reduces the operation rate demand and data loss through preposed extraction. According to the invention, low power consumption, low hardware consumption and high design flexibility of the downsampling filter in the sigma-delta ADC digital module are realized.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and specifically discloses a digital filter structure for Σ-Δ ADC downsampling. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, digital circuits have become a powerful engine for data information processing. As a key pathway for the interaction between analog information and digital circuits, analog-to-digital converters have become an important part. Among the many types of ADCs (Analog to Digital Converters), Σ-ΔADC has become the best choice for achieving high resolution due to its extremely high acquisition rate, shaping technology, and insensitivity to process matching. Σ-Δ ADC has natural advantages in low-frequency and high-resolution fields such as medical electronics and audio. In order to pursue high resolution, analog design engineers have placed a lot of focus on the structural optimization and innovation of the analog modulator, but have paid less attention to the subsequent digital circuits. The digital part of the Σ-Δ ADC largely determines the power consumption and hardware overhead of the chip, so it is very necessary to design a digital module with low power consumption, low area, and high flexibility.

[0003] The development of downsampling filters was not synchronized with the modulator at first. It was not until the Σ-ΔADC technology was proposed that downsampling filters that matched the Σ-ΔADC appeared. Croisier first proposed distributed multiplication-addition coding in 1973. This method complemented the FPGA proposed at the same time and became a popular method for filter design. Later, Hogenauer proposed a structure that used an integrator-comb cascade filter CIC (Cascaded Integrator Comb) for high-speed downsampling, which has had an impact to this day. BrandtBP achieved structural and area optimization through hardware reuse in FPGA on a distributed basis.

[0004] In the above methods, the implementation of the downsampling filter is not suitable for low-power, low-area and high-flexibility Σ-Δ ADCs. In terms of specific implementation solutions, there are two directions to choose from: one is to use a single FIR filter, and the other is to connect multiple filters in series. Using FilterDesigner to design a minimum-order low-pass FIR filter with a high density factor, flat passband and high stopband attenuation using the equal ripple method requires tens of thousands of orders, which requires a large number of additional multiplication and addition operations, which is a huge expense in terms of performance and area power consumption. Therefore, the form of multi-stage FIR filters in series is more suitable for the downsampling filter module in high-performance Σ-Δ ADCs.

[0005] In the signal rate conversion system, the integrator-comb cascade filter is the most widely used. It has low-pass and high-impedance properties, and its coefficients are all integers. When implemented in hardware, it is not necessary to perform various quantization processing on the coefficients, nor to occupy various ROMs. In addition, the particularity of the coefficients saves a lot of shift and multiplication operations for the calculation, and the final cost is completely determined by the number of additions. In addition, the structural rules of the integrator-comb cascade filter can change the extraction factor according to different system needs, and it has natural programmability. However, when the integrator-comb cascade filter is used as a low-pass, the passband is not flat, and the high-impedance characteristics are also affected by the number of cascades. A compensation filter must be added to process it, and the filter can also perform a decimation operation at the same time. Finally, in order to obtain a flatter passband and stopband, it is necessary to add another filter for control. The half-band filter has a special spectrum, which causes its coefficients to be naturally half less than the general structure. The overhead required under the same specifications is smaller, and its passband and stopband are flat, and the transition band is easy to control. Therefore, the half-band filter is used as the last stage and is downsampled twice, which also reduces the pressure of the compensation filter on the stopband attenuation. Therefore, the multi-stage series connection of the integrator-comb cascade filter, the compensation filter and the half-band filter will have excellent comprehensive performance, and will be more conducive to being used as a low-power, low-area and high-flexibility digital module for Σ-Δ ADC. Summary of the invention

[0006] The purpose of the present invention is to provide a digital filter structure for Σ-Δ ADC downsampling to solve the disadvantages of the above-mentioned existing downsampling filter structure, such as high power consumption, large area, complex structure, low flexibility, and the need for additional compensation circuits. To achieve the above purpose, the present invention adopts the following technical solutions:

[0007] The digital filter structure for Σ-Δ ADC downsampling comprises:

[0008] Integral-comb cascade filter, compensation filter, half-band filter; among them,

[0009] The input end of the integrator-comb cascade filter is connected to the signal input end, and the signal input end is used to input the output signal of the Σ-Δ ADC modulator;

[0010] The output end of the integrator-comb cascade filter is connected to the input end of the compensation filter;

[0011] The output end of the compensation filter is connected to the input end of the half-band filter.

[0012] The output end of the half-band filter outputs a filtered signal.

[0013] The integrator-comb cascade filter comprises:

[0014] A first integrator, a second integrator, a third integrator, ..., an N-1th integrator, an N-th integrator, a first filter, a second filter, a third filter, ..., an N-1th filter, an N-th filter, a first fixed-point conversion module, a second fixed-point conversion module, a third fixed-point conversion module, and a programmable downsampling module; wherein,

[0015] The first integrator is connected to the second integrator and the first fixed-point conversion module; the second integrator is connected to the third integrator; and so on, the N-1th integrator is connected to the Nth integrator; the Nth integrator is connected to the programmable downsampling module; the programmable downsampling module is connected to the second fixed-point conversion module; the second fixed-point conversion module is connected to the first filter; the second filter is connected to the third filter; and so on, the N-1th filter is connected to the Nth filter; and the Nth filter is connected to the compensation filter.

[0016] The compensation filter comprises:

[0017] The first branch first filter, the first branch second filter, the first branch third filter, ..., the first branch N-1 filter, the first branch N filter, the second branch first filter, the second branch second filter, the second branch third filter, ..., the second branch N-1 filter, the second branch N filter, the first downsampling module, the second downsampling module, the delay unit z-1; wherein,

[0018] The delay unit z-1 is connected to the integral-comb cascade filter, the first downsampling module, and the second downsampling module; the first downsampling module is connected to the first filter of the first branch; the first filter of the first branch is connected to the second filter of the first branch and the Nth filter of the second branch; the second filter of the first branch is connected to the third filter of the first branch; and so on, the N-1th filter of the first branch is connected to the Nth filter of the first branch; the Nth filter of the first branch is connected to the half-band filter; the second downsampling module is connected to the first filter of the second branch; the first filter of the second branch is connected to the second filter of the second branch; the second filter of the second branch is connected to the third filter of the second branch; and so on, the N-1th filter of the second branch is connected to the Nth filter of the second branch; the N-1th filter of the second branch is connected to the Nth filter of the second branch.

[0019] The half-band filter comprises:

[0020] A first multiplier, a second multiplier, a third multiplier, ..., an N-1th multiplier, an N-th multiplier, a first filter, a second filter, a third filter, ..., a 2N-1th filter, a first downsampling module, a second downsampling module, and a delay unit z-1; wherein,

[0021] The first downsampling module is connected to the delay unit z-1, the compensation filter, the first multiplier, the second multiplier, the third multiplier, ..., the N-1th multiplier; the delay unit z-1 is connected to the second downsampling module; the first multiplier is connected to the first filter and the 2N-1th filter; the second multiplier is connected to the first filter and the 2N-2th filter; and so on, the N-1th multiplier is connected to the N-2th filter and the N-1th filter; the second downsampling module is connected to the Nth multiplier; the Nth multiplier is connected to the Nth filter.

[0022] The Nth integrator comprises:

[0023] Adder, delay unit z-1; where,

[0024] The adder is connected to the delay unit z-1 and the programmable downsampling module; the delay unit z-1 is connected to the programmable downsampling module.

[0025] The Nth filter comprises:

[0026] Adder, delay unit z-1; where,

[0027] The adder is connected to the N-1th filter, the delay unit z-1, and the third fixed-point conversion module; the delay unit z-1 is connected to the N-1th filter.

[0028] The first branch Nth filter comprises:

[0029] A first delay unit z-1, a second delay unit z-1, a first adder, a second adder, and a multiplier; wherein,

[0030] The first delay unit z-1 is connected to the first adder, the N-1th filter of the first branch, and the second delay unit z-1; the second delay unit z-1 is connected to the first adder and the N-1th filter of the first branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; the second adder is connected to the N-1th filter of the first branch and the half-band filter.

[0031] The second branch Nth filter comprises:

[0032] A first delay unit z-1, a second delay unit z-1, a first adder, a second adder, and a multiplier; wherein,

[0033] The first delay unit z-1 is connected to the first adder, the N-1th filter of the second branch, and the second delay unit z-1; the second delay unit z-1 is connected to the first adder and the N-1th filter of the second branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; the second adder is connected to the N-1th filter of the second branch and the first filter of the first branch.

[0034] The 2N-1th filter comprises:

[0035] Delay unit z-1, adder; wherein,

[0036] The delay unit z-1 is connected to the 2N-2th filter and the adder; the adder is connected to the first multiplier and the first filter.

[0037] The digital filter structure for Σ-Δ ADC downsampling can select two modes, full parallel and serial, through the register module configuration parameters of the Σ-Δ ADC system.

[0038] Compared with the prior art, the present invention has the following technical effects:

[0039] 1. The digital filter structure for Σ-Δ ADC downsampling of the present invention has the advantages of low power consumption, low area and high flexibility, and is suitable for the design of Σ-Δ ADC customized for specific indicators.

[0040] 2. In the digital filter structure for Σ-Δ ADC downsampling of the present invention, a recursive integrator-comb cascade filter is used to move the downsampling module forward, thereby reducing hardware resource consumption.

[0041] 3. In the digital filter structure for Σ-Δ ADC downsampling of the present invention, the compensation filter reduces the number of multiplication operations by using the linear symmetry of coefficients, reduces circuit resources and improves the speed. At the same time, the demand for operation rate is reduced, and the parallelism of the system is greatly improved by duplicating multiple paths.

[0042] 4. In the digital filter structure for Σ-Δ ADC downsampling of the present invention, the half-band filter uses the retiming technology to modify the coefficient position, so that the critical path delay is reduced and the maximum frequency of the system is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1A schematic diagram of a series third-order feedforward structure of a digital filter structure for Σ-Δ ADC downsampling provided by an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of an integrator-comb cascade filter architecture design for a digital filter structure for Σ-Δ ADC downsampling provided in an embodiment of the present invention.

[0045] Figure 3 A schematic diagram of a compensation filter architecture design of a digital filter structure for Σ-Δ ADC downsampling provided by an embodiment of the present invention.

[0046] Figure 4 A schematic diagram of a half-band filter architecture design of a digital filter structure for Σ-Δ ADC downsampling provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] The present invention is further described in detail below with reference to specific embodiments.

[0050] See also Figure 1 , Figure 1 A schematic diagram of a three-stage filter series connection of a digital filter structure for Σ-Δ ADC downsampling provided by an embodiment of the present invention.

[0051] In one aspect of the present invention, the downsampling digital filter is composed of an integral-comb cascade filter, a compensation filter and a half-band filter in a multi-stage series connection form to form a third-order single-loop feedforward structure;

[0052] Among them, since the passband of the integral-comb cascade filter is not flat when used in low-pass mode, its high-impedance characteristics are also easily affected by the number of cascades. A compensation filter is added to compensate for its spectral characteristics, and the compensation filter can also perform a decimation operation at the same time. After compensation, it outputs data with flat low-frequency passband and good high-impedance characteristics. The final down-sampled data with a flatter passband and a steeper stopband is output through the last stage of the half-band filter. The half-band filter can perform two times downsampling at the same time, which reduces the pressure of the compensation filter on the stopband attenuation and reduces the area and hardware resource overhead.

[0053] It should be noted that the integrator-comb cascade filter has three programmable downsampling multiples, and the compensation filter and half-band filter are fixed downsampling multiples. The required frequency division clock can be generated by modifying the parameters of the register address of the specified Σ-ΔADC system, thereby programming the downsampling factor of the Σ-ΔADC modulator suitable for the application of digital filters.

[0054] It should be noted that the downsampling filter can select two modes, full parallel mode and serial mode, through the register module configuration parameters of the Σ-Δ ADC system.

[0055] The serial mode structure continuously reuses an adder to complete the operation in the manner of data window movement. For the full parallel mode, the compensation filter is implemented in a highly pipelined, structured, and regular pulsating manner; the half-band filter is implemented in a transposed manner.

[0056] It should be noted that the driving clock required inside the down-sampling digital filter is generated by the frequency division circuit of the Σ-Δ ADC system.

[0057] In addition, since the input excitation signal of the digital downsampling filter comes from the output floating-point data of the Σ-Δ modulator, the floating-point numbers and intermediate data need to be processed into fixed-point form, which requires a fixed-point unit.

[0058] It should be noted that in order to simplify the drawings, Figure 1 Only the three fixed-point conversion modules, namely the convert modules, in the integral-comb cascade filter are drawn, but the compensation filter and the half-band filter also require fixed-point units, which are located at the input ends of the three-stage filters, the output ends of the internal downsampling modules, and the final output ends.

[0059] In addition, it should be noted that the orders of the integral-comb cascade filter, the compensation filter and the half-band filter are calculated based on specific indicator requirements and models.

[0060] For further information, see Figure 2 , Figure 2 A schematic diagram of the design of an integrator-comb cascade filter architecture for a digital filter structure for Σ-Δ ADC downsampling.

[0061] In another aspect of the present invention, the integrator-comb filter is obtained by connecting an integrator and a comb filter in series, and the cascaded system of multiple integrator-comb filters has better low-pass properties. The downsampling module is moved forward in the recursive structure. The register parameters of the Σ-Δ ADC system generate the downsampling factor selected by the frequency division clock configuration.

[0062] It should be noted that the amplitude of the series integrator-comb filter is calculated using the following formula:

[0063]

[0064] Among them, R is the speed reduction factor, M is a fixed value, and N is the number of series stages.

[0065] In addition, it should be noted that the -3dB bandwidth must be taken into special consideration during calculations. It must be ensured that the drop in the integral-comb filter within the effective range is greater than the rise in the NTF.

[0066] It should be noted that since the excitation of the digital downsampling filter comes from the output of the Σ-Δ modulator, it is also necessary to perform fixed-point processing on the floating-point number. The fixed-point unit is Figure 1 The convert module in .

[0067] Specifically, in this embodiment, the integrator-comb filter adopts a four-stage structure. In the design of the integrator, the delay unit is adjusted to the data path, which improves the system parallelism and reduces the hardware consumption without changing the function. It also includes a fixed-point conversion module for converting floating point to fixed point and processing intermediate data. The data path is interrupted in the form of a pipeline to increase the maximum clock frequency.

[0068] In addition, it should be noted that due to the bit growth of the integral-comb filter, the fixed-point design is very important. It is necessary to combine the specific hardware to reasonably design the fixed-point design, to prevent data overflow from causing functional errors, and to save hardware resources as much as possible. The maximum bit width of the integral-comb filter is calculated using the following formula:

[0069]

[0070] Where Bin is the bit width of the input signed data.

[0071] For further information, see Figure 3 , Figure 3A schematic diagram of the compensation filter architecture design for a digital filter structure used for Σ-Δ ADC downsampling.

[0072] The compensation filter adopts a non-configurable mode and only compensates for the maximum bandwidth of the integrator-comb filter, that is, the passband attenuation under the minimum downsampling multiple, thereby reducing the required area and hardware overhead.

[0073] It should be noted that, since FIR is inherently linear in phase compared to IIR, the structure is optimized. In the embodiment, the compensation filter is an odd length, which meets the even symmetry condition, that is, the unit impulse response satisfies the periodic symmetry, and the symmetric structure saves nearly half of the computational overhead, and reduces the computational rate requirement and data waste by pre-positioning and decomposing the extraction path.

[0074] Specifically, in this embodiment, the number of filter data paths is related to the downsampling multiple, and the parallelism of the system is greatly improved by duplicating multiple paths. Moreover, each path of the compensation filter does not work at the same time, eliminating the waste of intermediate quantities in each calculation. Moreover, in the design of the integrator, the delay unit is adjusted to the data path, which improves the system parallelism while reducing hardware consumption without changing the function.

[0075] In addition, it should be noted that the input of the compensation filter is the output of the previous stage integrator-comb filter, so a fixed-point unit is also required. The higher the required accuracy of the design, the larger the required order. The most required fixed-point digital width of the compensation filter is calculated using the following formula:

[0076]

[0077] Where Ap is the stopband attenuation and L is the filter order.

[0078] It should be noted that in order to simplify the drawings, Figure 3 The fixed-point conversion module, namely the convert module, is not drawn in the figure. The fixed-point conversion module of the compensation filter is located at the input end of the compensation filter, the output ends of each internal downsampling module and the final output end.

[0079] For further information, see Figure 4 , Figure 4 A schematic diagram of a half-band filter architecture design for a digital filter structure for Σ-Δ ADC downsampling.

[0080] Specifically, the half-band filter uses the spectrum mirror relationship. If its order is an odd number, half of its coefficients are 0. The actual number of multiplications required, that is, the required input fan-out capacity, is much smaller than that of the compensation filter. By duplicating multiple paths to achieve a parallel structure and using retiming technology to modify the coefficient position, the critical path delay is reduced and the maximum frequency of the system is increased.

[0081] It should be noted that the input of the half-band filter is the output of the previous compensation filter. To simplify the drawings, Figure 4 The fixed-point conversion module, i.e., the convert module, is not drawn in the figure, but the half-band filter also requires a fixed-point unit to process the floating-point data generated in the middle. The fixed-point conversion module is located at the input end of the half-band filter, the output end of each internal downsampling module, and the final output end.

[0082] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A digital filter structure for Σ-Δ ADC downsampling, characterized in that: include: Integral-comb cascade filter, compensation filter, half-band filter; among them, The input end of the integrator-comb cascade filter is connected to the signal input end, and the signal input end is used to input the output signal of the Σ-Δ ADC modulator; The output end of the integrator-comb cascade filter is connected to the input end of the compensation filter; The output end of the compensation filter is connected to the input end of the half-band filter; The output end of the half-band filter outputs a filtered signal.

2. The digital filter structure for Σ-Δ ADC downsampling according to claim 1, characterized in that: The integrator-comb cascade filter comprises: A first integrator, a second integrator, a third integrator, ..., an N-1th integrator, an N-th integrator, a first filter, a second filter, a third filter, ..., an N-1th filter, an N-th filter, a first fixed-point conversion module, a second fixed-point conversion module, a third fixed-point conversion module, and a programmable downsampling module; wherein, The first integrator is connected to the second integrator and the first fixed-point conversion module; the second integrator is connected to the third integrator; and so on, the N-1th integrator is connected to the Nth integrator; the Nth integrator is connected to the programmable downsampling module; the programmable downsampling module is connected to the second fixed-point conversion module; the second fixed-point conversion module is connected to the first filter; the second filter is connected to the third filter; and so on, the N-1th filter is connected to the Nth filter; and the Nth filter is connected to the compensation filter.

3. The digital filter structure for Σ-Δ ADC downsampling according to claim 1, characterized in that: The compensation filter comprises: The first branch first filter, the first branch second filter, the first branch third filter, ..., the first branch N-1 filter, the first branch N filter, the second branch first filter, the second branch second filter, the second branch third filter, ..., the second branch N-1 filter, the second branch N filter, the first downsampling module, the second downsampling module, the delay unit z -1 ;in, The delay unit z -1 It is connected to the integral-comb cascade filter, the first downsampling module, and the second downsampling module; the first downsampling module is connected to the first filter of the first branch; the first filter of the first branch is connected to the second filter of the first branch and the Nth filter of the second branch; the second filter of the first branch is connected to the third filter of the first branch; and so on, the N-1th filter of the first branch is connected to the Nth filter of the first branch; the Nth filter of the first branch is connected to the half-band filter; the second downsampling module is connected to the first filter of the second branch; the first filter of the second branch is connected to the second filter of the second branch; the second filter of the second branch is connected to the third filter of the second branch; and so on, the N-1th filter of the second branch is connected to the Nth filter of the second branch; the N-1th filter of the second branch is connected to the Nth filter of the second branch.

4. The digital filter structure for Σ-Δ ADC downsampling according to claim 1, characterized in that: The half-band filter comprises: The first multiplier, the second multiplier, the third multiplier, ..., the N-1th multiplier, the Nth multiplier, the first filter, the second filter, the third filter, ..., the 2N-1th filter, the first downsampling module, the second downsampling module, the delay unit z -1 ;in, The first down-sampling module and the delay unit z -1 , a compensation filter, a first multiplier, a second multiplier, a third multiplier, ..., an N-1th multiplier are connected; the delay unit z -1 The first multiplier is connected to the first filter and the 2N-1th filter; the second multiplier is connected to the first filter and the 2N-2th filter; and so on, the N-1th multiplier is connected to the N-2th filter and the N-1th filter; the second downsampling module is connected to the Nth multiplier; the Nth multiplier is connected to the Nth filter.

5. The digital filter structure for Σ-Δ ADC downsampling according to claim 2, characterized in that: The Nth integrator comprises: Adder, delay unit -1 ;in, The adder and delay unit z -1 , programmable downsampling module connected; the delay unit z -1 Connects to the programmable downsampling module.

6. The digital filter structure for Σ-Δ ADC downsampling according to claim 2, characterized in that: The Nth filter comprises: Adder, delay unit -1 ;in, The adder and the N-1th filter and the delay unit z -1 , and the third fixed-point conversion module is connected; the delay unit z -1 Connected to the N-1th filter.

7. The digital filter structure for Σ-Δ ADC downsampling according to claim 3, characterized in that: The first branch Nth filter comprises: The first delay unit z -1 , the second delay unit z -1 , a first adder, a second adder, a multiplier; wherein, The first delay unit z -1 and the first adder, the first branch N-1 filter, the second delay unit z -1 The second delay unit z -1 It is connected to the first adder and the N-1th filter of the first branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; the second adder is connected to the N-1th filter of the first branch and the half-band filter.

8. The digital filter structure for Σ-Δ ADC downsampling according to claim 3, characterized in that: The second branch Nth filter comprises: The first delay unit z -1 , the second delay unit z -1 , a first adder, a second adder, a multiplier; wherein, The first delay unit z -1 With the first adder, the second branch N-1 filter, the second delay unit z -1 The second delay unit z -1 It is connected to the first adder and the N-1th filter of the second branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; the second adder is connected to the N-1th filter of the second branch and the first filter of the first branch.

9. The digital filter structure for Σ-Δ ADC downsampling according to claim 4, characterized in that: The 2N-1th filter comprises: Delay unit z -1 , adder; among them, The delay unit z -1 It is connected to the 2N-2th filter and the adder; the adder first multiplier and the first filter are connected.

10. The digital filter structure for Σ-Δ ADC downsampling according to claim 1, characterized in that: The digital filter structure used for Σ-Δ ADC downsampling can select both full parallel and serial modes through the register module configuration parameters of the Σ-Δ ADC system.

Images