Sigma-delta adc down-sampling digital filter floating point coefficient quantization unit design method

Abstract

The application discloses a kind of Σ-ΔADC downsampling digital filter floating point coefficient fixed-point unit design method, with all-digital implementation, fusion is based on the optimal coding of graph theory, hybrid coding combination and multiplication-addition operation optimization technique.By the hybrid coding method based on graph theory, multiplication-addition law operation hardware resource is reduced, operation speed is improved, and while guaranteeing the slight drop of delay, the area and power consumption are significantly optimized.In addition, the optimization carry chain rearrangement algorithm is used to maximize the fanout number of adder and the efficiency of connection.Compared with the traditional floating point coefficient fixed-point encoding and adder method, the present application can effectively realize the multiplication-addition operation optimization of downsampling filter in Σ-ΔADC digital module, significantly reduce the power delay product on the basis of keeping similar area, significantly enhance the comprehensive performance of downsampling digital filter floating point coefficient fixed-point unit, and be suitable for multiplication-addition operation optimization of downsampling filter in Σ-ΔADC digital module.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuit design, and particularly discloses a design method of a Σ-Δ ADC down-sampling digital filter floating point coefficient fixed point unit. BACKGROUND

[0002] Since the floating point numbers of the digital filter model need to be fixed-point processed in hardware implementation, the Σ-Δ ADC down-sampling digital filter often contains an integral-comb cascaded filter, a compensation filter and a half-band filter and the like. Except for the integral-comb cascaded filter, the coefficients of the rest of the filters, such as the compensation filter and the half-band filter, are non-integers. Under the condition of fixed-point width determination, the hardware implementation overheads of different encoding algorithms are also different. The more the non-zero numbers in the coefficients, the more the addition operations in hardware implementation. In order to reduce the hardware overhead, the traditional encoding algorithm must be optimized and designed.

[0003] In the digital system encoding, the most common methods include binary complement, inverse code, signed number value representation and the like, among which the binary encoding is the most widely used. According to statistics, when the binary encoding is used, nearly half of the positions are zeros. In order to reduce the non-zero numbers, the signed number encoding system adds -1 on the basis of 0 and 1. For the signed number encoding, the proportion of non-zero numbers is reduced to one third. However, the signed number encoding is not unique, and thus there is the best regular signed CSD encoding based on the signed number algorithm improvement.

[0004] Although the best regular signed CSD encoding can greatly reduce the non-zero numbers in the coefficients, thereby reducing the addition operations in the whole operation. However, in the optimal encoding, the coefficients are often factorized, and then the factors are implemented. The best regular signed CSD after the factorization of the coefficients can more effectively reduce the number of required adders. And for a set composed of multiple constant coefficients, there are many methods to represent it by a graph. Through the way of factorization, a series of intermediate variables can be generated. If the reuse of the existing intermediate variables can be used to generate other variables that have not been generated, then the system not only has a reduced overhead, but also has a speed improvement.

[0005] Σ-ΔADC down-sampling digital filter contains a variety of FIR filters, from the difference equation of FIR, it can be seen that it is essentially composed of a series of multiply-add operations. Therefore, the optimization of multiply-add operation is very useful for optimizing the coefficient solving process of Σ-ΔADC down-sampling digital filter. For multiply-add operation, the simplest way is to use the hardwired multiply-adder resource. Because these fixed resources are integrated with other basic logic, the tool will cause low resource utilization when automatically implemented, so the multiply-add operation must be designed and optimized according to the system requirements. The most commonly used optimization algorithm is to use the distributed idea, that is, to decompose the binary data bit by bit. The data at different times of the same bit is reorganized, and the result is stored in advance, and finally the final result is obtained by address reading and shifting addition.

[0006] After distributed reorganization, all possible results can be obtained by pre-operation, and the number of additions is only related to the input bit width. However, this method has several shortcomings. First, this method requires more ROM resources, and the resource consumption increases exponentially with the coefficient bit width. If you want to achieve full parallel mode, such hardware overhead is unacceptable. Second, this method has an advantage on FPGA because it has rich embedded RAM, LUT and other resources inside. If you want to implement it as ASIC, the advantage will no longer exist. Multiplication operation can be replaced by shifting addition, so no special multiplier is needed.

[0007] There are mainly two directions for the optimization of addition, one is for serial mode, focusing on low power consumption and low hardware overhead. The other is for parallel mode, focusing on high speed and low delay, and the requirements of hardware overhead and power consumption are relatively low. The common types are chain carry adder (Carry-Ripple Adder), carry-skip adder (Carry-Skip Adder), carry-select adder (Carry-Select Adder) and lookahead carry adder (Carry-Lookahead Adder). Among them, the carry-ripple structure is the simplest, but because it needs to pass the previous bit carry calculation to the next level for use, the critical path is the longest, and it is suitable for serial mode with low speed requirement. In full parallel mode, the speed requirement is high, and the carry propagation chain must be modified to shorten the time as much as possible. Whether it is carry selection or skip, although it improves the operation parallelism to some extent and reduces the critical path, it does not fundamentally eliminate the limitation of the propagation chain by the step-by-step carry.

[0008] Through the test comparison of the number of gates, delay, area and power consumption of different implementation methods of the same bit adder, it can be seen that the lookahead carry adder can exchange more hardware overhead and power consumption for lower delay. SUMMARY

[0009] The present application aims to provide a coefficient solving method for a Σ-Δ ADC decimation digital filter, to solve the above-mentioned shortcomings of large power consumption, large area and large delay in the coefficient solving process of the decimation digital filter, and the defects of limited working mode and small application range. In order to achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0010] The design method of the floating-point coefficient quantization unit of the Σ-Δ ADC decimation digital filter comprises:

[0011] An optimal quantization encoding method and a multiplication-addition operation optimization method; wherein,

[0012] The floating-point coefficients required by the Σ-Δ ADC decimation digital filter are input into the optimal quantization encoding method, and the optimal encoded quantized parameters are output to obtain an optimal floating-point coefficient quantization unit structure, and the multiplication-addition operation optimization method is used to optimize the operation unit structure in the floating-point coefficient quantization unit of the Σ-Δ ADC decimation digital filter.

[0013] The optimal quantization encoding method comprises:

[0014] An optimal encoding method based on graph theory and a hybrid encoding combination method; wherein,

[0015] The optimal encoding method based on graph theory is connected with the hybrid encoding combination method; the floating-point coefficients required by the Σ-Δ ADC decimation digital filter are input into the optimal encoding method based on graph theory, and the obtained optimized encoding is output; the optimized encoding output by the optimal encoding method based on graph theory is input into the hybrid encoding combination method, and finally the optimal encoded quantized parameters are output.

[0016] The multiplication-addition operation optimization method comprises the following steps:

[0017] Firstly, replace the multiplication operation with a shift-addition operation;

[0018] Secondly, initialize group generation signals and group propagation signals according to a generating function and a transfer function;

[0019] Thirdly, calculate the individual group generation signals and group propagation signals;

[0020] Fourthly, use partial group pre-computing in the Brent-Kung structure to generate odd carry;

[0021] Fifthly, gradually reduce the number of additional PG units required in the Kogge-Stone structure in the later stage;

[0022] Sixth step, the last stage uses odd carry to calculate even carry.

[0023] Seventh step, the calculation of the base sum and carry output is completed.

[0024] The optimal coding method based on graph theory comprises the following steps:

[0025] First step, initialize input set A and graph set B;

[0026] Second step, all elements in set A are positive and odd;

[0027] Third step, calculate the addition cost required by the coefficients in set A;

[0028] Fourth step, move the coefficients with a cost of 1 in set A into set B;

[0029] Fifth step, calculate the coefficients in set B that can generate a cost of 0;

[0030] Sixth step, store the generated coefficients in set C and randomly add or subtract;

[0031] Seventh step, move the coefficients with the value in set A into set B;

[0032] Eighth step, determine whether there are coefficients to be moved into set B: if yes, return to execute the fifth step: calculate the coefficients in set B that can generate a cost of 0; if no, execute the subsequent process, i.e., ninth step: determine whether set A is empty;

[0033] Ninth step, determine whether set A is empty: if yes, end the entire coding generation process and exit the loop; if no, execute the tenth step: add a new auxiliary coefficient to set B;

[0034] Tenth step, add a new auxiliary coefficient to set B.

[0035] The hybrid coding combination method comprises the following steps:

[0036] First step, compare the coding optimization effects of the two coding methods on the filter coefficients;

[0037] Second step, determine whether the graph theory coding performance is better than the optimal CSD coding: if yes, execute the third step: adopt the optimal coding based on graph theory; if no, execute the fourth step: adopt the optimal regular signed CSD coding;

[0038] Third step, adopt the optimal coding based on graph theory;

[0039] Fourth step, adopt the optimal regular signed CSD coding;

[0040] Fifth step, hybrid coding is completed, and the coding result is obtained.

[0041] The multiplication-addition operation optimization method optimizes the maximum fan-out number and the number of connections by rearranging the carry chain, configures the logic stage number as log2N+2, the maximum fan-out as 2, and the number of connections as 1.

[0042] Wherein, N is the addition bit number.

[0043] The multiplication-addition operation is replaced by shift-addition, and the multiplication-addition operation is realized by full-addition operation.

[0044] The new auxiliary coefficient is added in the set B, if the intermediate coefficients are all related to each other, the optimal encoding result can be directly obtained, otherwise the new auxiliary coefficient needs to be added to establish the relationship.

[0045] The judgment graph theory encoding performance is better than the best CSD encoding, the optimal encoding result of the graph theory-based encoding optimization is compared with the result of the best regular signed CSD encoding, and the optimal encoding result of the two is adopted.

[0046] The new auxiliary coefficient is added, only one variable is added, and the rest is not processed.

[0047] Compared with the prior art, the present application has the following technical effects:

[0048] 1. The number of adders required by the floating-point coefficient quantization unit of the down-sampling digital filter is significantly reduced, and the number of critical paths is also reduced. The hardware resource overhead is reduced and the operation speed of the floating-point coefficient quantization unit is improved.

[0049] 2. The optimal quantization encoding method has a slight delay in implementation, and the area and power consumption required by the floating-point coefficient quantization unit are significantly improved.

[0050] 3. The multiplication-addition operation optimization algorithm using the optimized carry chain rearrangement method realizes the maximum fan-out number and the number of connections of the adder in the floating-point coefficient quantization unit, and has a great improvement compared with the three typical addition acceleration structures at the same power consumption.

[0051] 4. Compared with the traditional floating-point coefficient quantization encoding and adder method, the optimized digital filter floating-point coefficient quantization unit design method significantly reduces the power-delay product of the integrated circuit while the area used is almost unchanged, and improves the comprehensive performance of the down-sampling digital filter floating-point coefficient quantization unit. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 The optimal encoding method flow chart of the Σ-Δ ADC down-sampling digital filter floating-point coefficient quantization unit design method based on graph theory provided by the embodiment of the present application;

[0053] Figure 2 A mixed encoding combination method flow chart of a Σ-Δ ADC down-sampling digital filter floating point coefficient fixed point unit design method provided by the embodiment of the present application;

[0054] Figure 3 A multiplication-addition operation optimization method flow chart of a Σ-Δ ADC down-sampling digital filter floating point coefficient fixed point unit design method provided by the embodiment of the present application;

[0055] Figure 4 A whole optimization design method flow chart of a Σ-Δ ADC down-sampling digital filter floating point coefficient fixed point unit design method provided by the embodiment of the present application; DETAILED DESCRIPTION

[0056] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely in the following by combining the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, not all. Based on the embodiment in the present application, all other embodiments obtained by the ordinary skilled in the art without creative labor should belong to the scope of the present application.

[0057] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0058] The present application will be further described in detail below in combination with specific embodiments.

[0059] Please refer to Figure 1 The optimal encoding method based on graph theory is generated as follows:

[0060] First, initialize the input set A and the graph set B;

[0061] Second, all elements of set A are positive odd numbers: that is, the input coefficient set A is positive odd, that is, each coefficient in the input coefficient set A is divided by the maximum divisor of the power of 2 to obtain the positive odd coefficient and the rewritten set A;

[0062] Third step, calculate the required addition cost of the coefficients in set A: that is, delete the power of 2 in the positive odd input coefficient set A and repeat the number, and then calculate the required addition cost of each coefficient, that is, the number of additions required;

[0063] Fourth step, move the coefficients with a cost of 1 in set A to set B: that is, move the coefficients corresponding to the addition cost of 1 obtained in the third step to the graph set B, and delete the coefficients in set A;

[0064] Fifth step, calculate the coefficients in set B that can generate a cost of 0: that is, calculate the multiple of the power of 2 of the coefficients in the graph set B;

[0065] Sixth step, store the generated coefficients in set C and randomly add or subtract: that is, store the coefficients calculated in the fifth step in set C, and perform an addition or subtraction operation on two random coefficients in set C;

[0066] Seventh step, move the coefficients with the value in set A to set B: that is, compare and find out whether set A contains the same coefficients as the coefficients generated by the operation in the sixth step, if so, move the same coefficients in set A to the graph set B and delete them in set A;

[0067] Eighth step, judge whether the coefficients are moved to set B: if yes, return to execute the fifth step: calculate the coefficients in set B that can generate a cost of 0; if not, execute the subsequent process, that is, the ninth step: judge whether set A is empty;

[0068] Ninth step, judge whether set A is empty: that is, judge whether set A is empty after the eighth step is executed, if yes, end the entire coding generation process and exit the loop; if not, execute the tenth step: add new auxiliary coefficients to set B;

[0069] Tenth step, add new auxiliary coefficients to set B: that is, repeat the fifth step to the ninth step, if the tenth step is entered, delete the original added auxiliary coefficients, and then add new auxiliary coefficients to set B, until the loop is exited after the ninth step is judged.

[0070] It should be noted that the coding optimization method based on graph theory representation, that is, using the correlation between the coefficients to complete the coding optimization of the floating point coefficient fixed point unit in the down-sampling digital filter, which needs to be considered in two cases: if the intermediate coefficients are related to each other, then the optimal coding result can be directly obtained; if additional variables need to be added to establish the relationship between the coefficients, this part has randomness.

[0071] In addition, it should be noted that if variables are added blindly to pursue correlation, it may lead to negative optimization. Therefore, the present application only considers the case of adding one additional variable, and the rest is not processed.

[0072] Specifically, the optimal encoding algorithm can be divided into two steps:

[0073] In the first step, all coefficients satisfying the associated attributes are optimized until all relationships are covered.

[0074] In the second step, if there are still uncovered cases after the first step, the second step is needed to optimize the additional variable alone. If there are still remaining after the second step, the probability of negative optimization increases, and this part is discarded.

[0075] In addition, it should be noted that, due to the correlation between the encoding optimization result based on graph theory and the floating-point coefficients required for encoding, the optimization effect has randomness, and there may be cases of negative optimization due to factor decomposition. Therefore, the encoding optimization result based on graph theory is compared with the result of the best regular signed CSD encoding, and the optimal encoding result is taken.

[0076] Further, please refer to Figure 2 The hybrid encoding combination method is as follows:

[0077] In the first step, the encoding optimization effect of the two encoding methods on the filter coefficients is compared: that is, the result of the graph theory-based coefficient encoding is compared with the best regular signed CSD encoding result;

[0078] In the second step, it is determined whether the graph theory encoding performance is better than the best CSD encoding: that is, a comparison is made and a judgment is made, if yes, the third step is executed: the optimal encoding based on graph theory is adopted; if not, the fourth step is executed: the best regular signed CSD encoding is adopted;

[0079] In the third step, the optimal encoding based on graph theory is adopted;

[0080] In the fourth step, the best regular signed CSD encoding is adopted;

[0081] In the fifth step, the hybrid encoding is completed, and the encoding result is obtained: that is, through the above selected only positive optimization coefficient solving method, the hybrid encoding of only positive optimization is completed.

[0082] Further, on the basis of hybrid encoding, the optimal coefficient hybrid encoding method has been realized, at this time the optimization of the total amount of adders and the number of adders on the critical path required by the fixed-point unit of the floating-point coefficient in the down-sampling digital filter has been realized. Further, from the level of multiply-add operation, the performance of the multiply-add operation unit required in the fixed-point unit of the floating-point coefficient in the down-sampling digital filter is optimized.

[0083] Specifically, the shift addition is used to replace the multiplication operation, so as to save the special multiplier. That is, all operations are reduced to addition, and only the addition needs to be optimized.

[0084] Wherein, the optimization design will be based on the advanced carry adder, and will be used in the full parallel mode. The hierarchical grouping method is adopted. On the basis of the traditional generation function and transfer function, the group generation signal G i:j and the group propagation signal P i:j are introduced, and are calculated according to the following formula:

[0085] G i:j =G i:k +P i:k ×G k-1:j

[0086] P i:j =P i:k ×P k-1:j

[0087] It should be noted that when the group generation signal G i:j and the group propagation signal P i:j are in the special case of the diagonal value, they can be simplified and calculated according to the following formula:

[0088] G i:i =G i =A×B

[0089] P i:i =P i =A⊕B

[0090] It should be noted that the definition of a grouped operation is calculated according to the following formula:

[0091] (G, P) × (G`, P`) = (G + P × G`, P × P`)

[0092] The operation operation satisfies the associative law, and the G and P functions are rearranged using the associative law, and are arranged in a tree structure, further shortening the critical path.

[0093] Please refer to Figure 3 , wherein the operation method of the optimized multiplication-addition operation optimization method is as follows:

[0094] First, replace the multiplication operation with shift addition;

[0095] Second, initialize the group generation signal and the group propagation signal according to the generation function and the transfer function;

[0096] Third, calculate each individual group generation signal and group propagation signal;

[0097] Fourth, use part of the group pre-computation in the Brent-Kung structure to generate odd carry;

[0098] Fifth, gradually reduce the number of additional PG units required in the Kogge-Stone structure in the later stage;

[0099] The sixth step is to calculate the even carry using odd carry in the final stage.

[0100] Step 7: Complete the calculation of the summation of the current position and the carry-out output.

[0101] It should be noted that the carry chain rearrangement method is an improvement based on three classic structures: Brent-Kung, Sklansky, and Kogge-Stone.

[0102] Specifically, in the Brent-Kung structure, the pre-generation of some groups is too fast, leading to a weakened connection between the remaining odd-numbered bits and the zeroth bit, and the logic stages are too lengthy; the Kogge-Stone structure calculates 2 using an additional PG unit. i The carry-over of -1 (i = 1, 2, ..., log2N) positions leads to increased wiring and resource consumption; the Sklansky structure compromises by calculating the intermediate leading bits together, which results in high fan-out and layout difficulties.

[0103] It should be noted that, with a slight increase in the number of logic levels, a trade-off between the number of logic levels L, the maximum fanout (Fanout), and the number of connections can achieve the optimal maximum fanout and number of connections. The final number of logic levels is log2N+2, the maximum fanout is 2, and the number of connections is 1.

[0104] Where N is the number of bits in the adder.

[0105] Further, please see Figure 4 The overall optimization design method is as follows:

[0106] The optimal fixed-point coding method, which combines graph theory-based optimal coding and hybrid coding, is as follows:

[0107] The first step is to perform fixed-point encoding operations based on the floating-point coefficients of the target filter characteristics;

[0108] The second step is to initialize the input set A and the graph set B.

[0109] The third step is to normalize all elements of set A: that is, to normalize the input coefficient set A by dividing each coefficient in the input coefficient set A by the largest divisor of a power of 2 to obtain the normalized coefficients and rewrite them into set A.

[0110] The fourth step is to calculate the addition cost required for the coefficients in set A: that is, to remove powers of 2 and duplicates from the set of positive odd-numbered input coefficients A, and then calculate the addition cost required for each coefficient, which is the number of additions required.

[0111] Fifth step, the cost of 1 in set A into the set B: that is, the third step of the cost of 1 corresponding to the addition of the coefficient into the graph set B, and the coefficient is deleted in set A;

[0112] Sixth step, the cost of 0 in set B can be generated: that is, the power of 2 of the coefficient in the graph set B is calculated;

[0113] Seventh step, the generated coefficient is stored in set C, and the random addition and subtraction is performed: that is, the coefficient generated in the fifth step is stored in set C, and the random addition and subtraction of two coefficients in set C is performed once;

[0114] Eighth step, the coefficient in set A is moved into set B: that is, the comparison is performed to find whether the same coefficient as the coefficient generated in the sixth step is included in set A, if yes, the same coefficient in set A is moved into the graph set B and is deleted in set A;

[0115] Ninth step, judge whether the coefficient is moved into set B: if yes, return to execute the sixth step: calculate the coefficient in set B which can generate cost 0; if no, execute the subsequent process, that is, tenth step: judge whether set A is empty;

[0116] Tenth step, judge whether set A is empty: that is, judge whether set A is empty after the ninth step is executed, if yes, end the whole coding generation process and exit the loop; if no, execute eleventh step: add new auxiliary coefficient to set B;

[0117] Eleventh step, add new auxiliary coefficient to set B: that is, repeat the fifth step to the ninth step, if the tenth step is entered, delete the original added auxiliary coefficient, and add new auxiliary coefficient to set B, until the loop is exited in the ninth step.

[0118] Twelfth step, compare the coding optimization effect of the two coding methods on the filter coefficient: that is, compare the result of the coefficient coding based on graph theory with the best regular signed CSD coding result;

[0119] Thirteenth step, judge whether the graph coding performance is better than the best CSD coding: that is, compare and judge, if yes, execute fourteenth step: adopt the optimal coding based on graph theory; if no, execute fifteenth step: adopt the best regular signed CSD coding;

[0120] Fourteenth step, adopt the optimal coding based on graph theory;

[0121] Fifteenth step, adopt the best regular signed CSD coding;

[0122] Sixteenth step, the hybrid coding is completed, and the coding result is obtained: that is, through the above selected only positive optimization coefficient solving method, the hybrid coding which only selects the positive optimization coefficient is completed.

[0123] It should be noted that,

[0124] The optimized multiplication-addition operation optimization method is calculated as follows:

[0125] First, replace the multiplication operation with shift-addition operation;

[0126] Second, initialize the group generation signal and group propagation signal according to the generating function and the transfer function;

[0127] Third, calculate the individual group generation signal and group propagation signal;

[0128] Fourth, use the Brent-Kung structure to calculate the odd carry;

[0129] Fifth, reduce the number of additional PG units in the Kogge-Stone structure at the later stage step by step;

[0130] Sixth, use the odd carry to calculate the even carry in the last stage.

[0131] Seventh, complete the calculation of the local sum and the carry output.

[0132] Specifically, the optimal fixed-point encoding method has realized the optimization of the total amount of adders and the number of adders in the critical path required by the floating-point coefficient fixed-point unit in the down-sampling digital filter. The multiplication-addition operation optimization improves the performance of the multiplication-addition operation unit in the fixed-point unit. The optimization design from the two levels of overall structure and individual unit improves the performance of the floating-point coefficient fixed-point unit in the down-sampling digital filter.

[0133] It should be noted that the RTL design circuit implementation code can be converted into a gate-level netlist hardware circuit under certain restrictions through constraint and synthesis. The power consumption and delay of the floating-point coefficient fixed-point unit circuit in the synthesized down-sampling digital filter are both significantly improved while the area remains almost unchanged.

Claims

1. A method of designing a Σ-Δ ADC down-sampling digital filter floating-point coefficient quantization unit, characterized in that, The application relates to an optimal fixed-point coding method and a multiplication-addition operation optimization method. The optimal fixed-point coding method is used for inputting floating-point coefficient required by a Sigma-Delta ADC down-sampling digital filter and outputting an optimal coded fixed-point quantization parameter to obtain an optimal floating-point coefficient fixed-point unit structure, and the multiplication-addition operation optimization method is used for optimizing an operation unit structure in the floating-point coefficient fixed-point unit of the Sigma-Delta ADC down-sampling digital filter. The optimal fixed-point coding method comprises the following steps: The optimal coding method based on graph theory and the hybrid coding combination method are connected; the optimal coding method based on graph theory is used for inputting floating-point coefficient required by a Sigma-Delta ADC down-sampling digital filter and outputting obtained optimal coding; the optimal coding output by the optimal coding method based on graph theory is input into the hybrid coding combination method, and finally optimal coded fixed-point quantization parameters are output. The multiplication-addition operation optimization method comprises the following steps: Firstly, shift addition is used to replace multiplication operation; Secondly, group generation signals and group propagation signals are initialized according to generation functions and transfer functions; Thirdly, each single group generation signal and group propagation signal are calculated; Fourthly, odd number carry is generated by using partial group preposition calculation in the Brent-Kung structure; Fifthly, the number of extra required PG units in the Kogge-Stone structure in a later stage is gradually reduced; Sixthly, even number carry is calculated by using odd number carry in the last stage; Seventhly, the calculation of the current sum and carry output is completed. The multiplication-addition operation optimization method optimizes the maximum fan-out number and the number of lines by rearranging the carry chain, configures the logic stage number as log2N+2, the maximum fan-out number as 2 and the number of lines as 1; wherein N is the addition bit number. Shift addition is used to replace multiplication operation, and full addition operation is adopted to realize multiplication-addition operation. The optimal coding method based on graph theory comprises the following steps: Firstly, input set A and graph set B are initialized; 2. The sigma-delta ADC down-sampling digital filter floating-point coefficient fixpointing unit design method of claim 1, wherein, Secondly, all elements in set A are positively and oddly processed; Thirdly, the addition cost required by coefficients in set A is calculated; Fourthly, coefficients with a cost of 1 in set A are moved into set B; Fifthly, coefficients capable of generating a cost of 0 in set B are calculated; Sixthly, the generated coefficients are stored in set C and are randomly added and subtracted; Seventhly, coefficients with the value in set A are moved into set B, and the value is the result of the random addition and subtraction of C in the sixth step; Eighthly, it is judged whether coefficients are moved into set B; if yes, the fifth step of calculating coefficients capable of generating a cost of 0 in set B is executed; if not, the subsequent process, that is, the ninth step of judging whether set A is empty, is executed; Ninthly, it is judged whether set A is empty; if yes, the whole coding generation process is ended and the loop is exited; If not, the tenth step of adding a new auxiliary coefficient into set B is executed; Tenthly, the new auxiliary coefficient is added into set B. The hybrid coding combination method comprises the following steps: Firstly, the coding optimization effects of two coding methods on filter coefficients are compared; ​ 3. The sigma-delta ADC down-sampling digital filter floating-point coefficient fixpointing unit design method of claim 1, wherein, ​ ​ ​ Second step, judging whether the graph theory coding performance is superior to the best CSD coding: if yes, executing third step: adopting the optimal coding based on graph theory; if no, executing fourth step: adopting the best regular signed CSD coding; Third step, adopting the optimal coding based on graph theory; Fourth step, adopting the best regular signed CSD coding; Fifth step, hybrid coding is completed, and the coding result is obtained.

4. The sigma-delta ADC down-sampling digital filter floating-point coefficient fixpointing unit design method of claim 2, wherein, The new auxiliary coefficients are added in the set B, and if the intermediate coefficients are all related to each other, the optimal coding result can be directly obtained, otherwise, the new auxiliary coefficients need to be added to establish the relationship between the coefficients.

5. The sigma-delta ADC down-sampling digital filter floating-point coefficient fixpointing unit design method of claim 2, wherein, The judgment that the graph theory coding performance is superior to the best CSD coding compares the optimal result of the coding optimization based on graph theory with the result of the best regular signed CSD coding, and adopts the optimal coding result of the two.

6. The sigma-delta ADC down-sampling digital filter floating-point coefficient fixpointing unit design method of claim 4, wherein, The new auxiliary coefficients are added, only considering the case of adding one variable, and the rest is not processed.

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