Hysteresis comparator circuit and system

Abstract

The invention provides a hysteresis comparator circuit and system, and relates to the technical field of integrated circuits, and the hysteresis comparator circuit comprises a differential comparison module, a tail current bias module, a self-adaptive shunt module and an output module. The output end of the tail current bias module, the first port of the differential comparison module and the second port of the adaptive shunt module are all connected to a first node, and the second port of the differential comparison module is connected with the second port of the output module. When the common-mode input range is normal, the adaptive shunt module is turned off, and the bias current output by the tail current bias module flows to the first port of the differential comparison module. When the common-mode input range is abnormal, the self-adaptive shunt module is conducted, and the self-adaptive shunt module is used for extracting part of bias current output by the tail current bias module so as to reduce the value of current flowing to the first port of the differential comparison module. The influence of the change of the common-mode voltage on the current flowing to the first port of the differential comparison module is weakened, so that the common-mode input range of the hysteresis comparator is widened.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a hysteresis comparator circuit and system. Background Art

[0002] The hysteresis comparator is named because its forward flip voltage and reverse flip voltage lag each other. Since the hysteresis comparator has a dead zone voltage near the zero point, it is more suitable for some noise interference environments. The common mode input range is an important parameter indicator of the hysteresis comparator, which can affect the dynamic working state of the hysteresis comparator. The common mode input range refers to the range of common mode voltages in which the hysteresis comparator can work normally. When the common mode voltage is within this range, the hysteresis comparator can accurately compare the size of the two input voltages and output the correct comparison result.

[0003] Existing hysteresis comparators only focus on the static working state of the transistor, without considering the dynamic working state, that is, whether the hysteresis comparator can flip normally when the common-mode voltage changes. For example, when the hysteresis comparator is applied to an undervoltage protection circuit in a noise interference environment, its flip voltage is required to be higher. However, an excessively high flip voltage will reduce the common-mode input range, resulting in an abnormal common-mode input range. If the common-mode voltage deviates from the common-mode input range at this time, the hysteresis comparator will not work properly.

[0004] Therefore, how to improve the common-mode input range of the hysteresis comparator and ensure that the hysteresis comparator can work normally is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The purpose of the present application is to provide a hysteresis comparator circuit and system to improve the common-mode input range of the hysteresis comparator and ensure that the hysteresis comparator can operate normally.

[0006] In order to achieve the above purpose, the technical solution adopted in this application is as follows:

[0007] On the one hand, the present application provides a hysteresis comparator circuit, including: a differential comparison module, a tail current bias module, an adaptive current shunting module and an output module;

[0008] The first port of the tail current bias module, the first port of the adaptive shunt module and the first port of the output module are all connected to the power supply; the output end of the tail current bias module, the first port of the differential comparison module and the second port of the adaptive shunt module are all connected to the first node, and the second port of the differential comparison module is connected to the second port of the output module; the third port of the differential comparison module, the third port of the adaptive shunt module and the third port of the output module are all grounded;

[0009] The tail current bias module is used to provide a bias current for the first port of the differential comparison module;

[0010] When the common mode input range is normal, the adaptive current shunting module is turned off, and the bias current output by the tail current bias module flows to the first port of the differential comparison module;

[0011] When the common mode input range is abnormal, the adaptive shunt module is turned on, and the adaptive shunt module is used to extract part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module.

[0012] Further, the adaptive current splitting module includes a first current mirror and a second current mirror;

[0013] The first port and the second port of the first current mirror are both connected to the power supply, the third port of the first current mirror is connected to the first node, the fourth port of the first current mirror is connected to the first port of the second current mirror, the second port of the second current mirror is connected to the first node, and the third port and the fourth port of the second current mirror are both grounded;

[0014] When the common mode input range is normal, the first current mirror and the second current mirror are both turned off, so that the bias current output by the tail current bias module flows to the first port of the differential comparison module;

[0015] When the common mode input range is abnormal, the first current mirror and the second current mirror are both turned on, and the second port of the second current mirror extracts part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module.

[0016] Further, the first current mirror includes a first PMOS tube and a second PMOS tube, and the second current mirror includes a first NMOS tube and a second NMOS tube;

[0017] The source of the first PMOS tube and the source of the second PMOS tube are both connected to the power supply, the drain of the first PMOS tube is connected to the first node, and the gate of the first PMOS tube is connected to the drain of the first PMOS tube and the gate of the second PMOS tube respectively;

[0018] The drain of the first NMOS tube is connected to the drain of the second PMOS tube, the gate of the first NMOS tube is connected to the drain of the first NMOS tube and the gate of the second NMOS tube respectively, the drain of the second NMOS tube is connected to the first node; the source of the first NMOS tube and the source of the second NMOS tube are both grounded.

[0019] Further, the differential comparison module includes a reverse input unit, a non-reversal input unit, a third current mirror and a fourth current mirror;

[0020] The first port of the reverse input unit and the first port of the same-direction input unit are both connected to the first node; the first port of the third current mirror, the first port of the fourth current mirror and the output end of the reverse input unit are all connected to the second node; the second port of the third current mirror, the second port of the fourth current mirror and the output end of the same-direction input unit are all connected to the third node; the third port of the third current mirror, the fourth port of the third current mirror, the third port of the fourth current mirror and the fourth port of the fourth current mirror are all grounded.

[0021] Further, the reverse input unit includes a third PMOS tube, the source of the third PMOS tube is connected to the first node, the drain of the third PMOS tube is connected to the second node, and the gate of the third PMOS tube is the reverse input terminal of the differential comparison module;

[0022] The non-inverting input unit includes a fourth PMOS tube, a source of the fourth PMOS tube is connected to the first node, a drain of the fourth PMOS tube is connected to the third node, and a gate of the fourth PMOS tube is the non-inverting input terminal of the differential comparison module.

[0023] Further, the third current mirror includes a third NMOS tube and a fourth NMOS tube, the drain of the third NMOS tube is connected to the second node, the gate of the third NMOS tube is respectively connected to the drain of the third NMOS tube and the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the third node, and the source of the third NMOS tube and the source of the fourth NMOS tube are both grounded;

[0024] The fourth current mirror includes a fifth NMOS tube and a sixth NMOS tube, the drain of the fifth NMOS tube is connected to the second node, the gate of the fifth NMOS tube is respectively connected to the drain of the sixth NMOS tube and the gate of the sixth NMOS tube, the drain of the sixth NMOS tube is connected to the third node, and the source of the fifth NMOS tube and the source of the sixth NMOS tube are both grounded.

[0025] Further, the output module includes a fifth current mirror, a seventh NMOS tube and an eighth NMOS tube;

[0026] The first port and the second port of the fifth current mirror are both connected to the power supply;

[0027] The drain of the seventh NMOS tube is connected to the third port of the fifth current mirror, the gate of the seventh NMOS tube is connected to the second node, and the source of the seventh NMOS tube is grounded;

[0028] The drain of the eighth NMOS tube is connected to the fourth port of the fifth current mirror as the output end of the output module, the gate of the eighth NMOS tube is connected to the third node, and the source of the eighth NMOS tube is grounded.

[0029] Further, the fifth current mirror includes a fifth PMOS tube and a sixth PMOS tube; the source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the power supply, the drain of the fifth PMOS tube is connected to the drain of the seventh NMOS tube, the gate of the fifth PMOS tube is respectively connected to the drain of the fifth PMOS tube and the gate of the sixth PMOS tube, and the drain of the sixth PMOS tube is connected to the drain of the eighth NMOS tube as the output end of the output module.

[0030] Furthermore, the tail current bias module includes a seventh PMOS tube; the source of the seventh PMOS tube is connected to the power supply, the drain of the seventh PMOS tube is connected to the first node, and the gate of the seventh PMOS tube serves as the bias voltage input terminal of the tail current bias module.

[0031] On the other hand, the present application further provides a hysteresis comparator system, which includes the hysteresis comparator circuit as described in any one of the aforementioned embodiments.

[0032] Compared with the prior art, this application has the following beneficial effects:

[0033] The present application provides a hysteresis comparator circuit and system, including: a differential comparison module, a tail current bias module, an adaptive shunt module and an output module. When the common-mode input range is normal, the common-mode voltage is within the common-mode input range. At this time, the adaptive shunt module is turned off, and the bias current output by the tail current bias module all flows to the first port of the differential comparison module, and the hysteresis comparator circuit can work normally. When the common-mode input range is abnormal, that is, when the common-mode input range is reduced, the bias current output by the tail current bias module will increase. In order to stabilize the current flowing to the first port of the differential comparison module, the adaptive shunt module is turned on at this time. The adaptive shunt module is used to extract part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module. Ensure that the current flowing to the first port of the differential comparison module is weakened by the change in common-mode voltage, thereby ensuring that the hysteresis comparator circuit can work normally and improving the common-mode input range of the hysteresis comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians of the art without making creative work are within the scope of protection of the present application.

[0035] Figure 1 A schematic diagram of the structure of an undervoltage protection circuit provided in this application;

[0036] Figure 2 One of the structural schematic diagrams of a hysteresis comparator circuit provided in this application;

[0037] Figure 3 The second structural diagram of a hysteresis comparator circuit provided by the present application;

[0038] Figure 4 A structural diagram of a differential comparison module provided in this application;

[0039] Figure 5 A schematic diagram of the structure of an output module provided in this application;

[0040] Figure 6 One of the principle schematic diagrams of a hysteresis comparator circuit provided in this application;

[0041] Figure 7 This is the second principle schematic diagram of a hysteresis comparator circuit provided in this application.

[0042] Figure markings: 10 - hysteresis comparator circuit; 100 - differential comparison module; 110 - reverse input unit; 120 - same direction input unit; 130 - third current mirror; 140 - fourth current mirror; 200 - tail current bias module; 300 - adaptive shunt module; 310 - first current mirror; 320 - second current mirror; 400 - output module; 410 - fifth current mirror. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0044] In the description of this application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0045] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0046] As mentioned in the background technology, the hysteresis comparator is named because its forward flip voltage and reverse flip voltage lag each other. Currently, the hysteresis comparator is almost always implemented through a positive feedback loop, which is divided into external positive feedback and internal positive feedback. However, since the external positive feedback needs to be implemented through a resistor, and the resistor area in the integrated circuit is large and the accuracy is poor, the internal positive feedback hysteresis comparator is more widely used.

[0047] Since the hysteresis comparator has a dead zone voltage near the zero point, the hysteresis comparator is suitable for various noise and interference environments, such as over-temperature protection and under-voltage protection circuits in GaN power device drive circuits.

[0048] like Figure 1 The figure shows an undervoltage protection circuit composed of a hysteresis comparator and a voltage divider resistor. COMP is a hysteresis comparator, and R1, R2, and R3 form a resistor voltage divider network. The power supply voltage V DD The voltage is divided by resistors R1, R2 and R3, and resistor R3 is connected in parallel with MOS tube Q. The detected voltage enters the reverse input terminal of the hysteresis comparator COMP, and the reference voltage V generated by the band gap REF Entering the non-inverting input terminal of the hysteresis comparator COMP, the hysteresis comparator COMP compares the two input voltages and outputs the comparison result.

[0049] It should be noted that the average value of the voltages at the two input terminals of the hysteresis comparator is called the common-mode voltage, and the difference between the two input terminal voltages is called the differential-mode voltage. Only when the common-mode voltage is within the common-mode input range of the hysteresis comparator can the hysteresis comparator accurately compare the differential-mode voltage and output the correct comparison result.

[0050] When the hysteresis comparator is used in an undervoltage protection circuit in a noisy environment, its flip voltage is required to be high. However, too high a flip voltage will reduce the common-mode input range, resulting in an abnormal common-mode input range. If the common-mode voltage deviates from the common-mode input range at this time, the hysteresis comparator cannot output the correct comparison result, which will cause the chip to continue to work at high temperature, causing irreversible damage.

[0051] Therefore, how to improve the common-mode input range of the hysteresis comparator and ensure that the hysteresis comparator can work normally is a technical problem that needs to be solved urgently by those skilled in the art.

[0052] To solve the above technical problems, please refer to Figure 2 An embodiment of the present application provides a hysteresis comparator circuit 10, including: a differential comparison module 100, a tail current bias module 200, an adaptive current shunting module 300 and an output module 400.

[0053] The first port of the tail current bias module 200, the first port of the adaptive current shunting module 300 and the first port of the output module 400 are all connected to the power supply V DD The output end of the tail current bias module 200, the first port of the differential comparison module 100 and the second port of the adaptive current shunting module 300 are all connected to the first node N1, and the second port of the differential comparison module 100 is connected to the second port of the output module 400. The third port of the differential comparison module 100, the third port of the adaptive current shunting module 300 and the third port of the output module 400 are all grounded.

[0054] The tail current bias module 200 is used to provide a bias current for the differential comparison module 100 .

[0055] The differential comparison module 100 is used to convert the voltage V inp and the reverse input voltage V inn The comparison is performed and the differential signal is output to the second port of the output module 400 .

[0056] The output module 400 is used to realize the conversion of the differential signal to a single-stage output signal, and finally outputs a digital signal high level or low level V out .

[0057] When the common-mode input range is normal, that is, the common-mode voltage (V inp With V innWhen the average value of the common mode input is within the common mode input range, the adaptive current shunt module 300 is turned off (i.e., I C =0). At this time, the bias current output by the tail current bias module 200 all flows to the first port (i.e., I B =I A ). The differential comparison module 100 has a bias current I A Under the effect of can ensure that the output module 400 outputs the correct comparison result V out .

[0058] If the hysteresis comparator circuit 10 is applied to a noise interference environment, a higher flip voltage is required, but a higher flip voltage will reduce the common mode input range, that is, the common mode input range is abnormal, and the bias current I output by the tail current bias module 200 is increased. A Increase.

[0059] In order to stabilize the current I flowing to the first port of the differential comparison module 100 B In the embodiment of the present application, when the common mode input range is abnormal, the adaptive current splitting module 300 is turned on (ie, I C ≠0), and the adaptive current shunting module 300 can extract part of the bias current I output by the tail current bias module 200 A , so as to reduce the current value (i.e., I B =I A -I C ), so that the current value I at the first port of the differential comparison module 100 B The influence of common mode voltage changes is reduced to achieve stable I B The purpose of size.

[0060] That is, when the common-mode input range is abnormal, compared with when the common-mode input range is normal, although I A will increase, but since the adaptive current splitting module 300 is turned on at this time, I B The size of remains basically unchanged, thus avoiding the comparison result error caused by the sudden change of the common-mode voltage of the hysteresis comparator and improving the common-mode input range of the hysteresis comparator.

[0061] To better understand the technical solution of this application, please refer to Figure 3 In the embodiment of the present application, the adaptive current splitting module 300 includes a first current mirror 310 and a second current mirror 320 .

[0062] The first port and the second port of the first current mirror 310 are both connected to the power supply V DDThe third port of the first current mirror 310 is connected to the first node N1, the fourth port of the first current mirror 310 is connected to the first port of the second current mirror 320, the second port of the second current mirror 320 is connected to the first node N1, and the third port and the fourth port of the second current mirror 320 are both grounded.

[0063] It should be noted that the first port and the second port of the first current mirror 310 are the first ports of the adaptive shunt module 300, the third port of the first current mirror 310 and the second port of the second current mirror 320 are the second ports of the adaptive shunt module 300, and the third port and the fourth port of the second current mirror 320 are the third port of the adaptive shunt module 300.

[0064] When the common mode input range is normal, the first current mirror 310 and the second current mirror 320 are both turned off, so that the bias current output by the tail current bias module 200 flows entirely to the first port of the differential comparison module 100, i.e., I total =I p7 .

[0065] When the common-mode input range is abnormal, it will cause I p7 Increase, in order to stabilize I total The first current mirror 310 and the second current mirror 320 are both turned on, and the second port of the second current mirror 320 extracts part of the bias current I output by the tail current bias module 200. p7 (The magnitude of the extracted current is I n2 ), so as to reduce the current value flowing to the first port of the differential comparison module 100, that is, I total =I p7 -I n2 .

[0066] Furthermore, the first current mirror 310 includes a first PMOS transistor PM1 and a second PMOS transistor PM2 , and the second current mirror 320 includes a first NMOS transistor NM1 and a second NMOS transistor NM2 .

[0067] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the power supply V DD The drain of the first PMOS transistor PM1 is connected to the first node N1, and the gate of the first PMOS transistor PM1 is connected to the drain of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 respectively.

[0068] The drain of the first NMOS transistor NM1 is connected to the drain of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1 is connected to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 respectively, the drain of the second NMOS transistor NM2 is connected to the first node N1. The source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are both grounded.

[0069] Optionally, the tail current bias module 200 includes a seventh PMOS transistor PM7. The source of the seventh PMOS transistor PM7 is connected to the power supply V DD The drain of the seventh PMOS transistor PM7 is connected to the first node N1, and the gate of the seventh PMOS transistor PM7 serves as the bias voltage input terminal of the tail current bias module 200, for receiving the bias voltage V bias .

[0070] Among them, the drain current I of the seventh PMOS tube PM7 is p7 The size is:

[0071]

[0072] Among them, k′ p7 =μ np7 C oxp7 , μ np7 is the carrier mobility of the seventh PMOS tube PM7, C oxp7 is the gate oxide capacitance per unit area of ​​the seventh PMOS transistor PM7. (W / L) p7 is the quotient of the channel width and channel length of the seventh PMOS transistor PM7, V thp7 is the threshold voltage of the seventh PMOS tube PM7, λ p7 is the channel length modulation parameter of the seventh PMOS transistor PM7.

[0073] When the common-mode input range is abnormal (ie, the common-mode input range is reduced), the first node voltage V N1 Since the gate and drain of the first PMOS transistor PM1 are both connected to the first node N1, the first PMOS transistor PM1 is turned on. According to the current mirror effect of the first PMOS transistor PM1 and the second PMOS transistor PM2, the second PMOS transistor PM2 is also turned on (ie, the first current mirror 310 is turned on).

[0074] After the second PMOS transistor PM2 is turned on, it charges the gate and drain of the first NMOS transistor NM1, so that the first NMOS transistor NM1 is turned on. According to the current mirror effect of the first NMOS transistor NM1 and the second NMOS transistor NM2, the second NMOS transistor NM2 is also turned on (that is, the second current mirror 320 is turned on).

[0075] From formula (1), we can see that Ip7 With V N1 Inversely proportional, when V N1 When I p7 However, since the second NMOS tube NM2 is turned on, the drain of the second NMOS tube NM2 will extract part of I p7 , that is, the current I flowing through the second NMOS tube NM2 n2 will increase, making I p7 and I n2 The tail current I obtained after subtraction total The influence of common mode voltage changes is reduced, stabilizing I total The size of ensures that the hysteresis comparator circuit 10 can also output a correct comparison result when the common-mode voltage changes dynamically, thereby improving the common-mode input range of the hysteresis comparator circuit 10.

[0076] To better understand the overall working principle of the hysteresis comparator circuit 10, please refer to Figure 4 , the specific structure of the differential comparison module 100 is first described below.

[0077] In the embodiment of the present application, the differential comparison module 100 includes an inverting input unit 110 , a non-inverting input unit 120 , a third current mirror 130 and a fourth current mirror 140 .

[0078] The first port of the reverse input unit 110 and the first port of the same-direction input unit 120 are both connected to the first node N1. The first port of the third current mirror 130, the first port of the fourth current mirror 140 and the output end of the reverse input unit 110 are all connected to the second node N2. The second port of the third current mirror 130, the second port of the fourth current mirror 140 and the output end of the same-direction input unit 120 are all connected to the third node N3. The third port of the third current mirror 130, the fourth port of the third current mirror 130, the third port of the fourth current mirror 140 and the fourth port of the fourth current mirror 140 are all grounded.

[0079] Furthermore, the reverse input unit 110 includes a third PMOS transistor PM3 , a source of the third PMOS transistor PM3 is connected to the first node N1 , a drain of the third PMOS transistor PM3 is connected to the second node N2 , and a gate of the third PMOS transistor PM3 is a reverse input terminal of the differential comparison module 100 .

[0080] The non-inverting input unit 120 includes a fourth PMOS transistor PM4 , a source of which is connected to the first node N1 , a drain of which is connected to the third node N3 , and a gate of which is the non-inverting input terminal of the differential comparison module 100 .

[0081] The third current mirror 130 includes a third NMOS tube NM3 and a fourth NMOS tube NM4, the drain of the third NMOS tube NM3 is connected to the second node N2, the gate of the third NMOS tube NM3 is respectively connected to the drain of the third NMOS tube NM3 and the gate of the fourth NMOS tube NM4, the drain of the fourth NMOS tube NM4 is connected to the third node N3, and the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are both grounded.

[0082] The fourth current mirror 140 includes a fifth NMOS tube NM5 and a sixth NMOS tube NM6, the drain of the fifth NMOS tube NM5 is connected to the second node N2, the gate of the fifth NMOS tube NM5 is respectively connected to the drain of the sixth NMOS tube NM6 and the gate of the sixth NMOS tube NM6, the drain of the sixth NMOS tube NM6 is connected to the third node N3, and the source of the fifth NMOS tube NM5 and the source of the sixth NMOS tube NM6 are both grounded.

[0083] The specific structure of the output module 400 is as follows: Figure 5 As shown, in the embodiment of the present application, the output module 400 includes a fifth current mirror 410, a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8.

[0084] The first port and the second port of the fifth current mirror 410 are both connected to the power supply V DD The drain of the seventh NMOS tube NM7 is connected to the third port of the fifth current mirror 410, the gate of the seventh NMOS tube NM7 is connected to the second node N2, and the source of the seventh NMOS tube NM7 is grounded. The drain of the eighth NMOS tube NM8 is connected to the fourth port of the fifth current mirror 410 as the output end of the output module 400, the gate of the eighth NMOS tube NM8 is connected to the third node N3, and the source of the eighth NMOS tube NM8 is grounded.

[0085] Furthermore, the fifth current mirror 410 includes a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6. The source of the fifth PMOS transistor PM5 and the source of the sixth PMOS transistor PM6 are both connected to the power supply V DD The drain of the fifth PMOS tube PM5 is connected to the drain of the seventh NMOS tube NM7, the gate of the fifth PMOS tube PM5 is connected to the drain of the fifth PMOS tube PM5 and the gate of the sixth PMOS tube PM6 respectively, and the drain of the sixth PMOS tube PM6 is connected to the drain of the eighth NMOS tube NM8 as the output end of the output module 400.

[0086] Based on the above design, the overall structure of the hysteresis comparator circuit 10 is as follows: Figure 6 and Figure 7As shown. There are two feedback loops in this circuit: one is the series current negative feedback introduced through the common source node of PM3 and PM4 (i.e., the first node N1), and the other is the parallel voltage positive feedback introduced through NM4 and NM5. Only when the positive feedback effect is greater than the negative feedback effect, the hysteresis comparator will show the hysteresis effect, and the forward flip voltage and the reverse flip voltage will be different.

[0087] To analyze the positive flip voltage law of the hysteresis comparator circuit, please refer to Figure 6 , assuming V inn >>V inp , and the bias current I p7 All flow to the first port of the differential comparison module 100, PM3 is turned off, PM4 is turned on, and I p7 All flows through PM4. p4 =I p7 , I p3 =0, and V N2 <V N3 .

[0088] Since the gate voltage V N3 Since NM5 and NM6 form a current mirror relationship, and NM8 and NM5 also form a current mirror relationship, NM5, NM6, and NM8 are all turned on. At this time, the second node voltage V N2 Pulled down to ground by the drain current of NM5, that is, V N2 =0.

[0089] Since V N2 =0, and NM3 and NM4 form a current mirror relationship, and NM7 and NM4 also form a current mirror relationship, so NM3, NM4, and NM7 are all turned off. At this time, since NM8 is turned on and NM7 is turned off, the output end of the hysteresis comparator circuit is pulled down to ground by NM8, that is, V out =0.

[0090] If V inn begins to decrease, at which point the partial bias current I p7 Start to flow through PM3, that is, I p3 Starting from 0, I p4 starts to decrease. When I p3 =I n5 When the inverter structure composed of PM3 and NM5 reaches the flip point, since NM4 is still in the off state, I p4 =I n6 .

[0091] When I p3 =I n5 When , the following formula is satisfied:

[0092]

[0093] I p3 +I p4 =I p7 (3)

[0094] At this time, I p3 The size is:

[0095]

[0096] The second node voltage V is obtained by formulas (2), (3) and (4): N2 The potential is:

[0097]

[0098] If V N2 If the voltage of NM3 is high enough to form an inversion layer in NM3 (i.e., NM3 changes from the original off state to the on state), then NM3, NM4, and NM7 are all turned on, and the positive feedback loop composed of NM4 and NM5 will start, so V N2 and V N3 The polarity of V N2 >V N3 ). At this time, NM5, NM6, and NM8 are all turned off. Since NM7 is turned on, PM5 and PM6 are also turned on, and the output signal V out From 0 to V DD .

[0099] Ignoring the channel length modulation effect, the forward flip voltage of the hysteresis comparator circuit is obtained from formulas (2), (3), and (4): for:

[0100]

[0101] Among them, V gsp4 is the gate-source voltage of PM4, V gsp3 is the gate-source voltage of PM3, and the gate of PM4 is the non-inverting input terminal of the hysteresis comparator, and the gate of PM3 is the reverse input terminal of the hysteresis comparator.

[0102] At this point, the hysteresis comparator circuit has completed a normal comparison. According to formula (6), the flip voltage of the hysteresis comparator circuit is Too high a flip-flop voltage will reduce the common-mode input range of the hysteresis comparator.

[0103] The common-mode input range is a very important parameter of the hysteresis comparator, which determines its application scenario to a certain extent. The common-mode input range of the hysteresis comparator is defined as the range where all transistors are in the saturation region. Based on this definition, Figure 6 The common-mode input range of the circuit shown is:

[0104] -V gsp3 =V N1 -V cm ≥|V thp3 | (7)

[0105] V cm +∣V thp3 ∣≥V thn3 (8)

[0106] V thn3 -|V thp3 |≤V cm ≤V DD -V OV_P7 -|V thp3 | (9)

[0107] Among them, V cm is the common mode voltage, V thp3 is the threshold voltage of PM3, V thn3 is the threshold voltage of NM3, V OV_P7 is the overdrive voltage of PM7.

[0108] The common-mode input range affects the dynamic operation of the hysteresis comparator. As mentioned above, only when V N2 When it is high enough to form an inversion layer in NM3, the state of the hysteresis comparator will be flipped.

[0109]

[0110] That is, when V N2 When the above formula (10) is satisfied, the positive feedback loop composed of NM4 and NM5 is activated, V N2 and V N3 The hysteresis comparator can work properly only when the polarity of is reversed.

[0111] From formula (10), we can see that V N2 With V N1 is proportional to V N2 with I p7 Inversely proportional. From formula (1), we can see that I p7 With V N1 Inversely proportional.

[0112] When the hysteresis comparator is used in a noise interference scenario, its flip voltage is required to be larger. However, a larger flip voltage will reduce the common-mode input range, causing the common-mode voltage to deviate from the common-mode input range. N1 Reduce, I p7 Increase, V N2 Decreases. At this time, V N2 is too low to meet the condition in formula (10), so the positive feedback loop composed of NM4 and NM5 cannot be started. N2 Unable to pull high, V N3 It cannot be pulled low, which ultimately causes the hysteresis comparator to be unable to output the correct comparison result.

[0113] To ensure that the hysteresis comparator can work properly in a noise interference scenario, refer to Figure 7 In the embodiment of the present application, when the common mode voltage deviates from the common mode input range, V N1 When the voltage drops, since the gate and drain of PM1 in the adaptive current shunting module 300 are both connected to the first node N1, V N1 PM1 is turned on when falling.

[0114] At this time, the current I flowing through PM1 p1 Size:

[0115]

[0116] According to the current mirror relationship between PM1 and PM2, PM2 is also turned on and charges the gate and drain of NM1, so NM1 is turned on. According to the current mirror relationship between NM1 and NM2, NM2 is also turned on.

[0117] At this time, the current I flowing through NM2 n2 Size:

[0118]

[0119]

[0120] Since the drain of NM2 is connected to the first node N1 (equivalent to the drain of PM7), NM2 will extract part of the bias current I output by PM7. p7 , the current drawn is I n2 At this time, the bias current I flowing to the first port of the differential comparison module 100 is total The size is:

[0121] I total =I p7 -I n2 (14)

[0122] At this time, the conditions for the hysteresis comparator to work normally are:

[0123]

[0124] According to formulas (11) and (13), I n2 With V N1 Inversely proportional to. According to formula (1), I p7 With V N1 Inversely proportional.

[0125] Based on the above design, when the common-mode voltage deviates from the common-mode input range, V N1 When I p7 Increase, but at the same time I n2 will also increase, so according to formula (14), I p7 and I n2 The tail current I obtained after subtraction total The influence of common mode voltage change is weakened, and a stable tail current I is achieved. total The purpose of V in formula (15) is N2 Compared with V in formula (10) N2 It has a stronger ability to suppress input common-mode changes, thereby avoiding comparison result errors caused by common-mode voltage mutations of the hysteresis comparator, improving the common-mode input range of the hysteresis comparator, and broadening the application range of the hysteresis comparator.

[0126] Optionally, an embodiment of the present application further provides a hysteresis comparator system, which includes the hysteresis comparator circuit as described in any of the aforementioned implementations.

[0127] In summary, an embodiment of the present application provides a hysteresis comparator circuit and system, including: a differential comparison module, a tail current bias module, an adaptive shunt module and an output module. Among them, the first port of the tail current bias module, the first port of the adaptive shunt module and the first port of the output module are all connected to the power supply. The output end of the tail current bias module, the first port of the differential comparison module and the second port of the adaptive shunt module are all connected to the first node, and the second port of the differential comparison module is connected to the second port of the output module. The third port of the differential comparison module, the third port of the adaptive shunt module and the third port of the output module are all grounded.

[0128] When the common-mode input range is normal, the common-mode voltage is within the common-mode input range. At this time, the adaptive shunt module is turned off, and the bias current output by the tail current bias module all flows to the first port of the differential comparison module, and the hysteresis comparator circuit can work normally.

[0129] When the common-mode input range is abnormal (i.e., when the common-mode input range is reduced), the bias current output by the tail current bias module will increase. In order to stabilize the current flowing to the first port of the differential comparison module, the adaptive shunt module is turned on at this time. The adaptive shunt module is used to extract part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module. Ensure that the current flowing to the first port of the differential comparison module is weakened by the change in common-mode voltage, thereby ensuring that the hysteresis comparator circuit can work normally and improving the common-mode input range of the hysteresis comparator.

[0130] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0131] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A hysteresis comparator circuit, characterized in that: The hysteresis comparator circuit includes: a differential comparison module, a tail current bias module, an adaptive current shunting module and an output module; The first port of the tail current bias module, the first port of the adaptive shunt module and the first port of the output module are all connected to the power supply; the output end of the tail current bias module, the first port of the differential comparison module and the second port of the adaptive shunt module are all connected to the first node, and the second port of the differential comparison module is connected to the second port of the output module; the third port of the differential comparison module, the third port of the adaptive shunt module and the third port of the output module are all grounded; The tail current bias module is used to provide a bias current for the first port of the differential comparison module; When the common mode input range is normal, the adaptive current shunting module is turned off, and the bias current output by the tail current bias module flows to the first port of the differential comparison module; When the common mode input range is abnormal, the adaptive shunt module is turned on, and the adaptive shunt module is used to extract part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module.

2. The hysteresis comparator circuit according to claim 1, characterized in that: The adaptive current shunting module includes a first current mirror and a second current mirror; The first port and the second port of the first current mirror are both connected to the power supply, the third port of the first current mirror is connected to the first node, the fourth port of the first current mirror is connected to the first port of the second current mirror, the second port of the second current mirror is connected to the first node, and the third port and the fourth port of the second current mirror are both grounded; When the common mode input range is normal, the first current mirror and the second current mirror are both turned off, so that the bias current output by the tail current bias module flows to the first port of the differential comparison module; When the common mode input range is abnormal, the first current mirror and the second current mirror are both turned on, and the second port of the second current mirror extracts part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module.

3. The hysteresis comparator circuit according to claim 2, characterized in that: The first current mirror includes a first PMOS tube and a second PMOS tube, and the second current mirror includes a first NMOS tube and a second NMOS tube; The source of the first PMOS tube and the source of the second PMOS tube are both connected to the power supply, the drain of the first PMOS tube is connected to the first node, and the gate of the first PMOS tube is connected to the drain of the first PMOS tube and the gate of the second PMOS tube respectively; The drain of the first NMOS tube is connected to the drain of the second PMOS tube, the gate of the first NMOS tube is connected to the drain of the first NMOS tube and the gate of the second NMOS tube respectively, the drain of the second NMOS tube is connected to the first node; the source of the first NMOS tube and the source of the second NMOS tube are both grounded.

4. The hysteresis comparator circuit according to claim 1, characterized in that: The differential comparison module includes a reverse input unit, a non-reversal input unit, a third current mirror and a fourth current mirror; The first port of the reverse input unit and the first port of the same-direction input unit are both connected to the first node; the first port of the third current mirror, the first port of the fourth current mirror and the output end of the reverse input unit are all connected to the second node; the second port of the third current mirror, the second port of the fourth current mirror and the output end of the same-direction input unit are all connected to the third node; the third port of the third current mirror, the fourth port of the third current mirror, the third port of the fourth current mirror and the fourth port of the fourth current mirror are all grounded.

5. The hysteresis comparator circuit according to claim 4, characterized in that: The reverse input unit comprises a third PMOS tube, the source of the third PMOS tube is connected to the first node, the drain of the third PMOS tube is connected to the second node, and the gate of the third PMOS tube is the reverse input terminal of the differential comparison module; The non-inverting input unit includes a fourth PMOS tube, a source of the fourth PMOS tube is connected to the first node, a drain of the fourth PMOS tube is connected to the third node, and a gate of the fourth PMOS tube is the non-inverting input terminal of the differential comparison module.

6. The hysteresis comparator circuit according to claim 4, characterized in that: The third current mirror comprises a third NMOS tube and a fourth NMOS tube, the drain of the third NMOS tube is connected to the second node, the gate of the third NMOS tube is connected to the drain of the third NMOS tube and the gate of the fourth NMOS tube respectively, the drain of the fourth NMOS tube is connected to the third node, and the source of the third NMOS tube and the source of the fourth NMOS tube are both grounded; The fourth current mirror includes a fifth NMOS tube and a sixth NMOS tube, the drain of the fifth NMOS tube is connected to the second node, the gate of the fifth NMOS tube is respectively connected to the drain of the sixth NMOS tube and the gate of the sixth NMOS tube, the drain of the sixth NMOS tube is connected to the third node, and the source of the fifth NMOS tube and the source of the sixth NMOS tube are both grounded.

7. The hysteresis comparator circuit according to claim 6, characterized in that: The output module includes a fifth current mirror, a seventh NMOS tube and an eighth NMOS tube; The first port and the second port of the fifth current mirror are both connected to the power supply; The drain of the seventh NMOS tube is connected to the third port of the fifth current mirror, the gate of the seventh NMOS tube is connected to the second node, and the source of the seventh NMOS tube is grounded; The drain of the eighth NMOS tube is connected to the fourth port of the fifth current mirror as the output end of the output module, the gate of the eighth NMOS tube is connected to the third node, and the source of the eighth NMOS tube is grounded.

8. The hysteresis comparator circuit according to claim 7, characterized in that: The fifth current mirror includes a fifth PMOS tube and a sixth PMOS tube; The source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the power supply, the drain of the fifth PMOS tube is connected to the drain of the seventh NMOS tube, the gate of the fifth PMOS tube is respectively connected to the drain of the fifth PMOS tube and the gate of the sixth PMOS tube, and the drain of the sixth PMOS tube is connected to the drain of the eighth NMOS tube as the output end of the output module.

9. The hysteresis comparator circuit according to claim 1, characterized in that: The tail current bias module includes a seventh PMOS tube; The source of the seventh PMOS tube is connected to the power supply, the drain of the seventh PMOS tube is connected to the first node, and the gate of the seventh PMOS tube serves as the bias voltage input terminal of the tail current bias module.

10. A hysteresis comparator system, characterized in that: The hysteresis comparator system comprises the hysteresis comparator circuit according to any one of claims 1-9.

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