Level shifter

Abstract

The invention provides a level shifter which obtains an appropriate output signal even if the level of a power supply voltage supplied to an input stage circuit drops. The level shifter includes: an input stage circuit to which an input signal of a relatively low level is input; and the output stage circuit is used for converting the input signal into a signal with a relatively high level and outputting the signal. The output stage circuit includes: first and second transistors to which complementary signals generated according to an input signal are respectively input; a first switching circuit, a main path of which is connected to the first transistor, which is turned on when the second transistor is turned on, and which is turned off when the second transistor is turned off; and a second switching circuit, the main path of which is connected to the second transistor, which is turned on when the first transistor is turned on, and which is turned off when the first transistor is turned off. The on-resistance of the first switching circuit is greater than that of the first transistor, and the on-resistance of the second switching circuit is greater than that of the second transistor.

Description

Technical Field

[0001] The disclosed technology relates to a level shifter. Background Art

[0002] As a technology related to the level shifter, the following technology is known. Patent document 1 describes the following level shifter, which includes: a first voltage conversion circuit that generates a driving voltage that is lower than a first power supply voltage supplied from a first power supply line and corresponds to the first power supply voltage, and uses the driving voltage to generate a complementary signal corresponding to an input signal and output it; a second voltage conversion circuit that uses a second power supply voltage supplied from a second power supply line to generate a signal corresponding to the voltage of the complementary signal output by the first voltage conversion circuit and output it; and an output latch circuit that maintains the voltage of the signal output by the second voltage conversion circuit.

[0003] Patent document 2 describes a voltage level shifter including a first transistor to a fourth transistor of a first conductivity type. The first transistor and the second transistor are connected in series between a first power supply input and a second power supply input. The control electrode of the second transistor is connected to a first input for receiving a direct input signal. The third transistor and the fourth transistor are connected in series between the first power supply input and the second power supply input. The control electrode of the fourth transistor is connected to a second input for receiving a complementary input signal. The control electrode of the first transistor is connected to an output electrode of the third transistor and a common electrode of the fourth transistor. The control electrode of the third transistor is connected to an output electrode of the first transistor and a common electrode of the second transistor.

[0004] Patent document 3 describes a level shift circuit including a level shifter that converts a low voltage signal into a high voltage signal. The level shifter includes an input transistor to which the low voltage signal is input, and generates an output signal of the level shifter according to the on / off state of the input transistor. The level shift circuit includes a component that determines an input signal to the input transistor of the level shifter when a high voltage power supply is turned on before a low voltage power supply.

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2008-131457

[0008] [Patent Document 2] Japanese Patent Publication No. 2001-24502

[0009] [Patent Document 3] Japanese Patent Publication No. 2003-17996 Summary of the invention

[0010] [Problems to be solved by the invention]

[0011] In a level shifter including an input stage circuit to which a relatively low-level input signal is input and an output stage circuit that converts the input signal into a relatively high-level signal and outputs the signal, when the level of the power supply voltage supplied to the input stage circuit drops to the level of the threshold voltage of the transistor constituting the output stage circuit, an appropriate output signal may not be obtained.

[0012] The purpose of the disclosed technology is to obtain an appropriate output signal in a level shifter including an input stage circuit to which an input signal of a relatively low level is input and an output stage circuit that converts the input signal into a signal of a relatively high level and outputs it, even when the level of the power supply voltage supplied to the input stage circuit decreases.

[0013] [Technical means to solve the problem]

[0014] The level shifter of the disclosed technology includes: an input stage circuit to which a relatively low level input signal is input; and an output stage circuit to convert the input signal into a relatively high level signal and output the signal, wherein the input stage circuit includes: a first transistor and a second transistor to which complementary signals generated according to the input signal are input respectively; a first switch circuit whose main path is connected to the first transistor, and is turned on by the second transistor being turned on, and is turned off by the second transistor being turned off; and a second switch circuit whose main path is connected to the second transistor, and is turned on by the first transistor being turned on, and is turned off by the first transistor being turned off. The on-resistance of the first switch circuit is larger than the on-resistance of the first transistor, and the on-resistance of the second switch circuit is larger than the on-resistance of the second transistor.

[0015] [Effects of the Invention]

[0016] Through the disclosed technology, in a level shifter including an input stage circuit to which a relatively low-level input signal is input and an output stage circuit that converts the input signal into a relatively high-level signal and outputs it, an appropriate output signal can be obtained even when the level of the power supply voltage supplied to the input stage circuit drops. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a circuit diagram showing an example of the structure of a level shifter according to an embodiment of the disclosed technology.

[0018] Figure 2 : is a circuit diagram showing an example of the structure of a level shifter of a comparative example.

[0019] Figure 3 This is a circuit diagram showing an example of the structure of a level shifter according to another embodiment of the disclosed technology.

[0020] [Explanation of Symbols]

[0021] 10, 10A, 10X: Level shifter

[0022] 11, 12, 13, 14, 15, 16, 17, 18, 23, 24: Transistors

[0023] 19, 20, 21: Inverter

[0024] 30: Input stage circuit

[0025] 40, 40A, 40X: Output stage circuit

[0026] 42, 42A, 42X: First switch circuit

[0027] 43, 43A, 43X: Second switch circuit DETAILED DESCRIPTION

[0028] Hereinafter, an example of the disclosed embodiment will be described with reference to the drawings. In addition, the same reference numerals are given to the same or equivalent components and parts in each drawing, and repeated descriptions are omitted.

[0029] [First embodiment]

[0030] Figure 1 1 is a circuit diagram showing an example of the structure of the level shifter 10 according to the first embodiment of the disclosed technology. The level shifter 10 includes an input stage circuit 30 and an output stage circuit 40. A relatively low level input signal S is input to the input stage circuit 30. in The output stage circuit 40 converts the input signal S in The signal is converted into a relatively high level signal and used as the output signal S out Output.

[0031] The input stage circuit 30 includes a P-channel transistor 15, an N-channel transistor 16, an N-channel transistor 17, an N-channel transistor 18, an inverter 19, and an inverter 20. The source of the transistor 15 is connected to a power supply voltage V L The drain is connected to the power supply terminal of the inverter 19 and the inverter 20, and the gate is connected to the input reset signal S rst The reset input line 32 is connected.

[0032] The input terminal of the inverter 19 is connected to the input signal S inThe output terminal of the inverter 20 is connected to the gate of the transistor 12 of the output stage circuit 40. The inverter 19 and the inverter 20 are powered by a relatively low level power supply voltage V L drive.

[0033] The drain of transistor 16 is connected to the input terminal of inverter 20, the source is connected to ground line 34, and the gate is connected to reset input line 32. The drain of transistor 17 is connected to the drain (node ​​n1) of transistor 11 of output stage circuit 40, the source is connected to ground line 34, and the gate is connected to reset input line 32. The drain of transistor 18 is connected to the gate of transistor 12 of output stage circuit 40, the source is connected to ground line 34, and the gate is connected to reset input line 32.

[0034] The output stage circuit 40 includes a P-channel transistor 13, a P-channel transistor 14, a P-channel transistor 23, a P-channel transistor 24, an N-channel transistor 11, an N-channel transistor 12, and an inverter 21. The source of the transistor 13 is connected to a power supply voltage V H The first switch circuit 42 is connected to the power supply line 41 of the transistor 11, the drain is connected to the source of the transistor 23, and the gate is connected to the drain of the transistor 12 (node ​​n2). The drain of the transistor 23 is connected to the drain of the transistor 11 (node ​​n1), and the gate is connected to the drain of the transistor 12 (node ​​n2). The first switch circuit 42 is composed of the transistor 13 and the transistor 23 connected in cascade. The transistor 13 is an example of the "third transistor" in the disclosed technology. The transistor 23 is an example of the "fourth transistor" in the disclosed technology. The first switch circuit 42 is an example of the "first switch circuit" in the disclosed technology.

[0035] The source of transistor 14 is connected to power supply line 41, the drain is connected to the source of transistor 24, and the gate is connected to the drain of transistor 11 (node ​​n1). The drain of transistor 24 is connected to the drain of transistor 12 (node ​​n2), and the gate is connected to the drain of transistor 11 (node ​​n1). The second switch circuit 43 is composed of transistor 14 and transistor 24 connected in cascade. Transistor 14 is an example of a "fifth transistor" in the disclosed technology. Transistor 24 is an example of a "sixth transistor" in the disclosed technology. The second switch circuit 43 is an example of a "second switch circuit" in the disclosed technology.

[0036] The source of the transistor 11 is connected to the ground line 34, and the gate is connected to the output terminal of the inverter 19. The source of the transistor 12 is connected to the ground line 34, and the gate is connected to the output terminal of the inverter 20.

[0037] The power supply terminal of the inverter 21 is connected to the power supply line 41, and the input terminal is connected to the drain (node ​​n2) of the transistor 12. The inverter 21 is powered by a relatively high level power supply voltage V H The drive inverts the logic level of the signal input to the input terminal as the output signal S out To output.

[0038] The input stage circuit 30 is composed of the inverter 19 and the inverter 20 based on the input signal S input to the signal input line 33. in That is, the inverter 19 outputs the input signal S in The logic level of the signal is inverted, and the inverter 20 outputs the same signal as the input signal S in signals of the same logic level.

[0039] In the output stage circuit 40, the output signal of the inverter 19 is input to the gate of the transistor 11, and the output signal of the inverter 20 is input to the gate of the transistor 12. The transistors 11 and 12 operate complementarily according to the complementary signals input thereto. The transistor 11 is an example of a "first transistor" in the disclosed technology. The transistor 12 is an example of a "second transistor" in the disclosed technology.

[0040] The main path of the first switch circuit 42 composed of the cascaded transistors 13 and 23 is connected to the transistor 11, and the control terminal is connected to the node n2. The first switch circuit 42 is turned on when the transistor 12 is turned on, and is turned off when the transistor 12 is turned off.

[0041] The main path of the second switch circuit 43 composed of the cascaded transistors 14 and 24 is connected to the transistor 12, and the control terminal is connected to the node n1. The second switch circuit 43 is turned on when the transistor 11 is turned on, and is turned off when the transistor 11 is turned off.

[0042] The first switch circuit 42 and the second switch circuit 43 operate complementarily according to the on and off of the transistors 11 and 12 that operate complementarily. Since the first switch circuit 42 is composed of the transistors 13 and 23 connected in cascade, the on-resistance (output resistance) of the first switch circuit 42 is larger than the on-resistance of the transistor 11. Similarly, since the second switch circuit 43 is composed of the transistors 14 and 24 connected in cascade, the on-resistance of the second switch circuit 43 is larger than the on-resistance of the transistor 12. Here, the on-resistance of the transistors 11 and 12 is the on-resistance when half-on.

[0043] The operation of the level shifter 10 will be described below. First, the reset operation will be described. When the level shifter 10 is reset, a high-level reset signal S is input to the reset input line 32. rst As a result, transistors 16, 17, and 18 are turned on, regardless of the input signal S in Regardless of the logic level of , transistors 11 and 12 are both turned off. Transistor 17 is turned on, and the potential of node n1 becomes low, so transistors 14 and 24 are turned on. As a result, the potential of node n2 becomes high, so the output signal S output from the output terminal of inverter 21 is out As described above, during the reset operation of the level shifter 10, the high-level reset signal S rst , regardless of the input signal S in Regardless of the logic level, the output signal S is low. out .

[0044] Next, the input signal S of the low level is input in the level shift operation. in When the level shifter 10 performs the level shift operation, a low-level reset signal S is input to the reset input line 32. rst As a result, transistors 16, 17, and 18 are turned off. In this state, when a low-level input signal S is input to the signal input line 33, in When the inverter 19 outputs a high-level signal, the transistor 11 is turned on. In addition, the inverter 20 outputs a low-level signal, and the transistor 12 is turned off. By turning the transistor 11 on and the transistor 12 off, the potential of the node n1 converges to a low level, and the potential of the node n2 converges to a high level. As a result, the output signal S output from the output terminal of the inverter 21 is out As described above, when the level shifter 10 performs a level shift operation, when a low level input signal S in When the output signal S is low, out .

[0045] Next, the input signal S of the high level is input in the level shift operation. in When the level shifter 10 performs the level shift operation, a low-level reset signal S is input to the reset input line 32. rst , a high level input signal S is input to the signal input line 33 inAs a result, a low-level signal is output from the inverter 19, and the transistor 11 is turned off. In addition, a high-level signal is output from the inverter 20, and the transistor 12 is turned on. As the transistor 11 is turned off and the transistor 12 is turned on, the potential of the node n1 converges to a high level and the potential of the node n2 converges to a low level. As a result, the output signal S output from the output end of the inverter 21 is out As described above, when the level shifter 10 performs a level shift operation, when a high level input signal S in When the output signal S is high, out . From the relatively high level power supply voltage V H The output signal S of the inverter 21 driven by the out The level is lower than the input power supply voltage V L The input signal S of the inverter 19 driven by in The level is high.

[0046] Here, Figure 2 1 is a circuit diagram showing a structure of a level shifter 10X of a comparative example. The level shifter 10X of the comparative example is different from the level shifter 10 of the embodiment of the disclosed technology (see Figure 1 ) is that in the output stage circuit 40X, the first switch circuit 42X is composed of only the transistor 13, and the second switch circuit 43X is composed of only the transistor 14. The basic operation of the level shifter 10X of the comparative example is the same as that of the level shifter 10 of the embodiment of the disclosed technology.

[0047] In the level shifter 10X of the comparative example, consider the power supply voltage V supplied to the input stage circuit 30. L The level of the transistor 11 and the transistor 12 is reduced to the level of the threshold voltage. In this case, according to the input signal S in The transistor 11 or the transistor 12 is in a half-on state, which is not a completely on state. As a result, the potential of the node n1 or the node n2 becomes an intermediate potential, and an appropriate output signal S may not be output. out The risk.

[0048] On the other hand, in the level shifter 10 of the disclosed technical embodiment, the first switch circuit 42 is composed of the transistor 13 and the transistor 23 connected in cascade, and the second switch circuit 43 is composed of the transistor 14 and the transistor 24 connected in cascade. Thus, the on-resistance of the first switch circuit 42 can be made larger than the on-resistance of the transistor 11 when it is half-on, and the on-resistance of the second switch circuit 43 can be made larger than the on-resistance of the transistor 12 when it is half-on.

[0049] In the level shifter 10 according to the embodiment of the disclosed technology, when the power supply voltage V supplied to the input stage circuit 30 is L When the level of the transistor 11 and the transistor 12 drops to the level of the threshold voltage, as in the comparative example, according to the input signal S in The transistor 11 or the transistor 12 is in a half-on state.

[0050] For example, when the input signal S is at a low level in When the transistor 11 is in a half-on state, by making the on-resistance of the first switch circuit 42 larger than the on-resistance of the transistor 11 when it is half-on, the potential of the node n1 can be reduced to the extent that the second switch circuit 43 is in a half-on state. By making the second switch circuit 43 in a half-on state, the potential of the node n2 can be increased to the extent that the first switch circuit 42 is in a half-off state. As a result, the potential of the node n1 can be finally converged to a low level, and the potential of the node n2 can be converged to a high level, and a low-level output signal S can be output. out .

[0051] In addition, when the input signal S is high in When the transistor 12 is in a half-on state, the potential of the node n2 can be reduced to the extent that the first switch circuit 42 is in a half-on state by making the on-resistance of the second switch circuit 43 larger than the on-resistance of the transistor 12 when it is half-on. By making the first switch circuit 42 in a half-on state, the potential of the node n1 can be increased to the extent that the second switch circuit 43 is in a half-off state. As a result, the potential of the node n1 can be finally converged to a high level, and the potential of the node n2 can be converged to a low level, and a high-level output signal S can be output. out .

[0052] As described above, according to the level shifter 10 of the embodiment of the disclosed technology, even if the power supply voltage V supplied to the input stage circuit 30 is L When the level of the transistor 11 and the transistor 12 drops to the level of the threshold voltage, the same as the input signal S in The corresponding appropriate output signal S out .

[0053] In addition, by using a plurality of cascade-connected transistors as a component for increasing the on-resistance of the first switch circuit 42 and the second switch circuit 43, the substrate bias effect of the transistor 23 and the transistor 24 can be obtained. Thus, as a component for increasing the on-resistance of the first switch circuit 42 and the second switch circuit 43, the effect of increasing the on-resistance can be promoted compared to the case of using a single transistor. As a result, the size of the transistor can be reduced, so that the area and dead zone of the first switch circuit 42 and the second switch circuit 43 can be reduced.

[0054] [Second Embodiment]

[0055] Figure 3 1 is a circuit diagram showing an example of the structure of a level shifter 10A according to a second embodiment of the disclosed technology. Figure 1 ) Similarly, in the level shifter 10A of the second embodiment, the output stage circuit 40A includes a first switch circuit 42A composed of a cascade-connected transistor 13 and a transistor 23, and a second switch circuit 43A composed of a cascade-connected transistor 14 and a transistor 24. In the first switch circuit 42A, the gate of the transistor 23 is connected to the drain of the transistor 11 (node ​​n1), and the gate of the transistor 24 is connected to the drain of the transistor 12 (node ​​n2). That is, the transistor 23 and the transistor 24 are diode-connected.

[0056] Since the first switch circuit 42A is composed of the transistor 13 and the transistor 23 connected in cascade, the on-resistance of the first switch circuit 42A is larger than the on-resistance of the transistor 11 when it is half-on. Similarly, since the second switch circuit 43 is composed of the transistor 14 and the transistor 24 connected in cascade, the on-resistance of the second switch circuit 43 is larger than the on-resistance of the transistor 12 when it is half-on.

[0057] According to the level shifter 10A of the second embodiment, similarly to the level shifter 10 of the first embodiment, for example, when a low-level input signal S in When the transistor 11 is in a half-on state, by making the on-resistance of the first switch circuit 42A larger than the on-resistance of the transistor 11 when it is half-on, the potential of the node n1 can be reduced to the extent that the second switch circuit 43A is in a half-on state. By making the second switch circuit 43A in a half-on state, the potential of the node n2 can be increased to the extent that the first switch circuit 42A is in a half-off state. As a result, the potential of the node n1 can be finally converged to a low level, and the potential of the node n2 can be converged to a high level, and a low-level output signal S can be output. out As long as the potential of the node n1 can be reduced from the potential of the drain of the transistor 13 by an amount corresponding to the threshold voltage of the transistor 23 by the transistor 11 in the half-on state, the potential of the node n1 can be converged to a low level and the potential of the node n2 can be converged to a high level.

[0058] In addition, when the input signal S is high inWhen the transistor 12 is in a half-on state, by making the on-resistance of the second switch circuit 43A larger than the on-resistance of the transistor 12 when it is half-on, the potential of the node n2 can be reduced to the extent that the first switch circuit 42A is in a half-on state. By making the first switch circuit 42A in a half-on state, the potential of the node n1 can be increased to the extent that the second switch circuit 43A is in a half-off state. As a result, the potential of the node n1 can be finally converged to a high level, and the potential of the node n2 can be converged to a low level, and a high-level output signal S can be output. out As long as the potential of the node n2 can be made to be a potential obtained by dropping the potential of the drain of the transistor 14 by an amount corresponding to the threshold voltage of the transistor 24 by the transistor 12 in the half-on state, the potential of the node n1 can be converged to a high level and the potential of the node n2 can be converged to a low level.

[0059] As described above, the level shifter 10A according to the second embodiment of the disclosed technology is similar to the level shifter 10 of the first embodiment, even when the power supply voltage V supplied to the input stage circuit 30 is L When the level of the transistor 11 and the transistor 12 drops to the level of the threshold voltage, the same as the input signal S in The corresponding appropriate output signal S out .

[0060] In addition, according to the level shifter 10A of the second embodiment, if the potential of the node n1 can be made a potential obtained by dropping the potential of the drain of the transistor 13 by an amount corresponding to the threshold voltage of the transistor 23 by the transistor 11 in the half-on state, the potential of the node n1 can be made to converge to a low level and the potential of the node n2 can be made to converge to a high level, and if the potential of the node n2 can be made a potential obtained by dropping the potential of the drain of the transistor 14 by an amount corresponding to the threshold voltage of the transistor 24 by the transistor 12 in the half-on state, the potential of the node n1 can be made to converge to a high level and the potential of the node n2 can be made to converge to a low level. As a result, the sizes of the transistors constituting the first switch circuit 42A and the second switch circuit 43A can be further reduced, and the areas and dead zones of the first switch circuit 42 and the second switch circuit 43 can be further reduced.

[0061] In addition, the level shifter 10A of the second embodiment can output the signal S out The state is fixed, so it can also be used as a state-fixing circuit.

[0062] The following supplementary notes are further disclosed with respect to the above-mentioned first embodiment and second embodiment.

[0063] (Note 1)

[0064] A level shifter comprises: an input stage circuit to which a relatively low level input signal is input; and an output stage circuit to convert the input signal into a relatively high level signal and output the signal, wherein:

[0065] The output stage circuit comprises:

[0066] The first transistor and the second transistor are respectively input with complementary signals generated according to the input signal;

[0067] a first switch circuit having a main path connected to the first transistor, being turned on by the second transistor being turned on, and being turned off by the second transistor being turned off; and

[0068] A second switch circuit has a main path connected to the second transistor, is turned on when the first transistor is turned on, and is turned off when the first transistor is turned off.

[0069] The on-resistance of the first switch circuit is larger than the on-resistance of the first transistor, and the on-resistance of the second switch circuit is larger than the on-resistance of the second transistor.

[0070] (Note 2)

[0071] The level shifter according to Supplement 1, wherein:

[0072] The first switch circuit comprises a third transistor and a fourth transistor connected in cascade,

[0073] The second switch circuit includes a fifth transistor and a sixth transistor connected in cascade.

[0074] (Note 3)

[0075] The level shifter according to Supplement 2, wherein:

[0076] The gates of the third transistor and the fourth transistor are connected to the drain of the second transistor,

[0077] The gates of the fifth transistor and the sixth transistor are connected to the drain of the first transistor.

[0078] (Note 4)

[0079] The level shifter according to Supplement 2, wherein:

[0080] The gate of the third transistor is connected to the drain of the second transistor,

[0081] The gate of the fourth transistor is connected to the drain of the first transistor,

[0082] The gate of the fifth transistor is connected to the drain of the first transistor,

[0083] A gate of the sixth transistor is connected to a drain of the second transistor.

[0084] (Note 5)

[0085] A level shifter according to any one of Notes 1 to 4, wherein:

[0086] The input stage circuit includes a first inverter and a second inverter connected in cascade and driven by a relatively low level power supply voltage.

[0087] The input signal is input to the first inverter,

[0088] The output signal of the first inverter is input to the second inverter and the first transistor.

[0089] The output signal of the second inverter is input to the second transistor,

[0090] The output stage circuit includes a third inverter driven by a relatively high level power supply voltage,

[0091] A signal generated at a connection point between the second transistor and the second switch circuit is input to the third inverter.

Claims

1. A level shifter, comprising: an input stage circuit to which a relatively low level input signal is input; and an output stage circuit to convert the input signal into a relatively high level signal and output the signal, wherein: The output stage circuit comprises: The first transistor and the second transistor are respectively input with complementary signals generated according to the input signal; a first switch circuit having a main path connected to the first transistor, being turned on by the second transistor being turned on, and being turned off by the second transistor being turned off; and A second switch circuit has a main path connected to the second transistor, is turned on when the first transistor is turned on, and is turned off when the first transistor is turned off. The on-resistance of the first switch circuit is larger than the on-resistance of the first transistor, and the on-resistance of the second switch circuit is larger than the on-resistance of the second transistor.

2. The level shifter according to claim 1, wherein: The first switch circuit comprises a third transistor and a fourth transistor connected in cascade, The second switch circuit includes a fifth transistor and a sixth transistor connected in cascade.

3. The level shifter according to claim 2, wherein: The gates of the third transistor and the fourth transistor are connected to the drain of the second transistor, The gates of the fifth transistor and the sixth transistor are connected to the drain of the first transistor.

4. The level shifter according to claim 2, wherein: The gate of the third transistor is connected to the drain of the second transistor, The gate of the fourth transistor is connected to the drain of the first transistor, The gate of the fifth transistor is connected to the drain of the first transistor, A gate of the sixth transistor is connected to a drain of the second transistor.

5. The level shifter according to claim 1, wherein: The input stage circuit includes a first inverter and a second inverter connected in cascade and driven by a relatively low level power supply voltage. The input signal is input to the first inverter, The output signal of the first inverter is input to the second inverter and the first transistor. The output signal of the second inverter is input to the second transistor, The output stage circuit includes a third inverter driven by a relatively high level power supply voltage, A signal generated at a connection point between the second transistor and the second switch circuit is input to the third inverter.

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