Buffer circuit, chip and electronic device

Abstract

The invention provides a buffer circuit, a chip and electronic equipment, relates to the technical field of semiconductors, and can solve the problem that a chip in a high voltage range cannot receive an input signal in a low voltage range. The buffer circuit comprises a first PMOS tube, the grid electrode of the first PMOS tube is connected with the input end of the buffer circuit, the body electrode of the first PMOS tube is connected with a power supply, the source electrode of the first PMOS tube is connected with the power supply through a first voltage division circuit, and the voltage of the body electrode of the first PMOS tube is higher than that of the source electrode of the first PMOS tube; the grid electrode of the first NMOS tube is connected with the input end of the buffer circuit, the source electrode of the first NMOS tube is grounded, the body electrode of the first NMOS tube is connected with the power supply through the second voltage division circuit, and the voltage of the body electrode of the first NMOS tube is higher than that of the source electrode of the first NMOS tube; the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the output end of the buffer circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a buffer circuit, a chip, and an electronic device. Background Art

[0002] As semiconductor processes shrink, the gate oxide thickness becomes thinner, which reduces the core voltage to save power. In order to achieve communication between signals of different voltage levels, a mixed voltage compatible input / output (I / O) buffer is required. For example, a low voltage level signal is converted to a high voltage level signal, or a high voltage level signal is converted to a low voltage level signal.

[0003] However, the difficulty of this type of design lies in how to control the size of the input level signal that the buffer circuit can receive, such as the voltage range of the low input level VIL and the high input level VIH, to achieve compatibility with a wide range of power supply voltage requirements. Summary of the invention

[0004] The embodiments of the present application provide a buffer circuit, a chip, and an electronic device, which can solve the problem that a chip in a high voltage range cannot receive input signals in a low voltage range, so as to improve the adaptability and reliability of the chip.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] In a first aspect, a buffer circuit is provided, comprising:

[0007] a first P-type metal oxide semiconductor field effect PMOS tube, wherein the gate of the first PMOS tube is connected to the input end of the buffer circuit, the body electrode of the first PMOS tube is connected to the power supply, the source of the first PMOS tube is connected to the power supply through a first voltage divider circuit, and the body electrode voltage of the first PMOS tube is higher than the source voltage of the first PMOS tube;

[0008] a first N-type metal oxide semiconductor field effect NMOS transistor, wherein the gate of the first NMOS transistor is connected to the input end of the buffer circuit, the source of the first NMOS transistor is grounded, the body electrode of the first NMOS transistor is connected to the power supply through the second voltage divider circuit, and the body electrode voltage of the first NMOS transistor is higher than the source voltage of the first NMOS transistor;

[0009] The drain of the first PMOS tube and the drain of the first NMOS tube are connected to the output end of the buffer circuit.

[0010] In a possible design, the first voltage divider circuit includes a first resistor and a second resistor; wherein,

[0011] One end of the first resistor is connected to the source of the first PMOS tube, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the power supply.

[0012] Optionally, the buffer circuit further includes:

[0013] A second PMOS tube, a source of the second PMOS tube is connected to the other end of the first resistor and one end of the second resistor, a body electrode of the second PMOS tube is connected to a power supply, and a gate of the second PMOS tube is connected to the output end of the buffer circuit.

[0014] In a possible design, the second voltage divider circuit includes a third resistor and a fourth resistor; wherein,

[0015] One end of the third resistor is connected to the power supply, the other end of the third resistor is connected to one end of the fourth resistor and the body electrode of the first NMOS tube, and the other end of the fourth resistor is grounded.

[0016] Optionally, the buffer circuit further includes:

[0017] A first diode, wherein an anode of the first diode is connected to the other end of the third resistor and one end of the fourth resistor, and a cathode of the first diode is connected to a body electrode of the first NMOS tube.

[0018] Optionally, the buffer circuit further includes:

[0019] The second diode has a cathode connected to the body electrode of the first NMOS tube and the cathode of the first diode, and an anode of the second diode is grounded.

[0020] In one possible design, the buffer circuit further includes:

[0021] a third PMOS tube, wherein a body electrode of the third PMOS tube is connected to a power source, a source electrode of the third PMOS tube is connected to a drain electrode of the first PMOS tube, and a drain electrode of the third PMOS tube and a drain electrode of the first NMOS tube are connected to an output end of the buffer circuit through an inverter;

[0022] A second NMOS tube, a body electrode and a source electrode of the second NMOS tube are grounded, and a drain electrode of the second NMOS tube is connected to the output end of the buffer circuit through an inverter; wherein,

[0023] The gate of the third PMOS tube and the gate of the second NMOS tube are connected to the enable terminal of the buffer circuit, and the enable terminal also controls whether the buffer circuit works.

[0024] Optionally, the input end of the inverter is connected to the drain of the third PMOS tube and the drain of the second NMOS tube, and the output end of the inverter is connected to the output end of the buffer circuit.

[0025] In a second aspect, a chip is provided, comprising one or more buffer circuits as described in any implementation of the first aspect.

[0026] According to a third aspect, an electronic device is provided, comprising one or more chips as described in the second aspect.

[0027] Based on the buffer circuit, chip and electronic device provided in the embodiments of the present application, the body effect of the MOS tube can be used to adjust the threshold voltage of the MOS tube, for example, by connecting the body electrode of the first PMOS tube to the power supply, and connecting the source of the first PMOS tube to the power supply through a first voltage divider circuit, so that the body electrode voltage of the first PMOS tube is higher than the source voltage of the first PMOS tube, thereby reducing the threshold voltage of the first PMOS tube, so as to reduce the high input level voltage VIH acceptable to the buffer circuit; and by grounding the source of the first NMOS tube, and connecting the body electrode of the first NMOS tube to the power supply through a second voltage divider circuit, so that the body electrode voltage of the first NMOS tube is higher than the source voltage of the first NMOS tube, thereby reducing the threshold voltage of the first NMOS tube, so as to reduce the low input level voltage VIL acceptable to the buffer circuit. In this way, the buffer circuit can receive a level signal in a low voltage range, such as a level signal with a power supply voltage in the range of 1.2V to 1.8V, and convert it into a level signal in a high voltage range, such as a level signal with a power supply voltage in the range of 2.4V to 5V, thereby increasing the voltage range of the input level signal that can be processed by the chip containing the buffer circuit, thereby improving the adaptability and reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0029] Figure 1 It is a structural schematic diagram of a MOS tube in the prior art;

[0030] Figure 2 A schematic diagram of a buffer circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0032] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0033] The terms "first" and "second" and the like in the specification and drawings of this application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

[0034] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0035] To facilitate understanding of the technical solutions provided by the embodiments of the present application, relevant technologies and technical terms are first introduced.

[0036] 1. MOS tube

[0037] For example, Figure 1 FIG. 1 is a schematic diagram of the structure of a MOS tube in the prior art. Figure 1 As shown, the MOS tube includes a substrate (Subtrate, SUB), an isolation layer (BNL), a gate (Gate, G), a drain (Drain, D), a source (Source, S) and a body electrode (Body or Bulk, B).

[0038] 2. Body effect of MOS tube

[0039] The body effect of MOS tube meets:

[0040]

[0041] Among them, V TH is the threshold voltage of the MOS tube, V TH0 is the threshold voltage when the bias voltage between the source and body electrodes of the MOS tube is 0, γ is the body effect coefficient of the MOS tube, which ranges from 0 to 1, and ΦF is the surface potential energy, V SB It is the bias voltage between the source and body electrodes of the MOS tube.

[0042] It can be seen that the bias voltage between the source and the bulk electrode (Source-Bulk, SB) of the MOS tube (also called source-bulk bias) is positively correlated with the threshold voltage of the MOS tube. Therefore, when the SB bias voltage of the MOS tube continues to increase, the threshold voltage of the MOS tube will gradually increase; conversely, when the SB bias voltage of the MOS tube continues to decrease, the threshold voltage of the MOS tube will gradually decrease. In other words, the threshold voltage of the MOS tube can be adjusted by changing the SB bias voltage of the MOS tube.

[0043] Based on the above principles, the embodiments of the present application provide the following technical solutions, which are described in detail below:

[0044] For example, Figure 2 The schematic diagram of a buffer circuit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the buffer circuit includes:

[0045] a first P-type metal oxide semiconductor field effect PMOS transistor PM1, wherein a gate of the first PMOS transistor PM1 is connected to an input terminal PAD of the buffer circuit, a body electrode of the first PMOS transistor PM1 is connected to a power supply VDD, a source of the first PMOS transistor PM1 is connected to the power supply VDD via a first voltage divider circuit, and a body electrode voltage of the first PMOS transistor PM1 is higher than a source voltage of the first PMOS transistor PM1;

[0046] a first N-type metal oxide semiconductor field effect NMOS transistor NM1, wherein the gate of the first NMOS transistor NM1 is connected to the input terminal PAD of the buffer circuit, the source of the first NMOS transistor NM1 is grounded, the body electrode of the first NMOS transistor NM1 is connected to the power supply VDD through the second voltage divider circuit, and the body electrode voltage of the first NMOS transistor NM1 is higher than the source voltage of the first NMOS transistor NM1;

[0047] The drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1 are connected to the output terminal DOUT of the buffer circuit.

[0048] It can be seen that the first PMOS tube PM1 and the first NMOS tube NM1 form a first-stage inverter. Since the SB bias voltages of the first PMOS tube PM1 and the first NMOS tube NM1 are both negative, which is less than the SB bias voltage of 0 in the prior art, the threshold voltages of the first PMOS tube PM1 and the first NMOS tube NM1 can be reduced, so that the inverter can receive and identify input level signals in a low voltage range and convert them into level signals in a high voltage range.

[0049] Based on the buffer circuit provided in the embodiment of the present application, the body effect of the MOS tube can be used to adjust the threshold voltage of the MOS tube, for example, by connecting the body electrode B of the first PMOS tube PM1 to the power supply VDD, and connecting the source of the first PMOS tube to the power supply VDD through a first voltage divider circuit, so that the body electrode voltage of the first PMOS tube PM1 is higher than the source voltage of the first PMOS tube PM1, thereby reducing the threshold voltage of the first PMOS tube PM1, so as to reduce the high input level voltage VIH that the buffer circuit can receive; and by grounding the source of the first NMOS tube NM1, and connecting the body electrode of the first NMOS tube NM1 to the power supply through a second voltage divider circuit, so that the body electrode voltage of the first NMOS tube NM1 is higher than the source voltage of the first NMOS tube NM1, thereby reducing the threshold voltage of the first PMOS tube NM1, so as to reduce the low input level voltage VIL that the buffer circuit can receive. In this way, the buffer circuit can receive a level signal in a low voltage range, such as a level signal with a power supply voltage in the range of 1.2V to 1.8V, and convert it into a level signal in a high voltage range, such as a level signal with a power supply voltage in the range of 2.4V to 5V, thereby increasing the voltage range of the input level signal that can be processed by the chip containing the buffer circuit, thereby improving the adaptability and reliability of the chip.

[0050] In a possible design, the first voltage divider circuit includes a first resistor R1 and a second resistor R2; wherein,

[0051] One end of the first resistor R1 is connected to the source of the first PMOS transistor PM1 , the other end of the first resistor R1 is connected to one end of the second resistor R2 , and the other end of the second resistor R2 is connected to the power supply VDD.

[0052] For the existing inverter input stage, the pull-up network is implemented by a PMOS tube, and usually the body electrode and source of this PMOS are connected to the power supply voltage VDD, that is, the SB bias of the PMOS tube is 0. In the embodiment of the present application, the source voltage of the first PMOS tube PM1 is obtained by dividing the power supply voltage VDD through the first resistor R1 and the second resistor R2, which is lower than the body electrode voltage VDD of the first PMOS tube PM1, that is, the SB bias is a negative value (less than the 0 value SB bias in the existing solution), thereby reducing the threshold voltage of the first PMOS tube.

[0053] Furthermore, the current flowing through the first resistor R1, the second resistor R2 and the first PMOS tube PM1 can be changed by changing the values ​​of the first resistor R1 and the second resistor R2, thereby changing the voltage division value of the first resistor R1 and the second resistor R2, thereby changing the source voltage of the first PMOS tube PM1 and the SB bias of the first PMOS tube, and then changing the threshold voltage of the first PMOS tube.

[0054] In other words, the resistance values ​​of the first resistor R1 and the second resistor R2 can be calculated based on design requirements, such as the threshold voltage of the first PMOS tube and the voltage range of the high input level signal VIH that the buffer circuit needs to receive, as well as the body effect of the MOS tube, so as to design a buffer circuit that meets the requirements.

[0055] Alternatively, if Figure 2 As shown, the buffer circuit also includes:

[0056] The second PMOS transistor PM2 has a source connected to the other end of the first resistor R1 and one end of the second resistor R2, a body electrode connected to the power supply VDD, and a gate connected to the output end DOUT of the buffer circuit.

[0057] Based on this solution, the second PMOS tube PM2 is symmetrically connected to the first PMOS tube PM1, and the source voltage of the second PMOS tube PM2 is higher than the source voltage of the first PMOS tube PM1. In other words, the SB bias of the second PMOS tube PM2 is higher than the SB bias of the first PMOS tube PM1, the threshold voltage of the second PMOS tube PM2 is higher than the threshold voltage of the first PMOS tube PM1, and the gate of the second PMOS tube PM2 is connected to the output end DOUT of the buffer circuit, so that the second PMOS tube PM2 becomes a feedback loop between the output end DOUT of the buffer circuit and the input end PAD of the buffer circuit, and the threshold voltage of the second PMOS tube PM2 and the threshold voltage of the first PMOS tube PM1 can form a dual threshold control loop, which can avoid the situation where the signal level of the output end DOUT of the buffer circuit changes frequently due to the jitter of the signal level of the input end PAD of the buffer circuit, that is, the second PMOS tube PM2 can add hysteresis to the buffer circuit to enhance the anti-noise interference capability.

[0058] In one possible design, Figure 2 As shown, the second voltage divider circuit includes a third resistor R3 and a fourth resistor R4; wherein,

[0059] One end of the third resistor R3 is connected to the power supply VDD, the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the body electrode of the first NMOS transistor NM1, and the other end of the fourth resistor R4 is grounded.

[0060] For the existing inverter input stage, the pull-down network is implemented by an NMOS tube, and usually the body electrode and source of this NMOS are grounded, that is, the SB bias of the NMOS tube is 0. In the embodiment of the present application, the third resistor R3 and the fourth resistor R4 divide the power supply voltage DD, playing a role of following the power supply. Therefore, the body electrode voltage of the first NMOS tube NM1 is obtained by dividing the power supply voltage VDD by the third resistor R3 and the fourth resistor R4, which is higher than the source voltage (grounded) of the first NMOS tube NM1, that is, the SB bias is a negative value (less than the 0 value SB bias in the existing solution), thereby reducing the threshold voltage of the first NMOS tube NM1.

[0061] Furthermore, the current flowing through the third resistor R3, the fourth resistor R4 and the first NMOS tube NM1 can be changed by changing the resistance values ​​of the third resistor R3 and the fourth resistor R4, thereby changing the voltage division value of the third resistor R3 and the fourth resistor R4, and further changing the body electrode voltage of the first NMOS tube NM1 and the SB bias voltage of the first NMOS tube NM1, so as to change the threshold voltage of the first NMOS tube NM1.

[0062] In other words, the resistance values ​​of the third resistor R3 and the fourth resistor R4 can be calculated based on design requirements, such as the threshold voltage of the first NMOS tube NM1 and the voltage range of the low input level signal VIL that the buffer circuit needs to receive, and the body effect of the MOS tube, so as to design a buffer circuit that meets the requirements.

[0063] Alternatively, if Figure 2 As shown, the buffer circuit also includes:

[0064] The first diode D1 has an anode connected to the other end of the third resistor R3 and one end of the fourth resistor R4, and a cathode connected to the body electrode of the first NMOS transistor NM1.

[0065] The first diode D1 can apply the divided voltage of the fourth resistor R4 to the body electrode of the first NMOS transistor NM1 and prevent the PN junction between the body electrode and the source of the first NMOS transistor NM1 from being turned on, thereby improving the reliability of the buffer circuit.

[0066] Alternatively, if Figure 2 As shown, the buffer circuit also includes:

[0067] The second diode D2 has a cathode connected to the body electrode of the first NMOS transistor NM1 and the cathode of the first diode D1, and an anode of the second diode D2 is grounded.

[0068] Among them, combined Figure 1 and Figure 2It can be seen that the cathode and anode of the second diode D2 are reversely connected to the cathode and anode of the PN junction between the body electrode and the source of the first NMOS tube NM1, which can prevent the body electrode of the first NMOS tube NM1 from discharging to the outside, so as to maintain the stability of the voltage of the body electrode of the first NMOS tube NM1, and further maintain the stability of the SB bias voltage and the threshold power supply of the first NMOS tube NM1, thereby improving the reliability of the buffer circuit.

[0069] In one possible design, Figure 2 As shown, the buffer circuit also includes:

[0070] a third PMOS transistor PM3, wherein a body electrode of the third PMOS transistor PM3 is connected to a power supply VDD, a source electrode of the third PMOS transistor PM3 is connected to a drain electrode of the first PMOS transistor PM1, and a drain electrode of the third PMOS transistor PM3 and a drain electrode of the first NMOS transistor NM1 are connected to an output terminal DOUT of the buffer circuit via an inverter INV;

[0071] The second NMOS transistor NM2, the body electrode and the source electrode of the second NMOS transistor NM2 are grounded, and the drain electrode of the second NMOS transistor NM2 is connected to the output terminal DOUT of the buffer circuit through the inverter INV; wherein,

[0072] The gate of the third PMOS transistor PM3 and the gate of the second NMOS transistor NM2 are connected to the enable terminal enb of the buffer circuit, and the enable terminal enb is used to control whether the buffer circuit works.

[0073] Based on this solution, the gate of the third PMOS tube PM3 and the gate of the second NMOS tube NM2 are connected to the enable terminal enb of the buffer circuit. When the enable terminal enb is at the effective level enable, the third PMOS tube PM3 and the second NMOS tube NM2 are turned on, the buffer circuit works normally, and the input level can be converted into the output level; when the enable terminal enb is at the invalid level disable, the third PMOS tube PM3 and the second NMOS tube NM2 are turned off, and the buffer circuit does not work to save power consumption.

[0074] Optionally, an input end of the inverter INV is connected to the drain of the third PMOS transistor PM3 and the drain of the second NMOS transistor NM2 , and an output end of the inverter INV is connected to the output end DOUT of the buffer circuit.

[0075] Among them, the inverter INV can provide sufficient driving capability for the output level signal, and can be one or more, and the specific number can be determined according to the characteristics of the output level signal and the required driving capability. For example, when the level of the output terminal DOUT of the buffer circuit needs to be consistent with the level of the input terminal PAD of the buffer circuit, an odd number of inverters INV, such as 1, 3, etc., can be set. For another example, when the level of the output terminal DOUT of the buffer circuit needs to be opposite to the level of the input terminal PAD of the buffer circuit, an even number of inverters INV, such as 2, 4, etc., can be set, or the inverter INV may not be set (for example, when the driving capability of the inverter composed of the first PMOS tube and the first NMOS tube can meet the requirements).

[0076] The embodiment of the present application provides a chip, which includes one or more buffer circuits as described above, and a subsequent processing circuit of the buffer circuit. The chip can be a processor, a dedicated integrated circuit, or other integrated circuits designed for various purposes, which are not limited by the embodiment of the present application.

[0077] The embodiment of the present application provides an electronic device, which includes one or more of the above chips. The electronic device can be any electronic device equipped with the above chip, such as a mobile phone, a pad, a vehicle-mounted device, a PC, a large computer, a server, a network device, etc., and the embodiment of the present application is not limited.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A buffer circuit, characterized in that: include: a first P-type metal oxide semiconductor field effect PMOS transistor, wherein a gate of the first PMOS transistor is connected to an input end of the buffer circuit, a body electrode of the first PMOS transistor is connected to a power supply, a source of the first PMOS transistor is connected to the power supply via a first voltage divider circuit, and a body electrode voltage of the first PMOS transistor is higher than a source voltage of the first PMOS transistor; a first N-type metal oxide semiconductor field effect NMOS transistor, wherein the gate of the first NMOS transistor is connected to the input end of the buffer circuit, the source of the first NMOS transistor is grounded, the body electrode of the first NMOS transistor is connected to the power supply through a second voltage divider circuit, and the body electrode voltage of the first NMOS transistor is higher than the source voltage of the first NMOS transistor; The drain of the first PMOS tube and the drain of the first NMOS tube are connected to the output end of the buffer circuit.

2. The buffer circuit according to claim 1, characterized in that: The first voltage divider circuit includes a first resistor and a second resistor; One end of the first resistor is connected to the source of the first PMOS tube, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the power supply.

3. The buffer circuit according to claim 2, characterized in that: Also includes: A second PMOS tube, wherein the source of the second PMOS tube is connected to the other end of the first resistor and one end of the second resistor, the body electrode of the second PMOS tube is connected to the power supply, and the gate of the second PMOS tube is connected to the output end of the buffer circuit.

4. The buffer circuit according to claim 1, wherein: The second voltage divider circuit includes a third resistor and a fourth resistor; wherein, One end of the third resistor is connected to the power supply, the other end of the third resistor is connected to one end of the fourth resistor and the body electrode of the first NMOS tube, and the other end of the fourth resistor is grounded.

5. The buffer circuit according to claim 4, characterized in that: Also includes: A first diode, wherein an anode of the first diode is connected to the other end of the third resistor and one end of the fourth resistor, and a cathode of the first diode is connected to a body electrode of the first NMOS tube.

6. The buffer circuit according to claim 5, characterized in that: Also includes: A second diode, wherein a cathode of the second diode is connected to a body electrode of the first NMOS tube and the cathode of the first diode, and an anode of the second diode is grounded.

7. The buffer circuit according to any one of claims 1 to 6, characterized in that: Also includes: a third PMOS tube, wherein a body electrode of the third PMOS tube is connected to the power supply, a source electrode of the third PMOS tube is connected to a drain electrode of the first PMOS tube, and a drain electrode of the third PMOS tube and a drain electrode of the first NMOS tube are connected to an output end of the buffer circuit through an inverter; A second NMOS tube, the body electrode and the source of the second NMOS tube are grounded, and the drain of the second NMOS tube is connected to the output end of the buffer circuit through the inverter; wherein, The gate of the third PMOS tube and the gate of the second NMOS tube are connected to the enable end of the buffer circuit, and the enable end is used to control whether the buffer circuit works.

8. The buffer circuit according to claim 7, characterized in that: The input end of the inverter is connected to the drain of the third PMOS tube and the drain of the second NMOS tube, and the output end of the inverter is connected to the output end of the buffer circuit.

9. A chip, characterized in that: Comprising one or more buffer circuits as claimed in any one of claims 1-8.

10. An electronic device, characterized in that: Comprising one or more chips as claimed in claim 9.

Images