Time domain comparison circuit and analog-to-digital converter

Abstract

The application provides a time domain comparison circuit and an analog-to-digital converter, comprising: a first ring voltage-controlled oscillator, which adjusts the rising edge and falling edge delay of an oscillation signal based on the size relationship between a first input voltage and a second input voltage to obtain a first oscillation signal with a first oscillation frequency; a second ring voltage-controlled oscillator, which adjusts the rising edge and falling edge delay of an oscillation signal based on the size relationship between the first input voltage and the second input voltage to obtain a second oscillation signal with a second oscillation frequency; and a phase detector, which receives and calculates the phase difference between the first oscillation signal and the second oscillation signal to obtain the size relationship between the first input voltage and the second input voltage based on the phase difference. The application adopts a current multiplexing VCO structure and a feedback adjustment mode based on the number of oscillation periods to adjust the size of the phase detector dead time, thereby improving the performance of the time domain comparison circuit, improving the overall energy efficiency, optimizing the relationship between noise and energy consumption, and reducing the probability of metastability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a time-domain comparison circuit and an analog-to-digital converter. BACKGROUND

[0002] An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. ADCs are widely used in modern electronic devices, such as communication systems, audio and video equipment, sensor data acquisition, etc. The performance of ADC directly affects the accuracy and speed of the entire system, and is a key component in the signal processing chain. Among them, the successive approximation register analog-to-digital converter (SAR ADC) is a common ADC architecture, which is widely used due to its high energy efficiency and moderate conversion speed. The working principle of SAR ADC is to determine the digital representation of the input signal bit by bit in a series of comparison operations through the method of successive approximation.

[0003] The comparator plays a key role in the SAR ADC, and its performance directly determines the speed and accuracy of the entire converter. For the design of SAR ADC, the comparator plays a decisive role in the overall performance and area. With the update iteration of semiconductor technology, the process size is also constantly reduced to improve chip integration, while the voltage and intrinsic gain of the transistor are also reduced. The advantage is that the updated semiconductor technology will provide faster transistor operating frequency and higher time domain resolution. Therefore, the design of the time-domain comparator in the SAR ADC system has obvious advantages in energy efficiency and process iteration.

[0004] However, the existing time-domain comparators generally have small voltage-to-time gain, cannot be effectively reset, and have high metastable probability, etc. How to solve the above problems has become one of the technical problems that technicians in the field need to solve.

[0005] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a time-domain comparison circuit and an analog-to-digital converter, which solves the problems of small voltage-to-time gain, ineffective reset, high metastable probability, etc. of the time-domain comparator in the prior art.

[0007] To achieve the above object and other related objects, the present application provides a time-domain comparison circuit, which at least comprises:

[0008] a first ring voltage-controlled oscillator, a second ring voltage-controlled oscillator, and a phase discriminator;

[0009] The first ring voltage-controlled oscillator adjusts rising edge and falling edge delays of an oscillation signal based on a size relationship between a first input voltage and a second input voltage to obtain a first oscillation signal having a first oscillation frequency; and the second ring voltage-controlled oscillator adjusts rising edge and falling edge delays of an oscillation signal based on the size relationship between the first input voltage and the second input voltage to obtain a second oscillation signal having a second oscillation frequency.

[0010] The phase discriminator receives and calculates a phase difference between the first oscillation signal and the second oscillation signal to obtain the size relationship between the first input voltage and the second input voltage based on the phase difference.

[0011] Optionally, the first ring voltage-controlled oscillator and the second ring voltage-controlled oscillator each comprise N-stage delay modules and M-stage inverting modules sequentially cascaded to form a loop, N is a natural number greater than or equal to 1, and M is an odd number; the delay module comprises two-stage delay units cascaded, each delay unit comprising a first inverting unit, a first PMOS tube, and a first NMOS tube, the first PMOS tube being connected in series between a power supply voltage and a power supply end of the first inverting unit, and the first NMOS tube being connected in series between a ground and a ground end of the first inverting unit.

[0012] The first inverting unit is connected in series on the loop; the gate of each first PMOS tube in the delay module of the first ring voltage-controlled oscillator receives the first input voltage, and the gate of each first NMOS tube receives the second input voltage; the gate of each first PMOS tube in the delay module of the second ring voltage-controlled oscillator receives the second input voltage, and the gate of each first NMOS tube receives the first input voltage.

[0013] More optionally, each delay module further comprises a first reset tube and a second reset tube; the first reset tube is connected to the output end of the first-stage delay unit and is controlled by an enable signal to reset the output node of the first-stage delay unit; and the second reset tube is connected to the output end of the second-stage delay unit and is controlled by the enable signal to reset the output node of the second-stage delay unit.

[0014] More optionally, one stage of the M-stage inverting module is an NAND gate; the first input end of the NAND gate is connected in the loop, the second input end receives an enable signal, and the output end is connected to the input end of the first-stage delay unit.

[0015] More optionally, the output terminals of the first ring voltage-controlled oscillator and the second ring voltage-controlled oscillator are arranged on any one node between the output terminal of the last-stage delay module in the loop and the first input terminal of the NAND gate.

[0016] More optionally, the time-domain comparison circuit further comprises a dead time adjustment module, which receives an output signal of the phase detector, and adjusts a dead time of the phase detector based on the number of oscillations before the output signal of the phase detector flips, wherein the dead time of the phase detector is negatively related to the number of oscillations.

[0017] More optionally, the dead time adjustment module comprises a first adjustment unit and a second adjustment unit; each adjustment unit comprises a second inverter, a second PMOS transistor and a second NMOS transistor, the second PMOS transistor is connected in series between a power supply voltage and a power supply terminal of the second inverter, and the second NMOS transistor is connected in series between a ground and a ground terminal of the second inverter.

[0018] The gate of the second PMOS transistor and the second NMOS transistor in the first adjustment unit is connected to a first output signal of the phase detector, and the second inverter is controlled by an enable signal and outputs a first adjustment signal; the gate of the second PMOS transistor and the second NMOS transistor in the second adjustment unit is connected to a second output signal of the phase detector, and the second inverter is controlled by the enable signal and outputs a second adjustment signal; the first output signal and the second output signal of the phase detector are differential signals.

[0019] More optionally, the first adjustment signal and the second adjustment signal are used to adjust the capacitance of a load capacitor in the phase detector.

[0020] More optionally, the time-domain comparison circuit further comprises a latch module, which is connected to the output terminals of the first ring voltage-controlled oscillator and the second ring voltage-controlled oscillator, and is used to align the rising edges or falling edges of the first oscillation signal and the second oscillation signal to avoid false triggering of the phase detector.

[0021] More optionally, the latch module comprises a first latch and a second latch, the first input terminal of the first latch receives the first oscillation signal, and the second input terminal receives the second oscillation signal; the first input terminal of the second latch receives the second oscillation signal, and the second input terminal receives the first oscillation signal; the first latch and the second latch each comprise a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a third inverter and a fourth inverter; wherein the size of the third inverter is greater than the size of the fourth inverter.

[0022] The source of the third PMOS tube is connected with a power supply voltage, the drain is connected with the source of the fourth PMOS tube, and the gate is used as a second input end of the corresponding latch;

[0023] The drain of the fourth PMOS tube and the third NMOS tube are connected together, and the gates are connected together as a first input end of the corresponding latch; and the source of the third NMOS tube is grounded.

[0024] The third inverting unit and the fourth inverting unit are cross-coupled, the input end of the third inverting unit is connected with the drains of the fourth PMOS tube and the third NMOS tube, and the output end of the fourth inverting unit is used as an output end of the corresponding latch.

[0025] Optionally, the time domain comparison circuit further comprises a logic module, which receives an output signal of the phase detector, and controls the first ring voltage-controlled oscillator and the second ring voltage-controlled oscillator to stop working and reset when the phase detector outputs a comparison result.

[0026] To achieve the above object and other related objects, the application further provides an analog-to-digital converter, which comprises at least a digital-to-analog conversion unit, a successive approximation logic unit and the above time domain comparison circuit.

[0027] The digital-to-analog conversion unit receives an input signal and adjusts an output voltage based on a control signal output by the successive approximation logic unit;

[0028] The time domain comparison circuit is connected to the output end of the digital-to-analog conversion unit, compares the output voltage of the digital-to-analog conversion unit with a reference voltage, and outputs a comparison result;

[0029] The successive approximation logic unit is connected to the output end of the time domain comparison circuit and generates a control signal based on the comparison result.

[0030] As described above, the time domain comparison circuit and the analog-to-digital converter of the application have the following beneficial effects:

[0031] 1. In the time domain comparison circuit and the analog-to-digital converter of the application, NMOS and PMOS are used as input tubes in each stage of delay unit, so as to fully utilize the current of each branch, greatly improve the voltage-to-time gain through current multiplexing, and further improve the overall energy efficiency and optimize the relationship between noise and energy consumption.

[0032] 2. In the time domain comparison circuit and the analog-to-digital converter of the application, a reset tube is arranged in each stage of delay unit, so as to normally and quickly reset the internal node in the ring voltage-controlled oscillator, and avoid the unpredictable performance decline caused by the failure of effective reset.

[0033] 3. The dead time of the phase detector in the time domain comparison circuit and the analog-digital converter of the application is adjustable, and the dead time of the phase detector is adjusted based on the oscillation times of the output signal of the phase detector, so as to improve the probability of the latching result of the phase detector under small signal amplitude and reduce the probability of metastability.

[0034] 4. The time domain comparison circuit and the analog-digital converter of the application stop oscillation and reset once the comparison result is obtained, otherwise, the oscillation continues until the phase difference accumulates more than the dead time of the phase detector, so as to effectively optimize the noise performance. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A structural schematic diagram of a comparator is shown.

[0036] Figure 2 A structural schematic diagram of the time domain comparison circuit of the application is shown.

[0037] Figure 3 A structural schematic diagram of the delay module in the first ring voltage-controlled oscillator of the application is shown.

[0038] Figure 4 A structural schematic diagram of the delay module in the second ring voltage-controlled oscillator of the application is shown.

[0039] Figure 5 A structural schematic diagram of the phase detector of the application is shown.

[0040] Figure 6 A structural schematic diagram of the dead time adjustment module of the application is shown.

[0041] Figure 7 A principle schematic diagram of the adjustment of the dead time of the phase detector of the application is shown.

[0042] Figure 8 Another structural schematic diagram of the delay module of the application is shown.

[0043] Figure 9 A structural schematic diagram of the logic module of the application is shown.

[0044] Figure 10 A principle schematic diagram of the control of the first and second ring voltage-controlled oscillators to reset based on the output signal of the phase detector of the application is shown.

[0045] Figure 11 Another structural schematic diagram of the time domain comparison circuit of the application is shown.

[0046] Figure 12 A structural schematic diagram of the latch of the application is shown.

[0047] Figure 13Fig. 1 shows a schematic diagram of the working principle of the latch module of the present application.

[0048] Figure 14 Fig. 2 shows a schematic diagram of the structure of the analog-to-digital converter of the present application.

[0049] Element number explanation

[0050] 1 comparator

[0051] 11 oscillator

[0052] 12 phase detector

[0053] 2 time domain comparison circuit

[0054] 2a first ring voltage-controlled oscillator

[0055] 2b second ring voltage-controlled oscillator

[0056] 21 delay module

[0057] 211 delay unit

[0058] 212 first reset tube

[0059] 213 second reset tube

[0060] 22 NAND gate

[0061] 23 inverter

[0062] 24 inverter

[0063] 25 inverter

[0064] 2c phase detector

[0065] 2d dead time adjustment module

[0066] 26a first adjustment unit

[0067] 26b second adjustment unit

[0068] 2e logic module

[0069] 2f latch module

[0070] 27 first / second latch

[0071] 3 digital-to-analog conversion unit

[0072] 4 successive approximation logic unit DETAILED DESCRIPTION

[0073] Following, the advantages and effects of the present application will be described in detail by specific examples. The present application can be implemented or applied in other different embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0074] Please refer to Figures 1-14 . It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concept of the present application, and the drawings only show the components related to the present application, not the components number, shape and size when actually implemented. The actual implementation of each component type, number and proportion can be arbitrarily changed, and the component layout type can be more complex.

[0075] Figure 1 It is a comparator 1, comprising two closed loop voltage controlled oscillators 11 and a phase detector 12. Each oscillator 11 is formed by seven subunits with inverting function cascaded in turn to form a loop, wherein the first stage subunit is an NAND gate and the remaining stage subunits are inverters. The first stage subunit controls the operation of the entire loop by the intervention of the enable signal En, and the ground end of the odd stage subunit is grounded through an NMOS tube. The gate of each NMOS tube in one oscillator 11 receives a positive phase input signal Vip, and the oscillation frequency of the output signal is controlled based on the positive phase input signal Vip. The gate of each NMOS tube in the other oscillator 11 receives an inverted input signal Vin, and the oscillation frequency of the output signal is controlled based on the inverted input signal Vin. The phase detector 12 receives the output signals of the two oscillators 11 and detects the phase difference between the two to obtain the phase difference. Based on the leading or lagging relationship between the phases of the two output signals, the size relationship between the positive phase input signal Vip and the inverted input signal Vin is determined. The comparator 1 can optimize the relationship between power consumption, noise and speed; in the design of successive approximation type analog-to-digital converter, the comparator 1 and its inherent oscillation period number information can be used to estimate the amplitude of the input voltage while obtaining a single-bit comparison result, thereby skipping the subsequent unnecessary flipping and quantization, saving a lot of power consumption. However, the internal even stage subunit of the oscillator 11 cannot provide voltage signal to time difference gain, so the current of this branch (even stage) is wasted; the comparator 1 also cannot reach a certain stable state within a specified time, and the metastable state probability is high.

[0076] In order to solve the above problems, the present application provides a time domain comparison circuit 2, as shown in Figure 2 , the time domain comparison circuit 2 comprises:

[0077] The first ring voltage controlled oscillator 2a, the second ring voltage controlled oscillator 2b and the phase detector 2c.

[0078] As shown in Figure 2 , the first ring voltage-controlled oscillator 2a adjusts the rising edge and falling edge delay of the oscillation signal based on the size relationship between the first input voltage Vip and the second input voltage Vin to obtain a first oscillation signal X with a first oscillation frequency.

[0079] Specifically, the first ring voltage-controlled oscillator 2a includes N-stage delay modules 21 and M-stage inverting modules cascaded in sequence to form a loop, N is a natural number greater than or equal to 1, and M is an odd number. As an example, N is set to 5 and M is set to 3; in actual use, the values of N and M are set as needed, and the number of inverting stages in the loop is odd and can achieve oscillation, which will not be described one by one here.

[0080] More specifically, as shown in Figure 3 , each delay module 21 includes two-stage delay units 211 cascaded, and each delay unit 211 includes a first inverting unit not1, a first PMOS transistor MP1, and a first NMOS transistor MN1. The first inverting unit not1 is connected in series in the loop, the first PMOS transistor MP1 is connected in series between the power supply voltage VDD and the power supply end of the first inverting unit not1, and the first NMOS transistor MN1 is connected in series between the ground VSS and the ground end of the first inverting unit not1; wherein the gate of each first PMOS transistor MP1 is connected to the first input voltage Vip, and the current flowing into the delay unit 211 is adjusted based on the control of the first input voltage Vip, so as to realize the delay control of the rising edge of the oscillation signal X output by the first ring voltage-controlled oscillator 2a; the gate of each first NMOS transistor MN1 is connected to the second input voltage Vin, and the current flowing out of the delay unit 211 is adjusted based on the control of the second input voltage Vin, so as to realize the delay control of the falling edge of the oscillation signal X output by the first ring voltage-controlled oscillator 2a. The first ring voltage-controlled oscillator 2a of the present application makes full use of the current of each branch, sets a delay in each delay unit 211, and has a delay in both the rising edge and the falling edge of the oscillation signal. Through the superposition of each stage of delay, the voltage-to-time (phase difference) gain can be further increased, the voltage-to-time gain of the ring voltage-controlled oscillator under the same power consumption is improved, and the overall energy efficiency of the time domain comparison circuit 2 is improved.

[0081] More specifically, the M-stage inverting module is connected in series in the loop, and each stage of the inverting module can be set to any device with inverting function, including but not limited to inverters, NAND gates, or NOR gates; as shown in Figure 2As shown, in the embodiment, the first stage of the three-stage inverting module is a NAND gate 22, and the other two stages are inverters 23 and 24. The first input and output of the NAND gate 22 are connected in a loop, and the second input receives an enable signal En; that is, when the enable signal En is valid (high level), the NAND gate is equivalent to an inverter, and the first ring voltage-controlled oscillator 2a starts to work; when the enable signal En is invalid (low level), the output of the NAND gate is locked at high level, and the first ring voltage-controlled oscillator 2a is reset. When the valid level of the enable signal En is set to low level, the NAND gate can also be replaced by a NOR gate (or other devices), which is not described here. In order to maximize the use of each delay module 21, the NAND gate 22 is arranged at the input of the first-stage delay module 21, and the output of the first ring voltage-controlled oscillator 2a is arranged at any node (including the output node of the last-stage delay module 21 and the first input node of the NAND gate 22) between the output of the last-stage delay module 21 and the first input of the NAND gate 22. As shown in the figure, the output of the last-stage delay module 21 is connected to the first input of the NAND gate 22, and the output of the first ring voltage-controlled oscillator 2a is connected to the first input of the NAND gate 22. Figure 2 As shown, in the embodiment, each delay module 21 is cascaded in turn at the output of the NAND gate 22, the remaining inverting modules (inverters 23 and 24) are connected in series at the output of the last-stage delay module 21, the output of the last-stage inverting module (inverter 24) is connected to the input of the NAND gate 22, and the oscillation signal X output by the first ring voltage-controlled oscillator 2a is led out from the output of the inverter 23 through the inverter 25.

[0082] Further, in order to avoid the situation that the NAND gate 22 cannot be effectively reset in a special scenario, the delay module 21 of the present application further comprises a first reset tube 212 and a second reset tube 213; the first reset tube 212 is connected to the output of the first-stage delay unit and is controlled by the enable signal, for resetting the output node of the first-stage delay unit; the second reset tube 213 is connected to the output of the second-stage delay unit and is controlled by the enable signal, for resetting the output node of the second-stage delay unit. As shown in the figure, the first reset tube 212 is connected to the output of the first-stage delay unit, and the second reset tube 213 is connected to the output of the second-stage delay unit. Figure 3As shown, in the embodiment, the first reset tube 212 is implemented by an NMOS tube, the drain is connected to the output end of the first-stage delay unit, the source is grounded to VSS, and the gate is connected to the inverse signal Enb of the enable signal; when the enable signal En is invalid (low level), the first reset tube 212 is turned on, and the output end of the first-stage delay unit is reset to low level. The second reset tube 213 is implemented by a PMOS tube, the drain is connected to the output end of the second-stage delay unit, the source is connected to the power supply voltage VDD, and the gate is connected to the enable signal En; when the enable signal En is invalid (low level), the second reset tube 213 is turned on, and the output end of the second-stage delay unit is reset to high level. In this way, the effective reset of the first ring voltage-controlled oscillator 2a is ensured. In actual use, the output node of the first-stage delay unit can also be reset to high level, and the output node of the second-stage delay unit can also be reset to low level according to actual needs; in addition, the type, connection relationship and corresponding control signal of the reset tube can be set according to actual needs, as long as the reset function can be realized, and the embodiment is not limited.

[0083] As shown, Figure 2 The second ring voltage-controlled oscillator 2b adjusts the rising edge and falling edge delay of the oscillation signal based on the size relationship between the first input voltage Vip and the second input voltage Vin, so as to obtain a second oscillation signal Y with a second oscillation frequency.

[0084] Specifically, the structure of the second ring voltage-controlled oscillator 2b is the same as that of the first ring voltage-controlled oscillator 2a, and the difference lies in that the gate of the first PMOS tube MP1 in each delay unit 211 of the second ring voltage-controlled oscillator 2b is connected to the second input voltage Vin, the current flowing into the delay unit 211 is adjusted based on the control of the second input voltage Vin, so as to realize the delay control of the rising edge of the oscillation signal Y output by the second ring voltage-controlled oscillator 2b; the gate of each first NMOS tube MN1 is connected to the first input voltage Vip, the current flowing out of the delay unit 211 is adjusted based on the control of the first input voltage Vip, so as to realize the delay control of the falling edge of the oscillation signal Y output by the second ring voltage-controlled oscillator 2b; as shown. Figure 4

[0085] In the reset phase, the enable signal En is invalid (low level), and the first oscillation signal X and the second oscillation signal Y are both high level signals. In the comparison phase, the enable signal En is valid (high level), and the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b start oscillating at different frequencies according to the input voltage.

[0086] ​When the first input voltage Vip is greater than the second input voltage Vin, in the first ring voltage-controlled oscillator 2a, the current flowing through each first PMOS transistor MP1 in the delay unit 211 decreases due to the control of the first input voltage Vip, thus the rising speed of the rising edge of the first oscillation signal X is slow; similarly, the current flowing through each first NMOS transistor MN1 in the delay unit 211 also decreases due to the control of the second input voltage Vin, thus the falling speed of the falling edge of the first oscillation signal X is also very slow; after the continuous superposition of each delay unit, the delay of the first oscillation signal X is larger and larger, and has the first oscillation frequency. In the second ring voltage-controlled oscillator 2b, the current flowing through each first PMOS transistor MP1 in the delay unit 211 increases due to the control of the second input voltage Vin, thus the rising speed of the rising edge of the second oscillation signal Y is fast; similarly, the current flowing through each first NMOS transistor MN1 in the delay unit 211 also increases due to the control of the first input voltage Vip, thus the falling speed of the falling edge of the second oscillation signal Y is also fast; even after the continuous superposition of each delay unit, the delay of the second oscillation signal Y is very small, and has the second oscillation frequency. Thus, it can be seen that the delay of the first oscillation signal X is greater than the delay of the second oscillation signal Y, the first oscillation frequency is less than the second oscillation frequency, and the first oscillation signal X lags behind the second oscillation signal Y.

[0087] When the first input voltage Vip is less than the second input voltage Vin, in the first ring voltage-controlled oscillator 2a, the current flowing through each first PMOS transistor MP1 in the delay unit 211 increases due to the control of the first input voltage Vip, thus the rising speed of the rising edge of the first oscillation signal X is fast; similarly, the current flowing through each first NMOS transistor MN1 in the delay unit 211 also increases due to the control of the second input voltage Vin, thus the falling speed of the falling edge of the first oscillation signal X is also fast; even after the continuous superposition of each delay unit, the delay of the first oscillation signal X is very small, and has the first oscillation frequency. In the second ring voltage-controlled oscillator 2b, the current flowing through each first PMOS transistor MP1 in the delay unit 211 decreases due to the control of the second input voltage Vin, thus the rising speed of the rising edge of the second oscillation signal Y is slow; similarly, the current flowing through each first NMOS transistor MN1 in the delay unit 211 also decreases due to the control of the first input voltage Vip, thus the falling speed of the falling edge of the second oscillation signal Y is also very slow; after the continuous superposition of each delay unit, the delay of the second oscillation signal Y is larger and larger, and has the second oscillation frequency. Thus, it can be seen that the delay of the first oscillation signal X is less than the delay of the second oscillation signal Y, the first oscillation frequency is greater than the second oscillation frequency, and the first oscillation signal X leads the second oscillation signal Y.

[0088] It should be noted that the greater the difference between the first input voltage Vip and the second input voltage Vin (the greater the input voltage amplitude), the greater the phase difference between the first oscillation signal X and the second oscillation signal Y; the corresponding relationship between the first input voltage Vip and the second input voltage Vin in the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b can also be interchanged, which is not limited to the embodiment.

[0089] As shown in Figure 2 , the phase detector 2c receives and calculates the phase difference between the first oscillation signal X and the second oscillation signal Y to obtain the size relationship between the first input voltage Vip and the second input voltage Vin based on the phase difference.

[0090] Specifically, any circuit structure capable of detecting and reflecting the phase relationship between the first oscillation signal X and the second oscillation signal Y is applicable to the present application. As shown in Figure 5 , as an example, the phase detector 2c includes 6 NAND gates, wherein the first NAND gate U1, the second NAND gate U2, the third NAND gate U3, and the sixth NAND gate U6 are two-input NAND gates, and the fourth NAND gate U4 and the fifth NAND gate U5 are three-input NAND gates. The first input terminal of the first NAND gate U1 receives the first oscillation signal X, and the second input terminal is connected to the first output terminal Dop of the phase detector 2c. The first input terminal of the second NAND gate U2 receives the second oscillation signal Y, and the second input terminal is connected to the second output terminal Don of the phase detector 2c. The first input terminal of the third NAND gate U3 is connected to the output terminal of the second NAND gate U2, and the second input terminal is connected to the first output terminal Dop of the phase detector 2c. The first input terminal of the fourth NAND gate U4 is connected to the output terminal of the third NAND gate U3, the second input terminal is connected to the output terminal of the first NAND gate U1, the third input terminal is connected to the enable signal En, and the output terminal serves as the first output terminal Dop of the phase detector 2c. The first input terminal of the fifth NAND gate U5 is connected to the output terminal of the sixth NAND gate U6, the second input terminal is connected to the output terminal of the second NAND gate U2, the third input terminal is connected to the enable signal En, and the output terminal serves as the second output terminal Don of the phase detector 2c. The first input terminal of the sixth NAND gate U6 is connected to the output terminal of the first NAND gate U1, and the second input terminal is connected to the second output terminal Don of the phase detector 2c.

[0091] When the enable signal En jumps to low level, the output terminals of the fourth NAND gate U4 and the fifth NAND gate U5 are reset to high level, and after the reset, the enable signal En jumps to high level, and the phase detector 2c enters the working state. When the phase difference between the first oscillation signal X and the second oscillation signal Y is less than the dead zone of the phase detector 2c, the output signal of the phase detector 2c oscillates (as an example, it drops from high level to a certain potential and then quickly restores to high level, and so on, and the potential of the drop is lower and lower) but does not flip, and the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b continuously circulate and accumulate the phase difference. When the phase difference between the first oscillation signal X and the second oscillation signal Y is greater than the dead zone of the phase detector 2c, the output signal of the phase detector 2c flips; in this example, in the initial state, the first oscillation signal X and the second oscillation signal Y are both high level. If the first input voltage Vip is greater than the second input voltage Vin, the second oscillation signal Y is ahead of the first oscillation signal X, that is, the second oscillation signal Y jumps to low level first, at this time, the output signal of the second NAND gate U2 jumps to high level, and the enable signal En and the output signal of the sixth NAND gate U6 remain high level of the previous state, therefore, the second output signal Don output by the fifth NAND gate U5 jumps to low level, and the first output signal Dop output by the fourth NAND gate U4 remains high level, and the comparison result is obtained. If the first input voltage Vip is less than the second input voltage Vin, the first oscillation signal X is ahead of the second oscillation signal Y, that is, the first oscillation signal X jumps to low level first, at this time, the output signal of the first NAND gate U1 jumps to high level, and the enable signal En and the output signal of the third NAND gate U3 remain high level of the previous state, therefore, the first output signal Dop output by the fourth NAND gate U4 jumps to low level, and the second output signal Don output by the fifth NAND gate U5 remains high level, and the comparison result is obtained.

[0092] It should be noted that the structure of the phase detector 2c is not limited, and phase detection can also be realized based on the rising edges of the first oscillation signal X and the second oscillation signal Y as needed, which will not be described one by one here.

[0093] As another implementation manner of the present application, the time domain comparison circuit 2 of the present application further comprises a dead zone time adjustment module 2d for reducing the probability of encountering metastable state of the time domain comparison circuit 2 of the present application. The dead zone time adjustment module 2d receives the output signal of the phase detector 2c, and adjusts the dead zone time of the phase detector based on the number of oscillations before the flip of the output signal of the phase detector 2c, so that the dead zone time of the phase detector is negatively related to the number of oscillations (that is, the dead zone time of the phase detector decreases linearly or nonlinearly with the increase of the number of oscillations, and vice versa). For example, Figure 6As shown, the dead time adjustment module 2d includes, as an example, a first adjustment unit 26a and a second adjustment unit 26b; each adjustment unit includes a second inverter unit not2, a second PMOS transistor MP2 and a second NMOS transistor MN2; the second PMOS transistor MP2 is connected in series between the power supply voltage VDD and the power supply terminal of the second inverter unit not2, and the second NMOS transistor MN2 is connected in series between the ground VSS and the ground terminal of the second inverter unit not2. The gate of the second PMOS transistor MP2 and the second NMOS transistor MN2 in the first adjustment unit 26a are connected to the first output signal Dop of the phase detector 2c, and the second inverter unit not2 is controlled by an enable signal (in this example, the inverse signal Enb of the received enable signal) and outputs a first adjustment signal VGn. When the first input voltage Vip is less than the second input voltage Vin, the first adjustment unit 26a works; at this time, the second NMOS transistor MN2 in the first adjustment unit 26a is turned off, and the second PMOS transistor MP2 is turned on. In each oscillation of the first output signal Dop, the voltage of the first adjustment signal VGn is charged up (equivalent to integrating the output voltage of the phase detector) one by one, and the more the oscillation times, the greater the voltage value of the first adjustment signal VGn. The gate of the second PMOS transistor MP2 and the second NMOS transistor MN2 in the second adjustment unit 26b are connected to the second output signal Don of the phase detector 2c, and the second inverter unit not2 is controlled by an enable signal (in this example, the inverse signal Enb of the received enable signal) and outputs a second adjustment signal VGp. When the first input voltage Vip is greater than the second input voltage Vin, the second adjustment unit 26b works; at this time, the second NMOS transistor MN2 in the second adjustment unit 26b is turned off, and the second PMOS transistor MP2 is turned on. In each oscillation of the second output signal Don, the voltage of the second adjustment signal VGp is charged up one by one, and the more the oscillation times, the greater the voltage value of the second adjustment signal VGp, as shown in the figure. Figure 7 The first adjustment signal VGn and the second adjustment signal VGp are fed back to the phase detector 2c for adjusting the dead time of the phase detector 2c, and the greater the first adjustment signal VGn or the second adjustment signal VGp, the smaller the dead time of the phase detector 2c is adjusted.

[0094] Further, as an example, the first adjustment signal VGn and the second adjustment signal VGp are used to adjust the capacitance value of the load capacitor in the phase detector 2c. As shown in the figure, Figure 5As shown, the output nodes of the first and second NAND gates U1 and U2 are respectively provided with first capacitors C1, the output nodes of the third and sixth NAND gates U3 and U6 are respectively provided with second capacitors C2, and the output nodes of the fourth and fifth NAND gates U4 and U5 are respectively provided with third capacitors C3; each capacitor is configured as a variable capacitor, and the capacitance of at least one of the second and third capacitors C2 and C3 can be adjusted based on the first and second adjustment signals VGn and VGp, so as to adjust the dead time. As an implementation manner, the third capacitors C3 are implemented based on MOS tubes; the gate of the MOS tube is used as the upper plate of the third capacitor C3, and the source and the drain are connected together as the lower plate; wherein the upper plate of one third capacitor C3 is connected to the output node of the fourth NAND gate U4, and the lower plate is connected to the second adjustment signal VGp; the upper plate of another third capacitor C3 is connected to the output node of the fifth NAND gate U5, and the lower plate is connected to the first adjustment signal VGn; the first and second adjustment signals VGn and VGp adjust the voltage of the lower plate of the corresponding third capacitor C3, which is equivalent to adjusting the capacitance, and further adjusts the dead time of the phase detector 2c.

[0095] As another example, a pull-down tube is arranged at the output end of the fourth and fifth NAND gates U4 and U5, and the corresponding pull-down tube is controlled based on the first and second adjustment signals VGn and VGp, so as to accelerate the jump of the corresponding output signal of the phase detector 2c to low level, and further reduce the dead time.

[0096] As yet another example, the size of the fourth and fifth NAND gates U4 and U5 is changed based on the first and second adjustment signals VGn and VGp, so as to adjust the dead time.

[0097] As still another example, the gain of the first and second ring voltage-controlled oscillators 2a and 2b is changed based on the first and second adjustment signals VGn and VGp, and further adjusts the dead time (the greater the gain, the smaller the dead time). Further, as an implementation manner: the equivalent size of the input tube (PMOS tube MP1, NMOS tube MN1) of the first and second ring voltage-controlled oscillators is adjusted based on the first and second adjustment signals VGn and VGp. As another implementation manner, as shown in FIG. 2B, the first and second ring voltage-controlled oscillators 2a and 2b are respectively provided with a first and a second input tube (PMOS tube MP1, NMOS tube MN1), and the first and second adjustment signals VGn and VGp are respectively connected to the first and second input tubes. Figure 8As shown, the drain of NMOS MN1 in each delay unit 211 is connected to a first gain adjustment transistor 214 and a second gain adjustment transistor 215 (pull-down transistor) respectively, wherein the first gain adjustment transistor 214 is controlled by a second adjustment signal VGp, and the second gain adjustment transistor 215 is controlled by a first adjustment signal VGn. Based on the first adjustment signal VGn and the second adjustment signal VGp, the corresponding gain adjustment transistor is controlled to accelerate the pull-down of the drain of the corresponding NMOS MN1 (equivalent to increasing the value of Vip), so as to change the gain of the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b. In this example, the first gain adjustment transistor 214 and the second gain adjustment transistor 215 are implemented by NMOS transistors.

[0098] It should be noted that the manner in which the first adjustment signal VGn and the second adjustment signal VGp adjust the dead time of the phase detector 2c is not limited, and will not be described here.

[0099] As an implementation manner of the present application, the time domain comparison circuit 2 of the present application further comprises a logic module 2e, which receives the output signals (Dop and Don) of the phase detector 2c, and controls the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b to stop working and reset when the phase detector 2c outputs the comparison result. As shown in the figure, Figure 8 As an example, the logic module 2e comprises a first AND gate U7 and a second AND gate U8, the input terminals of the first AND gate U7 receive the first output signal Dop and the second output signal Don of the phase detector 2c respectively, and the output terminal is connected to one input terminal of the second AND gate U8; the other input terminal of the second AND gate U8 receives an externally provided enable signal En. As shown in the figure, Figure 9As shown, when the phase detector 2c does not output the comparison result, both Dop and Don are high, the first AND gate U7 outputs high, and if the enable signal En is valid (high), the second AND gate U8 outputs the high oscillator enable signal En_VCO, and the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b work normally. When the phase detector 2c outputs the comparison result, one of Dop and Don is high, and the other is low (in this example, Dop remains high, and Don jumps to low), the first AND gate U7 outputs low, and no matter whether the enable signal En is valid, the second AND gate U8 outputs the low enable signal En_VCO, and the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b are reset. It should be noted that at this time, the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b are no longer controlled by the external enable signal En, but are controlled by the oscillator enable signal En_VCO. Any logic circuit capable of achieving the above functions is applicable to the present application, and will not be described here. In this case, the noise performance of the present application is automatically optimized; the self-scaling characteristics of the comparator noise are very beneficial to systems such as successive approximation type analog-to-digital converters, because the comparison process of these systems is sometimes sensitive to noise.

[0100] As shown in FIG. 2, the time domain comparison circuit 2 of the present application further includes a latch module 2f as an implementation manner of the present application. Figure 11 As shown, the time domain comparison circuit 2 of the present application further includes a latch module 2f as an implementation manner of the present application. The latch module 2f is connected to the output terminals of the first ring voltage-controlled oscillator 2a and the second ring voltage-controlled oscillator 2b, and is used to align the rising edges or falling edges of the first oscillation signal X and the second oscillation signal Y to avoid false triggering of the phase detector 2c. In this embodiment, for the phase detector with the NAND gate structure of Figure 5 the rising edges of the two signals input into the phase detector 2c are aligned to avoid false triggering. As an example, the latch module 2f includes a first latch and a second latch, wherein the first input terminal of the first latch receives the first oscillation signal X, the second input terminal receives the second oscillation signal Y, and the output terminal (output signal P_d) is connected to the first input terminal of the phase detector 2c; the first input terminal of the second latch receives the second oscillation signal Y, the second input terminal receives the first oscillation signal X, and the output terminal (output signal N_d) is connected to the second input terminal of the phase detector 2c. As shown in FIG. 2, the output signal P_d of the first latch is connected to the first input terminal of the phase detector 2c, and the output signal N_d of the second latch is connected to the second input terminal of the phase detector 2c. Figure 12As shown, the first latch and the second latch (27) each comprises a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, a third inverter not3 and a fourth inverter not4; wherein the third inverter not3 has a larger size than the fourth inverter not4; the source of the third PMOS transistor MP3 is connected to a power supply voltage VDD, the drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4, and the gate of the third PMOS transistor MP3 is used as the second input In2 of the corresponding latch; the drain of the fourth PMOS transistor MP4 and the drain of the third NMOS transistor MN3 are connected together, and the gate of the fourth PMOS transistor MP4 and the gate of the third NMOS transistor MN3 are connected together to be used as the first input In1 of the corresponding latch; the source of the third NMOS transistor MN3 is connected to ground; the third inverter not3 and the fourth inverter not4 are cross-coupled, the input of the third inverter not3 is connected to the drain of the fourth PMOS transistor MP4 and the drain of the third NMOS transistor MN3, and the output of the fourth inverter not4 is used as the output Out of the corresponding latch. Figure 13 As shown, the first oscillation signal X is ahead of the second oscillation signal Y, the first latch and the second latch have reverse functions, and thus at the rising edges of the first oscillation signal X and the second oscillation signal Y, the output signal P_d of the first latch and the output signal N_d of the second latch are falling edges, and the output signal P_d of the first latch is ahead of the output signal N_d of the second latch, i.e. time gain is reserved; at the falling edges of the first oscillation signal X and the second oscillation signal Y, the output signal P_d of the first latch and the output signal N_d of the second latch are rising edges, and the output signal P_d of the first latch is aligned with the output signal N_d of the second latch.

[0101] It should be noted that for the NOR gate structure of the phase detector, the falling edges of the two signals input into the phase detector 2c are aligned to avoid false triggering, which will not be described here.

[0102] As shown, Figure 14 As shown, the application further provides an analog-to-digital converter, which comprises a digital-to-analog conversion unit 3, a successive approximation logic unit 4 and the time-domain comparison circuit 2 of the application.

[0103] The digital-to-analog conversion unit 3 receives an input signal and adjusts an output voltage based on a control signal output by the successive approximation logic unit 4; as an example, the digital-to-analog conversion unit 3 adopts a differential structure and comprises a first switched capacitor array and a second switched capacitor array. The time-domain comparison circuit 2 is connected to the output end of the digital-to-analog conversion unit 3, compares the output voltage of the digital-to-analog conversion unit 3 with a reference voltage, and outputs a comparison result; for specific structure and working principle, please refer to the above description, which will not be described here. The successive approximation logic unit 4 is connected to the output end of the time-domain comparison circuit 2 and generates a control signal based on the comparison result.

[0104] The time domain comparison circuit and the analog-to-digital converter have low noise and high energy efficiency. Figure 1 Compared with the VCO comparator 1, the time domain comparison circuit of the present application can greatly reduce the average oscillation times and the average power consumption required for obtaining the comparison result each time under the same input voltage (even if the integral charging unit for generating the first adjustment signal VGn and the second adjustment signal VGp in the phase detector increases the load of the phase detector). Figure 6 Therefore, the time domain comparison circuit of the present application can improve the performance of the comparison circuit, greatly improve the energy efficiency of the comparison circuit, improve the high metastability problem of the original VCO comparator, and quickly obtain the comparison result (especially under a small amplitude input signal).

[0105] In summary, the present application provides a time domain comparison circuit and an analog-to-digital converter, which comprises a first ring voltage-controlled oscillator, a second ring voltage-controlled oscillator, and a phase detector. The first ring voltage-controlled oscillator adjusts the rising edge and falling edge delay of the oscillation signal based on the size relationship between the first input voltage and the second input voltage to obtain a first oscillation signal with a first oscillation frequency. The second ring voltage-controlled oscillator adjusts the rising edge and falling edge delay of the oscillation signal based on the size relationship between the first input voltage and the second input voltage to obtain a second oscillation signal with a second oscillation frequency. The phase detector receives and calculates the phase difference between the first oscillation signal and the second oscillation signal to obtain the size relationship between the first input voltage and the second input voltage based on the phase difference. The present application uses a current multiplexing VCO structure and a feedback adjustment method based on the number of oscillation periods to adjust the size of the phase detector dead time, thereby improving the performance of the time domain comparison circuit, improving the overall energy efficiency, optimizing the relationship between noise and energy consumption, and reducing the probability of metastability. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0106] The above embodiments only exemplarily illustrate the principles and effects of the present application and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A time domain comparison circuit, characterized in that: The time domain comparison circuit at least includes: A first ring voltage controlled oscillator, a second ring voltage controlled oscillator, a latch module, a phase detector and a dead time adjustment module; The first ring voltage-controlled oscillator adjusts the rising edge and falling edge delays of the oscillation signal based on the magnitude relationship between the first input voltage and the second input voltage to obtain a first oscillation signal with a first oscillation frequency; the second ring voltage-controlled oscillator adjusts the rising edge and falling edge delays of the oscillation signal based on the magnitude relationship between the first input voltage and the second input voltage to obtain a second oscillation signal with a second oscillation frequency; wherein, the first ring voltage-controlled oscillator and the second ring voltage-controlled oscillator both include N-stage delay modules and M-stage inversion modules that are sequentially cascaded to form a loop, N is a natural number greater than or equal to 1, and M is an odd number; the delay module includes a first gain adjustment tube, a second gain adjustment tube and a cascaded two-stage delay unit, each delay unit includes a first inversion unit, a first PMOS tube and a first NMOS tube, the first PMOS tube is connected in series between the power supply voltage and the power supply of the first inversion unit The first NMOS transistor is connected in series between the ground and the ground terminal of the first inverting unit; wherein the first inverting unit is connected in series on the loop; the gate of each first PMOS transistor in the delay module of the first ring voltage-controlled oscillator receives the first input voltage, and the gate of each first NMOS transistor receives the second input voltage; the gate of each first PMOS transistor in the delay module of the second ring voltage-controlled oscillator receives the second input voltage, and the gate of each first NMOS transistor receives the first input voltage; one end of the first gain adjustment tube is connected to the ground terminal of the first inverting unit in the first-stage delay unit, and the other end is grounded, and is controlled by the second adjustment signal output by the dead time adjustment module; one end of the second gain adjustment tube is connected to the ground terminal of the first inverting unit in the second-stage delay unit, and the other end is grounded, and is controlled by the first adjustment signal output by the dead time adjustment module; The latch module is connected to the output terminals of the first ring voltage controlled oscillator and the second ring voltage controlled oscillator, and is used to align the rising edge or the falling edge of the first oscillation signal and the second oscillation signal to avoid false triggering of the phase detector; The phase detector is connected to the output end of the latch module, receives and calculates the phase difference between the first oscillation signal and the second oscillation signal, and obtains the magnitude relationship between the first input voltage and the second input voltage based on the phase difference; The dead time adjustment module receives the output signal of the phase detector and generates a first adjustment signal and a second adjustment signal based on the number of oscillations of the output signal of the phase detector before flipping, so as to adjust the dead time of the phase detector, wherein the dead time of the phase detector is negatively correlated with the number of oscillations.

2. The time domain comparison circuit according to claim 1, wherein: Each delay module also includes a first reset tube and a second reset tube; the first reset tube is connected to the output end of the first-stage delay unit, is controlled by the enable signal, and is used to reset the output node of the first-stage delay unit; the second reset tube is connected to the output end of the second-stage delay unit, is controlled by the enable signal, and is used to reset the output node of the second-stage delay unit.

3. The time domain comparison circuit according to claim 1, wherein: One stage of the M-stage inversion module is a NAND gate; the first input end of the NAND gate is connected in the loop, the second input end receives an enable signal, and the output end is connected to the input end of the first-stage delay unit.

4. The time domain comparison circuit according to claim 3, wherein: The output terminals of the first ring voltage controlled oscillator and the second ring voltage controlled oscillator are arranged at any node between the output terminal of the last delay module in the loop and the first input terminal of the NAND gate.

5. The time domain comparison circuit according to claim 1, wherein: The dead time adjustment module includes a first adjustment unit and a second adjustment unit; each adjustment unit includes a second inverting unit, a second PMOS transistor and a second NMOS transistor, the second PMOS transistor is connected in series between the power supply voltage and the power supply terminal of the second inverting unit, and the second NMOS transistor is connected in series between the ground and the ground terminal of the second inverting unit; The gates of the second PMOS transistor and the second NMOS transistor in the first adjustment unit are connected to the first output signal of the phase detector, and the second inverting unit is controlled by the enable signal and outputs the first adjustment signal; the gates of the second PMOS transistor and the second NMOS transistor in the second adjustment unit are connected to the second output signal of the phase detector, and the second inverting unit is controlled by the enable signal and outputs the second adjustment signal; the first output signal and the second output signal of the phase detector are differential signals.

6. The time domain comparison circuit according to claim 5, wherein: The first adjustment signal and the second adjustment signal are further used to adjust the capacitance of the load capacitor in the phase detector.

7. The time domain comparison circuit according to claim 1, wherein: The latch module includes a first latch and a second latch, wherein the first input terminal of the first latch receives the first oscillation signal, and the second input terminal receives the second oscillation signal; the first input terminal of the second latch receives the second oscillation signal, and the second input terminal receives the first oscillation signal; the first latch and the second latch each include a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a third inverting unit, and a fourth inverting unit; wherein the size of the third inverting unit is larger than that of the fourth inverting unit; The source of the third PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the fourth PMOS transistor, and the gate serves as the second input terminal of the corresponding latch; The drains of the fourth PMOS transistor and the third NMOS transistor are connected together, and the gates are connected together as the first input end of the corresponding latch; the source of the third NMOS transistor is grounded; The third inverting unit is cross-coupled with the fourth inverting unit, the input end of the third inverting unit is connected to the drains of the fourth PMOS transistor and the third NMOS transistor, and the output end of the fourth inverting unit serves as the output end of the corresponding latch.

8. The time domain comparison circuit according to claim 1, wherein: The time domain comparison circuit further includes a logic module, which receives an output signal of the phase detector. When the phase detector outputs a comparison result, the logic module controls the first ring voltage controlled oscillator and the second ring voltage controlled oscillator to stop working and reset.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises at least: a digital-to-analog conversion unit, a successive approximation logic unit, and a time domain comparison circuit according to any one of claims 1 to 8; The digital-to-analog conversion unit receives an input signal and adjusts an output voltage based on a control signal output by the successive approximation logic unit; The time domain comparison circuit is connected to the output end of the digital-to-analog conversion unit, compares the output voltage of the digital-to-analog conversion unit with a reference voltage, and outputs a comparison result; The successive approximation logic unit is connected to the output end of the time domain comparison circuit and generates a control signal based on the comparison result.

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