Sampled data receiver with chopper stabilization

Abstract

The invention relates to a sampled data receiver with chopper stabilization. Embodiments herein provide various apparatuses and techniques to reduce flicker noise and voltage offset from buffers and / or amplifiers while avoiding additional aliasing components in sampled data receivers with chopper stabilization. In addition, the direct conversion baseband chain may be improved by providing alternating current (AC) coupling circuits between chopper circuits in the transmitter or receiver chain to enable selection of different common mode levels at each stage of the direct conversion chain while reducing or eliminating signal loss at direct current (DC) frequencies.

Description

Background Art

[0001] The present disclosure relates generally to wireless communications, and more particularly to signal modulation and down-conversion in transmitters and receivers in wireless communication devices.

[0002] Wireless communication devices include radio frequency front end (RFFE) circuits that can perform operations such as signal amplification and down conversion. Wireless communication devices may also include a baseband chain that can further amplify the desired signal while rejecting unwanted signals, known as jammers or blocking signals. Baseband chains have evolved from continuous-time circuits to discrete-time circuits that process sampled data to provide benefits such as reduced power consumption, increased linearity, and technology expansion. The baseband chain may include a chopper circuit. A chopper may include a device or technique for modulating (e.g., switching) a radio frequency signal on and off at a specific frequency. This process may be referred to as chopping or amplitude modulation.

[0003] Challenges to RFFE circuits (e.g., baseband chain) can include flicker noise and voltage offsets from buffers or amplifiers inserted between sampling circuits, which can limit performance in narrowband applications—especially in direct conversion scenarios. In some cases, chopper stabilization can be used to overcome flicker noise and voltage offsets, but may cause additional noise due to the chopper sampling operation. Summary of the invention

[0004] The following describes a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented only to provide the reader with a concise summary of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass a number of aspects that may not be described below.

[0005] In one embodiment, a receiver circuit may include: an amplifier; a first chopper circuit including a first output coupled to a first input of the amplifier; a second chopper circuit including a second input coupled to a second output of the amplifier and including a third output; a sampling circuit including a third input coupled to the third output of the second chopper circuit and a fourth input coupled to a clock signal generator; and a divider circuit coupled to the clock signal generator, the first chopper circuit, and the second chopper circuit.

[0006] In another embodiment, an electronic device may include: multiple antennas configured to receive signals; a transmitter coupled to the multiple antennas; and a receiver coupled to the multiple antennas and configured to receive the signals from the multiple antennas, the receiver may include: an amplifier coupled between a differential output of a first chopper circuit and a differential input of a second chopper circuit; a sampling circuit coupled to the differential output of the second chopper circuit and to a clock generator configured to provide a sampling clock frequency to the sampling circuit; and a clock divider circuit that may provide a chopper frequency to the first chopper circuit and the second chopper circuit based on the sampling clock frequency, the chopper frequency being configured to combine a first interference caused by the first chopper circuit and a second interference due to the second chopper circuit.

[0007] In yet another embodiment, a transceiver is provided, which may include: multiple antennas; a transmitter coupled to the multiple antennas; and a receiver coupled to the multiple antennas, which may include a first group of chopper circuits, a first sampling circuit coupled to the first group of chopper circuits and a first clock generator, a first divider circuit coupled to the first clock generator and the first group of chopper circuits, a second group of chopper circuits, a second sampling circuit coupled to the second group of chopper circuits and the second clock generator, and a second divider circuit coupled to the second clock generator and the second group of chopper circuits.

[0008] With respect to various aspects of the present disclosure, there may be various improvements to the above-mentioned features. Other features may also be incorporated into these various aspects. These improvements and additional features may exist individually or in any combination. For example, the various features discussed below with respect to one or more embodiments in the illustrated embodiments may be incorporated into any of the above-mentioned aspects of the present disclosure individually or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of the embodiments of the present disclosure, without limiting the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the drawings described below, in which like reference numerals refer to like parts.

[0010] Figure 1 is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 2 According to the embodiments of the present disclosure Figure 1 Functional diagram of electronic equipment;

[0012] Figure 3 According to the embodiments of the present disclosure Figure 1 A schematic diagram of a transmitter of an electronic device;

[0013] Figure 4 According to the embodiments of the present disclosure Figure 1 A schematic diagram of a receiver of an electronic device;

[0014] Figure 5 The invention is a method for reducing or eliminating the influence of aliasing components caused by a chopper circuit according to an embodiment of the present disclosure. Figure 4 Schematic diagram of the receiver circuit;

[0015] Figure 6 is a diagram showing an embodiment according to the present disclosure Figure 4 a schematic diagram of a direct conversion architecture for a receiver circuit of the invention, the direct conversion architecture improving the performance of the direct conversion circuit and enabling selection of a common mode level at each stage of the direct conversion circuit;

[0016] Figure 7 is a diagram showing an embodiment according to the present disclosure Figure 4 a schematic diagram of another direct conversion architecture of a receiver circuit of the invention, which improves the performance of the direct conversion circuit by placing an alternating current (AC) coupling circuit between the chopper circuit and at the output of the amplifier and enables selection of a common mode level at each stage of the direct conversion circuit; and

[0017] Figure 8 is a diagram showing an embodiment according to the present disclosure Figure 4 A schematic diagram of another direct conversion architecture for a receiver circuit of the invention that improves the performance of the direct conversion circuit by placing AC coupling circuits between the chopper circuits and at both the input and output of the amplifier and that enables selection of a common-mode level at each stage of the direct conversion circuit. DETAILED DESCRIPTION

[0018] When introducing the elements of various embodiments of the present disclosure, the articles "one", "an" and "the" are intended to mean one or more elements present in the elements. The terms "include", "comprise" and "have" are intended to be inclusive, and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that the reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the features. In addition, specific features, structures or characteristics can be combined in any appropriate manner in one or more embodiments. The use of the terms "roughly", "close to", "about", "close to" and / or "substantially" should be understood to mean including close to a target (e.g., design, value and amount), such as within the limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). In addition, it should be understood that any exact value, number, measurement value, etc. provided herein can be conceived to include approximate values ​​of these exact values, numbers, measurement values, etc. (e.g., within the limits of suitable or conceivable error). Additionally, the term "set" may include one or more. That is, a set may include a single set of one member, but a set may also include sets of multiple members.

[0019] Wireless communication devices include radio frequency front end (RFFE) circuits that can perform operations such as signal amplification and down conversion. Wireless communication devices may also include a baseband chain that can further amplify the desired signal while rejecting unwanted signals, referred to as jammers or blockers. Baseband chains have evolved from continuous time circuits to discrete time circuits that process sampled data to provide benefits such as reduced power consumption, increased linearity, and technology expansion. The baseband chain may include a chopper circuit. A chopper may include a device or technology for modulating (e.g., switching) a radio frequency signal on and off at a specific frequency. This process may be referred to as chopping or amplitude modulation. Challenges to RFFE circuits (e.g., baseband chains) may include flicker noise and voltage offsets from buffers or amplifiers inserted between sampling circuits, which may limit performance in narrowband applications—especially in direct conversion scenarios. In some cases, chopper stabilization may be used to overcome flicker noise and voltage offsets, but may cause additional noise due to the chopper sampling operation. The additional noise may be aliased (e.g., down converted) such that the additional noise may interfere with the desired signal. Noise that is down-converted into or near the desired signal may be referred to as an "aliasing component."

[0020] Embodiments herein provide various devices and techniques to reduce flicker noise and voltage offsets from buffers and / or amplifiers while avoiding additional aliasing components in a sampled data receiver with chopper stabilization. In addition, a direct conversion baseband chain can be improved by providing an alternating current (AC) coupling circuit between chopper circuits in a transmitter or receiver chain to enable selection of different common mode levels at each stage of the direct conversion chain while reducing or eliminating signal losses at direct current (DC) frequencies.

[0021] Figure 1 1 is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include, among other things, one or more processors 12 (collectively referred to herein as a single processor for convenience, which may be implemented in any suitable form of processing circuitry), a memory 14, a non-volatile storage device 16, a display 18, an input structure 22, an input / output (I / O) interface 24, a network interface 26, and a power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuits), software elements (including machine executable instructions), or a combination of hardware and software elements (which may be referred to as logical components). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to send and / or receive signals between each other. It should be noted that Figure 1 This is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10 .

[0022] By way of example, electronic device 10 may include any suitable computing device, including a desktop or laptop computer, a portable electronic or handheld electronic device (such as a wireless electronic device or a smart phone), a tablet computer, a wearable electronic device, and other similar devices. In additional or alternative embodiments, electronic device 10 may include an access point, such as a base station, a router (e.g., a wireless or Wi-Fi router), a hub, a switch, etc. It should be noted that Figure 1 The processor 12 and other related items in the embodiment may be embodied in whole or in part as software, hardware, or both. Figure 1The processor 12 and other related items in the electronic device 10 may be a single contained processing module, or may be fully or partially incorporated into any of the other elements within the electronic device 10. The processor 12 may be implemented using a combination of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, a gated logic, a discrete hardware component, a dedicated hardware finite state machine, or any other suitable entity that can perform calculations or other manipulations of information. The processor 12 may include one or more application processors, one or more baseband processors, or both, and perform various functions described herein.

[0023] exist Figure 1 In the electronic device 10, the processor 12 may be operably coupled to the memory 14 and the non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article including one or more tangible computer-readable media. The tangible computer-readable medium may include the memory 14 and / or the non-volatile storage device 16, individually or collectively, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard drive, and optical disk. In addition, the program (e.g., operating system) encoded on such a computer program product may also include instructions that can be executed by the processor 12 to enable the electronic device 10 to provide various functions.

[0024] In certain embodiments, display 18 may facilitate a user viewing images generated on electronic device 10. In some embodiments, display 18 may include a touch screen that may facilitate a user interacting with a user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light emitting diode (LED) displays, organic light emitting diode (OLED) displays, active matrix organic light emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0025] The input structures 22 of the electronic device 10 may enable a user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). As with the network interface 26, the I / O interface 24 may enable the electronic device 10 to interact with a variety of other electronic devices. In some embodiments, the I / O interface 24 may include an I / O port for a hardwired connection to charge and / or manipulate content using a standard connector and protocol (such as a Lightning connector, a universal serial bus (USB), or other similar connectors and protocols). The network interface 26 may include, for example, one or more interfaces for a personal area network (PAN), such as an ultra-wideband (UWB) or Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN), such as one of the IEEE 802.11x family of protocols (e.g., ) networks; and / or wide area networks (WANs), such as any standards associated with the Third Generation Partnership Project (3GPP), including, for example, 3rd generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), 4th generation (4G) cellular networks, (LTE) cellular network, Long Term Evolution Licensed Assisted Access (LTE-LAA) cellular network, 5th Generation (5G) cellular network and / or New Radio (NR) cellular network, 6th Generation (6G) or beyond 6G cellular network, satellite network, non-terrestrial network, etc. Specifically, the network interface 26 may include, for example, one or more interfaces for using a cellular communication standard of the 5G specification including a millimeter wave (mmWave) frequency range (e.g., 24.25 gigahertz (GHz) to 300 GHz) that defines and / or implements a frequency range for wireless communication. The network interface 26 of the electronic device 10 may allow communication through the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0026] The network interface 26 may also include, for example, one or more interfaces for: a broadband fixed wireless access network (eg, ), mobile broadband wireless network (mobile ), asynchronous digital subscriber line (e.g., ADSL, VDSL), digital video terrestrial broadcasting Network and its extension DVB handheld devices Networks, ultra-wideband (UWB) networks, alternating current (AC) power lines, etc.

[0027] As shown, the network interface 26 may include a transceiver 30. In some embodiments, all or part of the transceiver 30 may be disposed within the processor 12. The transceiver 30 may support sending and receiving various wireless signals via one or more antennas, and thus may include a transmitter and a receiver. The power supply 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0028] Figure 2 According to the embodiments of the present disclosure Figure 1 1 is a functional diagram of an electronic device 10. As shown, the processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) can be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to send and / or receive signals between each other.

[0029] The electronic device 10 may include a transmitter 52 and / or a receiver 54, both of which enable, for example, a network (e.g., including a base station or access point) or a direct connection to send and receive signals between the electronic device 10 and an external device. As shown, the transmitter 52 and the receiver 54 may be combined into a transceiver 30. The electronic device 10 may also have one or more antennas 55A-55N electrically coupled to the transceiver 30. The antennas 55A-55N may be configured in an omnidirectional or directional configuration, such as a single beam, a dual beam, or a multi-beam arrangement. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in the antennas 55A-55N of the antenna group or module may be communicatively coupled to the corresponding transceiver 30, and each transmits a radio frequency signal that may be constructively and / or destructively combined to form a beam. The electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas suitable for various communication standards. In some embodiments, transmitter 52 and receiver 54 may send and receive information via other wired or wired systems or components.

[0030] As illustrated, the various components of the electronic device 10 may be coupled together via a bus system 56. The bus system 56 may include, for example, a data bus and, in addition to the data bus, a power bus, a control signal bus, and a status signal bus. The components of the electronic device 10 may be coupled together or receive or provide input to each other using some other mechanism.

[0031] Figure 3is a schematic diagram of a transmitter 52 (e.g., a transmitting circuit) according to an embodiment of the present disclosure. As shown, the transmitter 52 may receive outgoing data 60 to be transmitted via one or more antennas 55 in the form of a digital signal. A digital-to-analog converter (DAC) 62 of the transmitter 52 may convert the digital signal into an analog signal, and a modulator 64 may combine the converted analog signal with a carrier signal to generate a radio wave. A power amplifier (PA) 66 receives the modulated signal from the modulator 64. The power amplifier 66 may amplify the modulated signal to a suitable level to drive the transmission of the signal via one or more antennas 55. A filter 68 (e.g., a filter circuit and / or software) of the transmitter 52 may then remove undesirable noise from the amplified signal to generate a transmit signal 70 to be transmitted via one or more antennas 55. The filter 68 may include any suitable one or more filters that remove undesirable noise from the amplified signal, such as a bandpass filter, a bandstop filter, a lowpass filter, a highpass filter, and / or a decimation filter.

[0032] The power amplifier 66 and / or the filter 68 may be referred to as part of a radio frequency front end (RFFE) (and more specifically, a transmit front end (TXFE) of the electronic device 10). In addition, the transmitter 52 may include any suitable additional components not shown, or may not include some of the components shown, so that the transmitter 52 can transmit the outgoing data 60 via one or more antennas 55. For example, the transmitter 52 may include a mixer and / or a digital upconverter. As another example, if the power amplifier 66 outputs an amplified signal within a desired frequency range or approximately within a desired frequency range (such that filtering the amplified signal may not be necessary), the transmitter 52 may not include the filter 68.

[0033] Figure 4 8 is a schematic diagram of a receiver 54 (e.g., receiving circuit) according to an embodiment of the present disclosure. As shown, the receiver 54 may receive a received signal 80 from one or more antennas 55 in the form of an analog signal. A low noise amplifier (LNA) 82 may amplify the received analog signal to a suitable level for processing by the receiver 54. A filter 84 (e.g., a filter circuit and / or software) may remove unwanted noise such as cross-channel interference from the received signal. The filter 84 may also remove additional signals received by one or more antennas 55 at a frequency different from the desired signal. The filter 84 may include any one or more suitable filters for removing unwanted noise or signals from the received signal, such as a bandpass filter, a bandstop filter, a low-pass filter, a high-pass filter, and / or a decimation filter. The low noise amplifier 82 and / or the filter 84 may be referred to as part of the RFFE, and more specifically, as a receiver front end (RXFE) of the electronic device 10.

[0034] The demodulator 86 may remove the RF carrier signal from the filtered signal and / or extract the demodulated signal (e.g., envelope signal) for processing. The analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert the signal into a digital signal of the incoming data 90 for further processing by the electronic device 10. In addition, the receiver 54 may include any suitable additional components not shown, or may not include some of the components shown, so that the receiver 54 can receive the received signal 80 via one or more antennas 55. For example, the receiver 54 may include a mixer and / or a digital down converter.

[0035] Figure 5 is a schematic diagram of a receiver circuit 100 for reducing or eliminating the influence of aliasing components caused by a chopper circuit according to an embodiment of the present disclosure. The receiver circuit 100 may include the above Figure 4 Receiver circuit 100 includes one or more antennas 55, front-end circuit 102, anti-aliasing circuit 104, chopper circuits 106A, 106B, 106C, and 106D (collectively, chopper circuit 106), amplifiers 108A and 108B (collectively, amplifier 108), sampling circuits 110A and 110B (collectively, sampling circuit 110), and frequency dividers 112A and 112B (collectively, frequency divider 112). A desired (e.g., target) signal 114 (e.g., f) may be received via antenna 55. sig ). Noise such as blocking signal 116 (eg, f blk ) may also be received at the antenna 55 concurrently with the desired signal 114. The addition of the chopper circuit 106 may introduce additional noise, such as a blocking signal 118. The blocking signals 116 and 118 may be offset or distanced away from the desired signal (e.g., 2f ch1 However, the sampling circuit 110 may down-convert or alias the blocking signal, so that the blocking signal overlaps with the desired signal 114 , thereby causing or aggravating interference with the desired signal 114 .

[0036] The anti-aliasing circuit 104 can reduce the amplitude of the blocking signals 116 and 118 before the blocking signal 116 and the desired signal 114 reach the chopper circuit 106. The anti-aliasing circuit 104 may include a filter circuit, such as a low-pass filter, a high-pass filter, or a band-pass filter. An amplifier 108A (e.g., a differential amplifier such as an operational amplifier) ​​may be disposed between the chopper circuits 106A and 106B, such that an input terminal of the amplifier 108A may be coupled to the output of the chopper circuit 106A and an output terminal of the amplifier 108A may be coupled to the input of the chopper circuit 106B. The output of the chopper circuit 106B may be coupled to the input of the sampling circuit 110A. The output of the sampling circuit 110A may be coupled to the input of the chopper circuit 106C. The output of the chopper circuit 106C may be coupled to the input terminal of the amplifier 108B (e.g., a differential amplifier such as an operational amplifier), and the output terminal of the amplifier 108B may be coupled to the input of the chopper circuit 106D. The output of the chopper circuit 106D may be coupled to an input of a sampling circuit 110B. The sampling circuit 110 may include a switching network, such as a switched capacitor unit. The switched capacitor unit may include two switch branches coupled via capacitors coupled in parallel. Although only two switch branches and one capacitor are shown, it should be noted that the sampling circuit # may include any suitable number of switch branches coupled via one or more capacitors. The output of the sampling circuit 110B may be coupled to an analog-to-digital converter (ADC) 128 or may be coupled to another sampling stage of the receiver circuit 100. That is, the output of the sampling circuit 110B may be coupled to the input of another set of chopper circuits 106, another amplifier 108, and / or another sampling circuit 110.

[0037] Although the anti-aliasing circuit 104 can reduce the amplitude of the blocking signals 116 and 118, the blocking signals 116 and 118 can still interfere with the desired signal 114 when down-converted (e.g., by the sampling circuit 110A), thereby negatively affecting the performance of the receiver circuit 100. The sampling circuit 110A can receive a sampling clock frequency 120 (e.g., f ck1 ), and the chopper circuit 106 may receive a chopper frequency 122 (eg, f ch1 ). In some cases, the relationship between chopper frequency 122 and sampling clock frequency 120 may cause blocking signals 116 and 118 to be down-converted into or near desired signal 114, thereby adversely affecting the performance of receiver circuit 100. To reduce or eliminate the effects of down-conversion, the clock frequency of chopper circuit 106 may be adjusted so that blocking signal 116 overlaps blocking signal 118, thereby reducing the overall interference with desired signal 114.

[0038] The chopper frequency 122 may be derived from the sampling clock frequency 120 such that Where n represents a harmonic of the sampling clock frequency 120. To achieve this relationship, a frequency divider 112 may be implemented between the sampling clock frequency 120 (e.g., a sampling clock frequency generator) and the chopper circuit 106. By setting the chopper frequency 122 to 1 / 2 of the sampling clock frequency 122, the blocking signal 116 will be merged into the blocking signal 118, thereby reducing the overall noise experienced by the receiver circuit 100. It should be noted that the chopper frequency 122 may be derived as a value other than 1 / 2 of the sampling clock frequency 120. For example, the chopper frequency 122 may be set to another suitable integer multiple or factor of 3 / 2 or 1 / 2 of the sampling clock frequency 120.

[0039] The sampling circuit 110A may receive a sampling clock frequency 124 (eg, f ck2 ), and the chopper circuit 106 may receive a chopper frequency 126 (eg, f ch2 ). In some cases, the relationship between chopper frequency 126 and sampling clock frequency 124 may cause the blocking signal to be down-converted into or near desired signal 114, thereby adversely affecting the performance of receiver circuit 100. To reduce or eliminate the effects of down-conversion of the blocking signal, the clock frequencies of chopper circuits 106C and 106D may be adjusted so that the blocking signal due to chopper circuits 106C and 106D overlaps the blocking signal received via antenna 55, thereby reducing the overall interference with desired signal 114.

[0040] The chopper frequency 126 may be derived from the sampling clock frequency 124, as discussed above with respect to the chopper frequency 122 and the sampling clock frequency 120. To achieve this, a frequency divider 112B may be implemented between the sampling clock frequency 124 (e.g., a sampling clock frequency generator) and the chopper circuits 106C and 106D. By setting the chopper frequency 126 to ½ of the sampling clock frequency 124, the blocking signal due to the chopper circuit 106 will be incorporated into the blocking signal received at the antenna 55, thereby reducing the overall noise experienced by the receiver circuit 100. It should be noted that the chopper frequency 126 may be derived to a value other than ½ of the sampling clock frequency 124. For example, the chopper frequency 126 may be set to another suitable integer multiple of 3 / 2 or ½ of the sampling clock frequency.

[0041] Figure 61 is a schematic diagram showing a direct conversion architecture of a receiver circuit 150 according to an embodiment of the present disclosure, which improves the performance of the direct conversion circuit and enables the selection of a desired or target common mode level at each stage of the direct conversion circuit. As previously discussed, the direct conversion baseband chain can be improved by providing an AC coupling circuit between chopper circuits in a transmitter or receiver chain to enable the selection of a different common mode level at each stage of the direct conversion chain while reducing or eliminating signal losses at DC frequencies. Chopper stabilization can improve the performance of a direct conversion receiver circuit (e.g., receiver circuit 150) by reducing or eliminating flicker noise and offset, but alignment of the common mode level between stages may be desired for improved performance. In addition, for each stage of the receiver circuit 150, a different common mode level may be desired. In some scenarios, the AC coupling circuit may be implemented so that the AC corner frequency is less than (e.g., significantly less than) the signal bandwidth divided by 2. For example, the AC corner frequency may be less than 100 kilohertz (100kHz). However, in some cases, the specific implementation of the AC coupling circuit may result in signal power loss at DC frequencies, which may be particularly challenging for the direct conversion architecture. However, by embedding the AC coupling circuit into the chopper circuit 106 (e.g., by implementing the AC coupling circuit between groups of chopper circuits 106), signal losses can be reduced or eliminated while enabling each stage of the receiver circuit 150 to select a different (e.g., stage-specific) common-mode level.

[0042] Receiver circuit 150 may include antenna 55, front end circuit 102, anti-aliasing circuit 104, chopper circuit 106, amplifier 108, sampling circuit 110 and / or ADC 128, as described with reference to FIG. Figure 5 The receiver circuit 150 may also include clock generators 152A and 152B (collectively referred to as clock generators 152) coupled between the sampling clock frequency (eg, configured to generate the sampling clock frequency f ck1 and f ck2 The clock generator 152 may set the chopper frequencies 122 and 126 for the chopper circuit 106. In some embodiments, the clock generator 152 may include, for example, Figure 5 The divider 112 discussed. In this way, Figure 5 The implementation scheme can be Figures 6 to 8 The architecture can be implemented separately or combined with Figure 5 The aliasing reduction functionality is similar to Figures 6 to 8 The combination of improved direct conversion chain performance and common mode level selection capability.

[0043] Receiver circuit 150 may also include AC coupling circuits 154A and 154B (collectively referred to as AC coupling circuit 154). AC coupling circuit 154A may include capacitors 156A and 156B and / or resistor 158A. Capacitor 156A may be coupled in series between a first output terminal of chopper circuit 106A and a first input terminal of amplifier 108A. Capacitor 156B may be coupled in series between a second output terminal of chopper circuit 106A and a second input terminal of amplifier 108A. Resistor 158A may be coupled in parallel between the input terminals of amplifier 108A, such that a first terminal of resistor 158A may be coupled between capacitor 156A and the first input terminal of amplifier 108A at node 160, and a second terminal of resistor 158A may be coupled between capacitor 156B and the second input terminal of amplifier 108A at node 162. AC coupling circuit 154A may enable selection of a desired or target common mode voltage 164A (e.g., V CM1 ). In addition, by embedding the AC coupling circuit 154A between the chopper circuits 106A and 106B (such as Figure 6 ), chopper circuit 106A may perform frequency conversion on desired signal 114 and chopper circuit 106B may perform signal conversion on desired signal 114, and thus AC coupling circuit 154A may not exclude any DC frequencies in desired signal 114, but may exclude DC frequencies in a portion of chopper frequency 122. This may improve the signal quality and signal power of desired signal 114.

[0044] Likewise, AC coupling circuit 154B may include capacitors 156C and 156D and / or resistor 158B. Capacitor 156C may be coupled in series between a first output terminal of chopper circuit 106C and a first input terminal of amplifier 108B. Capacitor 156D may be coupled in series between a second output terminal of chopper circuit 106C and a second input terminal of amplifier 108B. Resistor 158B may be coupled in parallel between the input terminals of amplifier 108B such that a first terminal of resistor 158B may be coupled between capacitor 156C and the first input terminal of amplifier 108B at node 166, and a second terminal of resistor 158B may be coupled between capacitor 156D and the second input terminal of amplifier 108B at node 168. AC coupling circuit 154A may enable selection of a desired or target common mode voltage 164B (e.g., V CM2 ). In addition, by embedding the AC coupling circuit 154A between the chopper circuits 106A and 106B (such as Figure 6), chopper circuit 106C may perform frequency conversion on desired signal 114 and chopper circuit 106D may perform signal conversion on desired signal 114, and thus AC coupling circuit 154B may not exclude any DC frequencies in desired signal 114, but may exclude DC frequencies in a portion of chopper frequency 126. This may improve the signal quality and signal power of desired signal 114.

[0045] Figure 7 1 is a schematic diagram illustrating another direct conversion architecture of a receiver circuit 200 according to an embodiment of the present disclosure, which improves the performance of the direct conversion circuit by placing an AC coupling circuit between the chopper circuit and at the output of the amplifier and enables selection of a desired or target common-mode level at each stage of the direct conversion circuit. The receiver circuit 200 may be structurally and operationally similar to the receiver circuit 150, except that the AC coupling circuit 154A is implemented at the output of the amplifier 108A (rather than at the input of the amplifier 108A, as shown in FIG. 1 ). Figure 6 ) and AC coupling circuit 154B is implemented at the output of amplifier 108B (rather than at the input of amplifier 108B, as shown Figure 6 ). In receiver circuit 200, capacitor 156A may be coupled in series between a first output of amplifier 108A and a first input of chopper circuit 106B. Capacitor 156B may be coupled between a second output of amplifier 108A and a second input of chopper circuit 106B. Resistor 158A may be coupled in parallel between the inputs of chopper circuit 106B. A first terminal of resistor 158A may be coupled between capacitor 156A and the first input of chopper circuit 106B at node 202, and a second terminal of resistor 158A may be coupled between capacitor 156B and the second input of chopper circuit 106B at node 204. Similar to receiver circuit 150, a desired or target common-mode voltage 206A (V CM 2). The capacitance values ​​of capacitors 156A and 156B and the resistance value of resistor 158A may be selected to ensure that the AC corners of the first stage (eg, amplifier 108A and switching circuit 110A) are sufficiently low (eg, significantly less than chopper frequencies 122 and 126).

[0046] Turning to AC coupling circuit 154B, capacitor 156C may be coupled in series between a first output of amplifier 108B and a first input of chopper circuit 106D. Capacitor 156B may be coupled between a second output of amplifier 108B and a second input of chopper circuit 106B. Resistor 158B may be coupled in parallel between the inputs of chopper circuit 106D. A first terminal of resistor 158B may be coupled between capacitor 156C and the first input of chopper circuit 106D at node 208, and a second terminal of resistor 148B may be coupled between capacitor 156D and the second input of chopper circuit 106D at node 210. A desired or target common mode voltage 206B (V CM 3). The capacitance values ​​of capacitors 156A and 156B and the resistance value of resistor 158A may be selected to ensure that the AC corners of subsequent stages (eg, amplifier 108B and switching circuit 110B) are sufficiently low (eg, significantly less than chopper frequencies 122 and 126).

[0047] Figure 8 is a schematic diagram illustrating another direct conversion architecture of a receiver circuit 250 according to an embodiment of the present disclosure, which improves the performance of the direct conversion circuit by placing AC coupling circuits between the chopper circuits and at both the input and output of the amplifier and enables the selection of common mode levels at each stage of the direct conversion circuit. The receiver circuit 250 may be structurally and operationally similar to the receiver circuits 150 and 200, except that each amplifier 108 is coupled to an AC coupling circuit 154 at each input and output. As can be observed from the receiver circuit 250, the AC coupling circuit 154A may be coupled to the input of the amplifier 108A, the AC coupling circuit 154B may be coupled to the output of the amplifier 108A, the AC coupling circuit 154C may be coupled to the input of the amplifier 108B, and the AC coupling circuit 154D may be coupled to the output of the amplifier 108B.

[0048] AC coupling circuit 154A may include capacitors 156A and 156B and resistor 158A. Capacitor 156A may be coupled in series between a first output terminal of chopper circuit 106A and a first input terminal of amplifier 108A. Capacitor 156B may be coupled in series between a second output terminal of chopper circuit 106A and a second input terminal of amplifier 108A. Resistor 158A may be coupled in parallel between the input terminals of amplifier 108A such that a first terminal of resistor 158A may be coupled between capacitor 156A and the first input terminal of amplifier 108A at node 252, and a second terminal of resistor 158A may be coupled between capacitor 156B and the second input terminal of amplifier 108A at node 254. AC coupling circuit 154A may enable selection of a desired or target common-mode input voltage 164A (e.g., V ) based on a desired input of a subsequent stage (e.g., switching circuit 110B and / or amplifier 108B). CM1 The capacitance values ​​of capacitors 156A and 156B and the resistance value of resistor 158A may be selected to ensure that the AC cornering of the first stage (eg, amplifier 108A and switching circuit 110A) is sufficiently low (eg, significantly less than chopper frequencies 122 and 126).

[0049] AC coupling circuit 154B includes capacitors 156C and 156D and resistor 158B. Capacitor 156C may be coupled in series between the first output of amplifier 108A and the first input of chopper circuit 106B. Capacitor 156D may be coupled between the second output of amplifier 108A and the second input of chopper circuit 106B. Resistor 158B may be coupled in parallel between the inputs of chopper circuit 106B. The first terminal of resistor 158A may be coupled between capacitor 156C and the first input of chopper circuit 106B at node 256, and the second terminal of resistor 158B may be coupled between capacitor 156D and the second input of chopper circuit 106B at node 258. A desired or target common-mode output voltage 260A (V CMO 1). The capacitance values ​​of capacitors 156C and 156D and the resistance value of resistor 158B may be selected to ensure that the AC corners of the first stage (eg, amplifier 108A and switching circuit 110A) are sufficiently low (eg, significantly less than chopper frequencies 122 and 126).

[0050] Additionally, by embedding the AC coupling circuits 154A and 154B between the chopper circuits 106A and 106B, the chopper circuit 106A may perform frequency conversion on the desired signal 114 and the chopper circuit 106B may perform signal conversion on the desired signal 114, and thus the AC coupling circuits 154A and 154B may exclude little or no DC frequencies in the desired signal 114, but may exclude DC frequencies in a portion of the chopper frequency 122. This may improve the signal quality and signal power of the desired signal 114, and improve the overall performance of the receiver circuit 250.

[0051] AC coupling circuit 154C may include capacitors 156E and 156F and resistor 158C. Capacitor 156E may be coupled in series between a first output terminal of chopper circuit 106C and a first input terminal of amplifier 108B. Capacitor 156F may be coupled in series between a second output terminal of chopper circuit 106C and a second input terminal of amplifier 108B. Resistor 158C may be coupled in parallel between the input terminals of amplifier 108B such that a first terminal of resistor 158C may be coupled between capacitor 156E and the first input terminal of amplifier 108B at node 262, and a second terminal of resistor 158C may be coupled between capacitor 156F and the second input terminal of amplifier 108B at node 264. AC coupling circuit 154C may enable selection of a desired or target common-mode input voltage 164B (e.g., V CM 2). The capacitance values ​​of capacitors 156E and 156F and the resistance value of resistor 158C may be selected to ensure that the AC cornering of the second stage (eg, amplifier 108B and switching circuit 110B) is sufficiently low (eg, significantly less than chopper frequencies 122 and 126).

[0052] AC coupling circuit 154D may include capacitors 156G and 156H and resistor 158D. Capacitor 156G may be coupled in series between a first output of amplifier 108B and a first input of chopper circuit 106D. Capacitor 156H may be coupled in series between a second output of amplifier 108B and a second input of chopper circuit 106D. Resistor 158D may be coupled in parallel between the inputs of chopper circuit 106D. A first terminal of resistor 158B may be coupled between capacitor 156G and a first input of chopper circuit 106D at node 266, and a second terminal of resistor 158D may be coupled between capacitor 156H and a second input of chopper circuit 106D at node 268. A desired or target common-mode output voltage 260B (VCMO 2). The capacitance values ​​of capacitors 156G and 156H and the resistance value of resistor 158D may be selected to ensure that the AC corners of the second stage (eg, amplifier 108B and switching circuit 110B) are sufficiently low (eg, significantly less than chopper frequencies 122 and 126).

[0053] Additionally, by embedding the AC coupling circuit 154D between the chopper circuits 106C and 106D, the chopper circuit 106C may perform frequency conversion on the desired signal 114 and the chopper circuit 106D may perform signal conversion on the desired signal 114, and thus the AC coupling circuit 154D may exclude little or no DC frequencies in the desired signal 114, but may exclude DC frequencies in a portion of the chopper frequency 126. This may improve the signal quality and signal power of the desired signal 114 and the performance of the receiver circuit 250.

[0054] It should be noted that the receiver circuits 100, 150, 200 and / or 250 may include Figure 4 In addition, the same principles can be applied to the receiver 54 discussed above. Figure 3 The transmitter 52 discussed.

[0055] In one embodiment, a receiver circuit may include: a first chopper circuit; an alternating current (AC) coupling circuit coupled to the output of the first chopper circuit and to the input of an amplifier, the AC coupling circuit including a first capacitor coupled to a first input terminal of the amplifier, a second capacitor coupled to a second input terminal of the amplifier, and a resistor coupled in series between the first and second input terminals of the amplifier; and a second chopper circuit coupled to the output of the amplifier.

[0056] The receiver circuit includes a sampling circuit coupled to the output of the second chopper circuit, the sampling circuit configured to receive a sampling clock frequency from the first clock generator.

[0057] The receiver circuit includes a second clock generator coupled at an input to the first clock generator and coupled at an output to the first chopper circuit and to the second chopper circuit.

[0058] Wherein the second clock generator of the receiver circuit is configured to provide a chopper frequency to the first chopper circuit and the second chopper circuit based on the sampling clock frequency.

[0059] Wherein the second clock generator of the receiver circuit comprises a frequency divider circuit and is configured to adjust the chopper frequency such that the chopper frequency is equal to a multiple of one-half of the sampling clock frequency.

[0060] The AC coupling circuit of the receiver circuit is configured to exclude direct current (DC) frequencies from the chopper frequency.

[0061] Wherein the first capacitor, the second capacitor, and the resistor are configured to provide an AC corner frequency associated with the amplifier.

[0062] The receiver circuit includes a third chopper circuit coupled to the output of the sampling circuit and to an additional AC coupling circuit coupled to an input of the additional amplifier.

[0063] The additional AC coupling circuit of the receiver circuit includes a third capacitor, a fourth capacitor and a second resistor.

[0064] Wherein the third capacitor, the fourth capacitor and the second resistor of the receiver circuit are configured to provide an additional AC corner frequency associated with the additional amplifier, wherein the additional AC corner frequency is different from the AC corner frequency.

[0065] An electronic device includes: multiple antennas configured to receive signals; a transmitter coupled to the multiple antennas; and a receiver coupled to the multiple antennas and configured to receive signals from the multiple antennas, the receiver including: a first chopper circuit; an amplifier including a differential input terminal coupled to an output terminal of the first chopper circuit; an alternating current (AC) coupling circuit coupled to the differential output terminal of the amplifier; and a second chopper circuit including a first input terminal and a second input terminal coupled to the output terminal of the AC coupling circuit.

[0066] The AC coupling circuit of the electronic device includes: a first capacitor, which is coupled between the first output terminal of the differential output terminal of the amplifier and the first input terminal of the first chopper circuit; a second capacitor, which is coupled between the second output terminal of the differential output terminal of the amplifier and the second input terminal of the second chopper circuit; and a resistor, which is coupled in parallel between the first input terminal and the second input terminal of the second chopper circuit.

[0067] The first capacitor, the second capacitor, and the resistor of the electronic device are configured to provide an AC corner frequency associated with the amplifier.

[0068] The electronic device includes an additional AC coupling circuit, the additional AC coupling circuit including: a third capacitor; a fourth capacitor; and a second resistor, the second resistor being coupled in parallel to the first capacitor and the second capacitor.

[0069] Wherein the third capacitor, the fourth capacitor and the second resistor are configured to provide an additional AC corner frequency to a subsequent stage of the receiver, the additional AC corner frequency being different from the AC corner frequency.

[0070] The subsequent stage of the receiver includes a third chopper circuit, a fourth chopper circuit and a second amplifier, and the additional AC coupling circuit is arranged between the second amplifier and the fourth chopper circuit.

[0071] A transceiver includes: a plurality of antennas; a transmitter coupled to the plurality of antennas; and a receiver coupled to the plurality of antennas and including: a first group of chopper circuits including a first chopper circuit and a second chopper circuit; a first amplifier, a first alternating current (AC) coupling circuit, and a second AC coupling circuit embedded between the first chopper circuit and the second chopper circuit; a second group of chopper circuits including a third chopper circuit and a fourth chopper circuit; and a second amplifier, a third AC coupling circuit, and a fourth AC coupling circuit embedded between the third chopper circuit and the fourth chopper circuit.

[0072] The transceiver, wherein the output of the first chopper circuit is coupled to the input of the first AC coupling circuit, the output of the first AC coupling circuit is coupled to the differential input of the first amplifier, the differential output of the first amplifier is coupled to the input of the second AC coupling circuit, and the output of the second AC coupling circuit is coupled to the second chopper circuit.

[0073] The transceiver, wherein the output of the third chopper circuit is coupled to the input of the third AC coupling circuit, the output of the third AC coupling circuit is coupled to the differential input of the second amplifier, the differential output of the second amplifier is coupled to the input of the fourth AC coupling circuit, and the output of the fourth AC coupling circuit is coupled to the fourth chopper circuit.

[0074] The transceiver, wherein the first AC coupling circuit is configured to provide a first common-mode input voltage level to the first amplifier, the second AC coupling circuit is configured to provide a second common-mode output voltage level to the first amplifier, the third AC coupling circuit is configured to provide the second common-mode input voltage level to the second amplifier, and the fourth AC coupling circuit is configured to provide a second common-mode output voltage level to the second amplifier.

[0075] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0076] The technology presented and claimed herein is cited and applied to specific examples of a physical and practical nature that significantly improves the art and is therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be interpreted in accordance with 35 U.S.C. 112(f).

[0077] It is understood that the use of personally identifiable information should be subject to privacy policies and practices that are generally recognized to meet or exceed industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of the authorized use should be clearly stated to users.

Claims

1. A receiver circuit, the receiver circuit comprising: Amplifier; a first chopper circuit comprising a first output coupled to a first input of the amplifier; a second chopper circuit comprising a second input coupled to the second output of the amplifier and comprising a third output; a sampling circuit comprising a third input coupled to the third output of the second chopper circuit and a fourth input coupled to a clock signal generator; and A frequency divider circuit is coupled to the clock signal generator, the first chopper circuit, and the second chopper circuit. 2 . The receiver circuit of claim 1 , wherein the clock signal generator is configured to output a sampling clock frequency. 3 . The receiver circuit of claim 2 , wherein the frequency divider circuit is configured to provide a chopper frequency equal to one-half the sampling clock frequency.

4. The receiver circuit according to claim 1, comprising: Additional amplifier; a third chopper circuit comprising a fourth output coupled to a fifth input of the amplifier; and A fourth chopper circuit includes a sixth input coupled to the fifth output of the amplifier.

5. The receiver circuit of claim 4, comprising an additional sampling circuit coupled to the output of the fourth chopper circuit, the additional sampling circuit coupled to an additional clock generator configured to output an additional sampling clock frequency.

6. The receiver circuit of claim 5 , comprising an additional frequency divider coupled to the additional clock generator and to the third chopper circuit and the fourth chopper circuit, the additional frequency divider being configured to provide an additional chopper frequency to the third chopper circuit and the fourth chopper circuit. 7 . The receiver circuit of claim 6 , wherein the frequency divider circuit is configured to provide the additional chopper frequency based on the additional sampling clock frequency.

8. The receiver circuit of claim 7, wherein the additional chopper frequency comprises a frequency equal to one-half the additional sampling clock frequency.

9. The receiver circuit of claim 7, wherein the additional chopper frequency comprises a frequency equal to three-half of the additional sampling clock frequency.

10. An electronic device, comprising: a plurality of antennas configured to receive signals; a transmitter coupled to the plurality of antennas; and a receiver coupled to the plurality of antennas and configured to receive the signals from the plurality of antennas, the receiver comprising an amplifier coupled between the differential output of the first chopper circuit and the differential input of the second chopper circuit, a sampling circuit coupled to the differential output of the second chopper circuit and to a clock generator configured to provide a sampling clock frequency to the sampling circuit, and A clock divider circuit is configured to provide a chopper frequency to the first chopper circuit and the second chopper circuit based on the sampling clock frequency, the chopper frequency being configured to combine a first interference caused by the first chopper circuit and a second interference caused by the second chopper circuit. 11 . The electronic device of claim 10 , wherein the clock divider circuit is configured to adjust the chopper frequency such that the chopper frequency comprises a frequency equal to one-half of the sampling clock frequency.

12. The electronic device of claim 10, wherein the sampling circuit comprises a switched capacitor unit.

13. The electronic device of claim 10, the receiver comprising an anti-aliasing circuit coupled to one of the plurality of antennas and configured to reduce a magnitude of the first interference, the second interference, or both.

14. The electronic device of claim 13, wherein the anti-aliasing circuit comprises a low pass filter.

15. The electronic device of claim 10, wherein the amplifier comprises an operational amplifier.

16. A transceiver, comprising: Multiple antennas; a transmitter coupled to the plurality of antennas; and a receiver coupled to the plurality of antennas and comprising The first set of chopper circuits, a first sampling circuit coupled to the first set of chopper circuits and a first clock generator, a first frequency divider circuit coupled to the first clock generator and the first set of chopper circuits, The second chopper circuit, a second sampling circuit coupled to the second set of chopper circuits and a second clock generator, and A second frequency divider circuit is coupled to the second clock generator and the second set of chopper circuits. 17 . The transceiver of claim 16 , wherein the first clock generator is configured to provide a first clock sampling frequency to the first sampling circuit. 18 . The transceiver of claim 17 , wherein the first divider circuit is configured to provide a first chopper frequency associated with the first set of chopper circuits based on the first clock sampling frequency.

19. The transceiver of claim 18, wherein the first divider circuit is configured to output the first chopper frequency at a frequency equal to a multiple of one-half of the first clock sampling frequency.

20. The transceiver of claim 16, wherein the second clock generator is configured to provide a second clock sampling frequency to the second sampling circuit, and the second divider circuit is configured to provide a second chopper frequency associated with the second group of chopper circuits based on the second clock sampling frequency.

21. A receiver circuit, the receiver circuit comprising: a first chopper circuit; an alternating current (AC) coupling circuit coupled to the output of the first chopper circuit and to an input of an amplifier, the AC coupling circuit comprising a first capacitor coupled to a first input terminal of the amplifier, a second capacitor coupled to a second input terminal of the amplifier, and a resistor coupled in series between the first input terminal and the second input terminal of the amplifier; and A second chopper circuit is coupled to the output of the amplifier.

22. The receiver circuit of claim 21, comprising a sampling circuit coupled to the output of the second chopper circuit, the sampling circuit configured to receive a sampling clock frequency from a first clock generator.

23. The receiver circuit of claim 22, comprising a second clock generator coupled at an input to the first clock generator and coupled at an output to the first chopper circuit and the second chopper circuit.

24. The receiver circuit of claim 23, wherein the second clock generator is configured to provide a chopper frequency to the first chopper circuit and the second chopper circuit based on the sampling clock frequency.

25. The receiver circuit of claim 24, wherein the second clock generator comprises a frequency divider circuit and is configured to adjust the chopper frequency such that the chopper frequency is equal to a multiple of one-half the sampling clock frequency.

26. The receiver circuit of claim 24, wherein the AC coupling circuit is configured to exclude direct current (DC) frequencies from the chopper frequency.

27. The receiver circuit of claim 21, wherein the first capacitor, the second capacitor, and the resistor are configured to provide an AC corner frequency associated with the amplifier.

28. The receiver circuit of claim 27, comprising a third chopper circuit coupled to the output of the sampling circuit and to an additional AC coupling circuit coupled to the input of the additional amplifier.

29. The receiver circuit of claim 28, wherein the additional AC coupling circuit comprises a third capacitor, a fourth capacitor, and a second resistor.

30. The receiver circuit of claim 29, wherein the third capacitor, the fourth capacitor, and the second resistor are configured to provide an additional AC corner frequency associated with the additional amplifier, wherein the additional AC corner frequency is different than the AC corner frequency.

31. An electronic device, comprising: a plurality of antennas configured to receive signals; a transmitter coupled to the plurality of antennas; and a receiver coupled to the plurality of antennas and configured to receive the signals from the plurality of antennas, the receiver comprising First chopper circuit, an amplifier comprising a differential input terminal coupled to an output terminal of the first chopper circuit, an alternating current (AC) coupling circuit coupled to the differential output terminals of the amplifier, and a second chopper circuit including a first input terminal and a second input terminal coupled to the output terminal of the AC coupling circuit.

32. The electronic device of claim 31 , wherein the AC coupling circuit comprises a first capacitor coupled between a first output terminal of the differential output terminal of the amplifier and the first input terminal of the first chopper circuit, a second capacitor coupled between a second output terminal of the differential output terminal of the amplifier and the second input terminal of the second chopper circuit, and A resistor is coupled in parallel between the first input terminal and the second input terminal of the second chopper circuit.

33. The electronic device of claim 32, wherein the first capacitor, the second capacitor, and the resistor are configured to provide an AC corner frequency associated with the amplifier.

34. The electronic device of claim 33, comprising an additional AC coupling circuit, the additional AC coupling circuit comprising: A third capacitor; a fourth capacitor; and A second resistor is coupled in parallel to the first capacitor and the second capacitor.

35. The electronic device of claim 34, wherein the third capacitor, the fourth capacitor, and the second resistor are configured to provide an additional AC corner frequency to a subsequent stage of the receiver, the additional AC corner frequency being different from the AC corner frequency.

36. The electronic device of claim 35, wherein the subsequent stage of the receiver comprises a third chopper circuit, a fourth chopper circuit, and a second amplifier, the additional AC coupling circuit being disposed between the second amplifier and the fourth chopper circuit.

37. A transceiver, comprising: Multiple antennas; a transmitter coupled to the plurality of antennas; and a receiver coupled to the plurality of antennas and comprising a first group of chopper circuits, the first group of chopper circuits comprising a first chopper circuit and a second chopper circuit, a first amplifier, a first alternating current (AC) coupling circuit, and a second AC coupling circuit embedded between the first chopper circuit and the second chopper circuit, a second group of chopper circuits, the second group of chopper circuits comprising a third chopper circuit and a fourth chopper circuit, and A second amplifier, a third AC coupling circuit, and a fourth AC coupling circuit are embedded between the third chopper circuit and the fourth chopper circuit.

38. The transceiver of claim 37, wherein The output of the first chopper circuit is coupled to the input of the first AC coupling circuit, the output of the first AC coupling circuit is coupled to the differential input of the first amplifier, the differential output of the first amplifier is coupled to the input of the second AC coupling circuit, and An output of the second AC coupling circuit is coupled to the second chopper circuit.

39. The transceiver of claim 37, wherein The output of the third chopper circuit is coupled to the input of the third AC coupling circuit, the output of the third AC coupling circuit is coupled to the differential input of the second amplifier, the differential output of the second amplifier is coupled to the input of the fourth AC coupling circuit, and An output of the fourth AC coupling circuit is coupled to the fourth chopper circuit.

40. The transceiver of claim 37, wherein the first AC coupling circuit is configured to provide a first common-mode input voltage level, the second AC coupling circuit is configured to provide a second common-mode output voltage level to the first amplifier, the third AC coupling circuit is configured to provide a second common-mode input voltage level to the second amplifier, and the fourth AC coupling circuit is configured to provide a second common-mode output voltage level to the second amplifier.

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