A hardware link modeling method

Abstract

The application discloses a hardware link modeling method, wherein a total transfer function of a link is obtained through scattering parameters, a step response of the link is obtained through the transfer function, the response is stored in a lookup table, a jitter generation circuit is designed by using a hardware description language to obtain each jitter component injection value and then obtain a total jitter injection value, a link modeling circuit is designed by using the hardware description language to interpolate the step response with the total jitter injection value to complete total jitter injection and obtain a step response after jitter injection, a circuit for converting the step response into a pulse response is designed by using the hardware description language, and finally a pulse response after jitter injection is obtained to complete hardware circuit modeling of inter-symbol interference and jitter of the link. Hardware resource consumption of the application is far lower than that of a traditional algorithm.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of signal processing, and particularly relates to a link modeling method of hardware. BACKGROUND

[0002] With the rapid development of technologies such as artificial intelligence, cloud computing, big data and the Internet, high-throughput wired communication technology is the key to realizing the next generation of computing and communication systems. Due to the advantages of high transmission rate and low transmission delay, high-speed serial communication technology has become the mainstream technology in the field of wired high-speed communication.

[0003] Before SerDes (Serializer / Deserializer) chip tape-out, algorithm and system verification need to be performed in cooperation with simulation. Software simulation based on Python and the like has extremely low efficiency and does not support large-scale simulation applications. Hardware simulation based on field programmable logic gate array (FPGA) has an efficiency improvement of about several thousand times, and supports large-scale simulation applications. However, division, floating-point numbers and the like are difficult to implement in FPGA, and resource consumption is large. Therefore, how to model a simulation link in FPGA with low resource consumption, high precision and high resolution is a key problem of hardware simulation.

[0004] Factors to be considered for modeling a simulation link are inter symbol interference (ISI) and jitter. With the gradual increase of SerDes rate, the tolerance of jitter gradually becomes smaller, and its influence on the communication system becomes greater and greater. For example, if four-level pulse amplitude modulation (PAM-4) technology is used, in a 112 Gbps SerDes, the duration of 1 unit interval (UI) is 17.86 ps; in a 224 Gbps SerDes, the duration of 1 UI is 8.93 ps. The traditional link modeling method needs to consume a large amount of hardware resources to complete the injection of low-resolution (generally 1 / 32 UI) jitter, and it is difficult to meet the requirements of high-precision, high-resolution and scalable jitter injection, and it is also difficult to meet the requirements of high-speed and parallel SerDes hardware simulation.

[0005] Therefore, the existing modeling method still needs to be improved and developed. SUMMARY

[0006] To solve the above technical problems, the application provides a link modeling method of hardware, which is based on the advantages of low resource consumption, high precision and high resolution of FPGA to further improve the precision and efficiency of SerDes hardware simulation.

[0007] To achieve the above object, the application adopts the following technical scheme:

[0008] A link modeling method of hardware, the method comprising the following steps:

[0009] Step 1, scattering parameter (S parameter) files of a transmitting chip package, a channel and a receiving chip package are obtained respectively; the obtained S parameters are processed using a software language (such as Python) to obtain transfer functions of the transmitting chip package, the channel and the receiving chip package;

[0010] Step 2, the obtained transfer functions are processed using a software language (such as Python) to obtain a step response of a step signal after passing through the transmitting chip package, the channel and the receiving chip package, the step response containing parameter information of a signal modulation format, a signal baud rate, a signal sampling rate, a pre-cursor number of the step response, a post-cursor number of the step response, a quantization bit width of the step response and a bit width of a link input signal; the obtained step response is stored in a hardware lookup table;

[0011] Step 3, a hardware generation circuit of each jitter component is designed using a hardware description language (such as Chisel) to obtain an injection value of each jitter component;

[0012] Step 4, the injection values of each jitter component are summed using a hardware description language (such as Chisel) to obtain a total jitter injection value;

[0013] Step 5, the step response and the total jitter injection value are taken as inputs, a low resource consumption, high precision and high resolution jitter injection algorithm is completed on hardware by interpolation to obtain a step response after injecting jitter; the step responses after injecting jitter are subtracted to obtain a pulse response after injecting jitter, thereby completing modeling of inter-symbol interference and jitter of the link.

[0014] The application has the following beneficial effects:

[0015] The application can complete high-resolution jitter injection with low resource consumption, and the divisor in the calculation formula is 2^n, which can be converted into a shift operation on the hardware circuit. Therefore, the algorithm of the application can be implemented on the hardware circuit; the hardware resource consumption of the algorithm of the application is far lower than that of the traditional algorithm, and about 8 times, 4 times or 2 times can be saved according to the demand. With the gradual increase of the rate of high-speed serial communication, the subtle change of jitter will have a great influence on the system, and the high-resolution jitter injection method of the application has a wide application scenario. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The flow of the hardware link modeling method of the application is shown.

[0017] Figure 2 The schematic diagram of the mixed modulo two port network model is shown.

[0018] Figure 3 The schematic diagram of the step response modeling principle is shown.

[0019] Figure 4 The schematic diagram of the periodic jitter hardware generation technology principle is shown.

[0020] Figure 5 The schematic diagram of the duty cycle distortion hardware generation technology principle is shown.

[0021] Figure 6 The schematic diagram of the bounded uncorrelated jitter hardware generation technology principle is shown.

[0022] Figure 7 The schematic diagram of the relationship between the total jitter and each jitter component is shown.

[0023] Figure 8 The schematic diagram of the high-precision, low-resource consumption jitter injection technology of the application is shown.

[0024] Figure 9 The schematic diagram of the example test result of the application is shown. DETAILED DESCRIPTION

[0025] The application will be further described below in combination with the drawings and embodiments.

[0026] Figure 1 The flow of the hardware link modeling method of the application is shown, which mainly includes five steps: extracting S parameters; calculating the step response of the link; generating the injection value of each jitter component; obtaining the total jitter injection value; and link modeling. The specific process of each step will be described below.

[0027] Step 1, extracting S parameters to obtain a transfer function. Figure 2A hybrid two-port network model is shown, subscripts 1 and 2 represent the first physical port and the second physical port respectively, subscript 11 represents the first physical port to the first physical port, subscript 12 represents the first physical port to the second physical port, subscripts 21 and 22 are the same, define the differential mode incident wave, common mode incident wave, differential mode reflected wave and common mode reflected wave as 、 、 and , their relationship with the differential mode S parameter , the common mode S parameter , the cross mode S parameter and is:

[0028] (1)

[0029] In the case of only using differential signal transmission, only the differential mode S parameter is generally considered:

[0030] (2)

[0031] Therefore, formula (1) can be simplified as:

[0032] (3)

[0033] In general, the actual circuit design will meet the conjugate matching. Therefore, according to the following formula, the transfer function can be obtained by S parameter.

[0034] (4)

[0035] Where, is the reference impedance, is the source impedance, is the load impedance, is the source reflection coefficient, is the load reflection coefficient, is the input reflection coefficient.

[0036] According to the above process, the scattering parameter, that is, the S parameter file of the sending end chip package, the channel and the receiving end chip package, three transfer functions can be obtained, and the total transfer function of the link can be obtained by multiplying the three transfer functions in the frequency domain using Python and other software languages .

[0037] Step 2 yields the link's step response. Traditional methods model inter-symbol interference by convolving the impulse response with the input signal, but this requires significant hardware resources to achieve low-precision jitter injection, making it unsuitable for current needs. Traditional methods calculate the impulse responses corresponding to all possible jitter values ​​using software and store them in the hardware circuit as lookup tables. Improving resolution or jitter injection range requires increasing hardware resource consumption, and this approach lacks scalability, hindering parallelized SerDes hardware simulation design.

[0038] This invention uses step response instead of impulse response for link modeling, laying the foundation for subsequent high-precision, high-resolution jitter injection algorithms. The principle of step response modeling is as follows: Figure 3 As shown in the diagram, this schematic only considers inter-symbol interference modeling and not jitter modeling. The first step signal 1 and the second step signal 2 differ by one unit time interval on the time axis; subtracting them yields a pulse signal. Similarly, the first step response 3 and the second step response 4 differ by one unit time interval on the time axis; subtracting them yields the corresponding pulse response. Using this relationship, the translation of the first step signal 1 and the second step signal 2 on the time axis represents signal jitter. Correspondingly, the first step response 3 and the second step response 4 are translated along the same time axis, thus obtaining a pulse response injected with a certain jitter value.

[0039] The parameters required to generate the step response of the link using a software language (such as Python) are: signal modulation format, signal baud rate, signal sampling rate, number of pre-cursors in the step response, number of post-cursors in the step response, quantization bit width of the step response, and bit width of the link input signal. First, generate a step signal using the software language based on the above parameters; second, transform this time-domain step signal to the frequency domain using the Fast Fourier Transform (FFT) function of the software language; third, use the software language to convert the overall link transfer function obtained in step one... The signal is multiplied with the step signal transformed to the frequency domain; fourth, the multiplied signal is transformed to the time domain using the Inverse Fast Fourier Transform (IFFT) function in the software language, thereby obtaining the step response of the link.

[0040] Step 3: Obtain the injection values ​​for each jitter component. To meet the requirements of efficient, real-time jitter injection, this step needs to be completed in hardware circuitry. The jitter components considered in this invention include periodic jitter (PJ), duty cycle distortion (DCD), bounded uncorrelated jitter (BUJ), and random jitter (RJ).

[0041] There are three types of periodic jitter: sine waves, triangular waves, and square waves. The probability density functions for these three types of periodic jitter are as follows:

[0042] (5)

[0043] in, The peak value of the periodic jitter. Figure 4 A schematic diagram of the periodic jitter generation technology is shown, in which and These represent the clock frequency and the frequency of the periodic jitter, respectively. Based on the initial parameters and probability density function, a lookup table for each type of periodic jitter can be obtained using a Python script. This lookup table is stored in Random Access Memory (RAM), and a counter generates the read address for each RAM location. The obtained RAM read data represents the generated PJ values ​​for the three types. Only one type of periodic jitter can be injected at a time; therefore, a select signal is needed to select the current periodic jitter type. If a transition edge (low-high or high-low) exists, the value of the periodic jitter selected by the select signal is output; otherwise, 0 is output.

[0044] Duty cycle distortion refers to a type of data correlation jitter where the ratio of the high-level duration to the low-level duration of a pulse deviates from its ideal value. Its probability density function is:

[0045] (6)

[0046] in, This represents the peak value of DCD jitter. Figure 5 The diagram illustrates the DCD jitter generation technology, which demonstrates how hardware jitter generation can be achieved by controlling the presence or absence of a transition edge and its direction (low-high or high-low).

[0047] The probability density function of uniformly distributed bounded uncorrelated jitter is shown in equation (7), where, This represents the peak value of BUJ. Figure 6This diagram illustrates a uniformly distributed BUJ generation technique. A lookup table for the BUJ can be obtained using a Python script based on initial parameters. This lookup table is stored in RAM at a depth of ramDepth. A uniformly distributed random number is generated using a Uniform Random Number Generator (URNG) as the read address for RAM, ranging from 0 to ramDepth-1. The obtained RAM read data is the generated BUJ value. If a transition edge (low-high or high-low) exists, the generated BUJ value is output; otherwise, 0 is output.

[0048] (7)

[0049] The probability density function of random fluctuations is shown in equation (8), where, Standard deviation The mean is used. The RJ generation technique is the same as the hardware Gaussian Random Number Generator (GRNG), and there are many publicly available, efficient architectures for the GRNG technique that can be directly adopted.

[0050] (8)

[0051] Step 4: Obtain the total jitter injection value. A jitter subdivision model can help to understand the impact of each jitter component on the high-speed serial communication system, but when injecting jitter, it is only necessary to obtain the total jitter injection value composed of the sum of each subdivision jitter component. This total jitter injection value is used to complete the jitter injection model of the link.

[0052] The relationship between total jitter and subdivision jitter is a linear summation, such as... Figure 7 As shown, this invention only considers periodic jitter, duty cycle distortion, bounded uncorrelated jitter, and random jitter in its examples, but other subdivisions of jitter can also be injected using the same method. The total jitter value can be obtained by summing all subdivisions in the hardware.

[0053] Step 5, Link Modeling. Following the steps outlined in Step 2, obtaining the step response and total jitter injection value of a link allows for the modeling of inter-symbol interference and jitter for that link. For example... Figure 3As shown, the impulse response after jitter injection can be obtained by shifting the step response along the time axis. For inter-symbol interference modeling, this can be accomplished by subtracting the two step responses shifted along the time axis; however, for jitter modeling, it is necessary to consider how to transform the time information on the horizontal axis into information that the FPGA can process in a hardware system such as an FPGA. Therefore, the key and difficult point of this step lies in jitter modeling, that is, how to implement a low-resource-consumption, high-precision, and high-resolution FPGA jitter injection algorithm.

[0054] In traditional solutions, due to hardware resource limitations, the oversampling factor is generally set to 32 times, so the jitter resolution is 1 / 32 UI. Figure 8 The following is a schematic diagram illustrating the low-resource-consumption, high-precision, and high-resolution jitter injection algorithm of the present invention, using 4x oversampling as an example.

[0055] First, let's explain how the method of this invention achieves low resource consumption. Traditional methods can only increase the oversampling factor to improve jitter resolution, such as oversampling by 32 times. The Nyquist-Shannon sampling theorem states that to recover a signal without distortion, the sampling frequency needs to be greater than or equal to twice the signal bandwidth. This sampling theorem can be understood in another way: when a continuous signal is converted into a discrete signal through sampling, and then the discrete signal is restored to a continuous signal, the fidelity of the result depends on the sampling frequency. Oversampling by 4, 8, or 16 times already includes all the frequency domain information that the link can express, satisfying the requirements of the sampling theorem, allowing the continuous signal to be recovered from the discrete signal. Therefore, the necessity of oversampling by 32 times is greatly reduced. Setting the oversampling factor to 4, 8, or 16 times correspondingly reduces resource consumption by approximately 8, 4, or 2 times compared to traditional methods. According to traditional methods, reducing the oversampling factor will reduce jitter resolution. Although the oversampling factor is reduced, this invention uses interpolation to improve jitter resolution.

[0056] Secondly, this invention explains how it achieves high-resolution jitter injection. Oversampling by a factor of 4 can encompass all the frequency domain information that a given link can represent. The improved accuracy of jitter modeling is achieved through interpolation, such as linear interpolation and sinc interpolation. Figure 8 The high-resolution jitter injection algorithm is illustrated using linear interpolation as an example. (Figure 1) and These are the voltage values ​​(amplitude values) at the two transition edges. Jitter is defined as the difference between the actual edge time and the ideal edge time. For example... Figure 8As shown, point A-point B is the ideal edge. If the total jitter injection value is 0.1UI to the right, then the edge of point A-point B is shifted to the right by 0.1UI. The intersection of the shifted edge and the vertical dashed line passing through point B is point C. This point C is the new sampling point after jitter injection. Point C is used to replace point B, that is, the vertical axis amplitude value of the sampling point is changed to complete the horizontal axis jitter injection. Therefore, the signal edge after jitter injection is point A-point C. Equation (9) shows the formula for calculating the amplitude of point C, where , and These are the voltage values ​​(amplitude values) at points A, B, and C, respectively. The maximum value for dithering injection is a positive integer, related to the dithering injection resolution. It's also used to quantize decimals like 0.25 and 0.1 into integers within the FPGA, and needs to be set to 2^n, such as 1024. Therefore, the dithering resolution is 1 / 4096 UI. Although this formula involves division, its divisor is always 2^n, so the division can be converted into a shift operation in hardware.

[0057] (9)

[0058] Interpolate the step response at the current moment based on the total jitter injection value to complete the jitter injection for that edge, obtaining the step response after jitter injection. Subtract the two step responses after jitter injection to obtain the impulse response after jitter injection, thus completing the inter-symbol interference and jitter modeling of the link.

[0059] Finally, the high-precision performance of the method of the present invention is demonstrated by actual test results. Figure 9 The test results of the low-resource-consumption, high-precision, and high-resolution hardware link modeling method described in this invention are presented. Figure 9 The existing algorithm mentioned is a high-precision software jitter injection algorithm proposed by Wu Tong in his doctoral dissertation, "Research on Key Technologies of Jitter in High-Speed ​​Serial Communication Signals." However, this algorithm involves arbitrary floating-point division, which is difficult to implement in hardware, and testing showed that its accuracy was low. As can be seen from the figure, the sampling points of the algorithm proposed in this invention basically overlap with the control group after jitter injection, while the existing algorithm deviates significantly from the control group. Table 1 shows... Figure 9 Medium local magnification Figure 4 Specific data and relative errors for each point.

[0060] Table 1

[0061]

[0062] As can be seen from Table 1, the algorithm proposed in this invention is highly consistent with the control group, with relative errors of 0.00%, 0.00%, 0.00% and 0.26%, respectively. In contrast, the existing algorithms deviate significantly from the control group, with relative errors of 1.23%, 0.97%, 0.74% and 0.79%, respectively.

[0063] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method of link modeling of hardware, characterized by, The method comprises the following steps: Step 1, respectively obtaining scattering parameter files of a transmitting chip package, a channel and a receiving chip package; processing the obtained scattering parameters to obtain transfer functions of the transmitting chip package, the channel and the receiving chip package; Step 2, processing the obtained transfer functions to obtain a step signal after the step signal respectively passes through the transmitting chip package, the channel and the receiving chip package, and storing a step response obtained after the step signal passes through the transmitting chip package, the channel and the receiving chip package in a hardware lookup table; Step 3, using a hardware description language to design hardware generation circuits of each jitter component to obtain injection values of each jitter component; Step 4, using a hardware description language to sum the injection values of each jitter component to obtain a total jitter injection value; Step 5, taking the step response and the total jitter injection value as inputs, completing a jitter injection algorithm on hardware through interpolation to obtain a step response after jitter injection; subtracting the two step responses after jitter injection to obtain a pulse response after jitter injection, and completing modeling of inter-symbol interference and jitter of the link.

2. The method of claim 1, wherein, In the step 1, scattering parameter files of the transmitting chip package, the channel and the receiving chip package are processed respectively to obtain three transfer functions corresponding to the transmitting chip package, the channel and the receiving chip package, and the three transfer functions are multiplied in the frequency domain to obtain a total transfer function of the link.

3. The method of claim 2, wherein, Parameter information required for generating the step response in the step 2 includes a signal modulation format, a signal baud rate, a signal sampling rate, a number of front cursors of the step response, a number of rear cursors of the step response, a quantization bit width of the step response and a bit width of a link input signal.

4. The method of claim 3, wherein, The step of obtaining the step response in the step 2 is as follows: Step 2.1, generating a time-domain step signal according to the parameter information; Step 2.2, transforming the time-domain step signal to the frequency domain by using a fast Fourier transform function; Step 2.3, multiplying the total transfer function of the link and the step signal transformed to the frequency domain; Step 2.4, transforming the multiplied signal to the time domain by using an inverse fast Fourier transform function to obtain the step response of the link.

5. The method of claim 4, wherein, The jitter components in the step 3 include periodic jitter, duty cycle distortion, bounded uncorrelated jitter and random jitter.

6. The method of claim 5, wherein, The periodic jitter includes sine wave jitter, triangular wave jitter and square wave jitter.

7. The method of claim 6, wherein, In the step 3, a probability density function of each jitter component is calculated, and a hardware generation circuit of each jitter component is designed according to the probability density function.

8. The method of claim 7, wherein, The summing manner in the step 4 is linear summing.

9. The method of claim 8, wherein, The interpolation manner of the step 5 includes linear interpolation and sinc interpolation; a maximum value of the total jitter injection value is related to a jitter injection resolution, and is set to 2^n, and is a positive integer.

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