Dual-clock Co-synchronization Method in Wireless Communication Based on Single-Photon Counting

Abstract

This invention discloses a dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection, comprising: setting up N parallel-operating gated clocks and one high-frequency clock at the receiving end, wherein each gated clock is equipped with an independent counter; the counter Cnt i (i∈[1,N]) in the gated clock Clk i (i∈[1,N]), the electrical pulses output by the single-photon detector, and the high-frequency clock Clk h Counting is performed under the control of the counter Cnt; i After counting for M (M≥1) count cycles, the counter Cnt... i Stop counting and output a count value Count. i This method compares the relative magnitudes of the N count values ​​output by N counters and uses the gate clock corresponding to the maximum count value as the synchronization clock. This approach achieves fast, high-precision clock synchronization, and the synchronization accuracy increases with the number of gate clocks N.

Description

Technical Field

[0001] This invention relates to the field of single-photon wireless communication and detection, and specifically to the field of high-precision clock synchronization with single-photon time resolution, and more specifically to a dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection. Background Technology

[0002] Single-photon counting detection is a light intensity detection technology with single-photon-limited sensitivity. Its principle is that when a weak light signal is incident on a single-photon detector, the detector outputs a discrete sequence of pulses. Each pulse represents the detection of one photon. The intensity of the incident light signal is represented by the density (count rate) of the output pulse signal, rather than the amplitude. Single-photon counting detection is one of the key technologies for wireless optical communication in high-attenuation scenarios such as deep space and underwater. Research shows that, due to the influence of afterpulse, dead time, and dark counting effects, the pulse output waveform of a single-photon detector differs significantly from and has typical characteristics of the output waveforms based on photodiodes (PDs) and avalanche photodiodes (APDs). These differences present new challenges for the design of wireless optical communication systems based on single-photon detectors. In particular, single-photon detection relies on precise single-photon counting, with a time resolution reaching the picosecond level. This means that compared to traditional PD or APD-based optical communication systems, wireless communication based on single-photon detection requires higher-precision clock synchronization to achieve data demodulation. Meanwhile, since single-photon detection outputs discrete electrical pulses and is subject to strong shot noise during photon detection, the key to ensuring reliable communication on extremely weak optical links is how to extract clock synchronization signals from these discrete electrical pulses.

[0003] Traditional single-photon clock synchronization methods count the number of electrical pulses output by the detector during the high-level time slot of the gated clock. However, this counting method may result in the same count between two adjacent gated clocks, leading to synchronization clock extraction errors and affecting system performance. Therefore, designing a high-precision clock synchronization method that meets the wireless communication requirements based on single-photon detection and fully exploring the potential of single-photon detection technology is a prerequisite and foundation for achieving robust single-photon counting communication. Summary of the Invention

[0004] To address the aforementioned problems, this invention innovatively proposes a dual-clock cooperative synchronization method for wireless communication based on single-photon counting detection. When a weak light wave signal illuminates a single-photon detector, the detector outputs discrete electrical pulse signals. By processing these discrete electrical pulse signals using the dual-clock cooperative synchronization method of this invention, high-precision clock synchronization of the single-photon counter can be achieved.

[0005] The technical solution for achieving the objective of this invention is as follows:

[0006] Dual-clock cooperative synchronization methods in wireless communication based on single-photon counting detection include:

[0007] At the receiving end, set N (N≥2) gated clocks Clk1, Clk2, ..., Clk for parallel operation. N and a high-frequency clock Clk h Each gated clock has the same frequency as the transmitting clock frequency f1, and the phase difference between two adjacent gated clocks is... Each gated clock is equipped with an independent counter Cnt1, Cnt2, ..., Cnt N ;

[0008] When the gated clock Clk i When (i∈[1,N]) is high, the electrical pulse output by the single-photon detector after responding to the weak light signal is used as the counter Cnt. i The enable signal, and simultaneously, the high-frequency clock Clk. h As a counter Cnt i The counter Cnt is started when the enable signal is present. i And in each high-frequency clock Clk h When the rising edge of the pulse arrives, the counter Cnt is triggered. i Count once; when the gated clock Clk i When the level is low, the counter Cnt is paused. i Count until the next gated clock cycle (Clk). i When a high level is reached, the counter Cnt... i Continue counting;

[0009] Gated clock Clk i One clock cycle of (i∈[1,N]) is used as the counter Cnt i (i∈[1,N]) is a counting cycle when the counter Cnt i After counting for M (M≥1) count cycles, the counter Cnt... i Output a count value Count i (i∈[1,N]); Compare Count1, Count2, ..., Count N Based on the relative magnitudes, select the maximum count value and use the gated clock corresponding to the maximum count value as the synchronization clock.

[0010] Using this method, the clock synchronization accuracy of the receiving end can reach [percentage missing].

[0011] The specific technical solution of the present invention is as follows:

[0012] The dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection includes the following steps:

[0013] S1, at the receiving end, N independent and parallel gated clocks are set. The frequency of each gated clock is the same as the clock frequency at the transmitting end, f1, and the phase difference between two adjacent gated clocks is Δθ. And N≥2;

[0014] S2 sets a corresponding counter Cnt1, Cnt2, ..., Cnt for each of the N gated clocks. N ;

[0015] S3, Set a high-frequency clock channel Clk h Its clock period is T1, the time slot width of the minimum electrical pulse output by the single-photon detector is T2, nT1<T2, and n takes an integer greater than or equal to 2;

[0016] S4, when the gated clock Clk i When (i∈[1,N]) is high, the electrical pulse output by the single-photon detector after responding to the weak light signal is used as the counter Cnt. i The enable signal; simultaneously, the high-frequency clock Clk. h As a counter Cnt i The counter Cnt is started when the enable signal is present. i And in each high-frequency clock Clk h Trigger counter Cnt i At that time, the counter Cnt i Then count once, and when the gate clock Cnt... i When it is low, the counter Cnt i Pause counting until the gated clock Clk i The voltage level is high, and at this time the single-photon detector outputs an electrical pulse, and the counter Cnt... i Continue counting;

[0017] S5, gate clock Clk i One clock cycle of (i∈[1,N]) is used as the counter Cnt i (i∈[1,N]) is a counting cycle when the counter Cnt i After counting for M (M≥1) count cycles, the counter Cnt... i Output a count value Count i Compare N count values: Count1, Count2, ..., Count3. NBased on the relative magnitudes, the maximum count value is selected, and the gate clock corresponding to the maximum count value is used as the synchronization clock. At this point, clock synchronization is complete.

[0018] Technical features and significant effects of the present invention:

[0019] (1) High-precision clock synchronization: Through the multi-channel gated clock and counter mechanism, the present invention can achieve high-precision clock synchronization, and the synchronization accuracy is proportional to the number of gated clocks N. The larger N is, the higher the clock synchronization accuracy.

[0020] (2) Fast clock synchronization: This invention sets up multiple counters in parallel and uses a comparator to quickly select the best synchronization clock, ensuring that the clock synchronization process is fast and efficient, reducing the delay problem in traditional synchronization methods. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the system block diagram according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of a single-photon detector outputting discrete electrical pulses in response to a weak light signal in an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram illustrating clock synchronization using a gated clock and a high-frequency counting clock in an embodiment of the present invention;

[0024] Figure 4 It is about Figure 3 Medium counter Cnt i In the gated clock Clk i A magnified view showing the counting process under the combined control of electrical pulse signals;

[0025] Figure 5 The counter Cnt in this embodiment of the invention i A schematic diagram of the counting method (i∈[1,N]).

[0026] In the diagram, 1. First computer; 2. Transmitter; 2-1. Encoder modulator; 2-2. Framer; 3. Laser driver module; 4. Laser; 5. Collimating lens; 6. Channel; 7. Convex lens; 8. Narrowband filter; 9. Single-photon detector; 10. Receiver; 10-1. Gated clock generator; 10-2. Counter; 10-3. Comparator; 11. Second computer. Detailed Implementation

[0027] The present invention will be further described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Example:

[0029] like Figure 1 As shown, an operable embodiment of the dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection includes two parts: a transmitter and a receiver.

[0030] The transmitting end includes a first computer 1, a transmitter 2, a laser driving module 3, a laser 4, and a collimating lens 5;

[0031] The first computer 1, transmitter 2, laser drive module 3 and laser 4 are connected in sequence. Collimating lens 5 is placed in front of laser 4. The laser emitted by laser 4 passes through collimating lens 5 to reach channel 6.

[0032] The transmitter 2 includes an encoding modulator 2-1 and a framer 2-2, with the encoding modulator 2-1 connected to the framer 2-2; the encoding modulator 2-1 is connected to the first computer 1, and the framer 2-2 is connected to the laser driving module 3;

[0033] The receiving end includes a convex lens 7, a narrowband filter 8, a single-photon detector 9, a receiver 10, and a second computer 11;

[0034] The single-photon detector 9, receiver 10, and second computer 11 are connected in sequence. The narrow-band filter 8 is disposed in front of the single-photon detector 9, and the convex lens 7 is disposed in front of the narrow-band filter 8. The convex lens 7 corresponds to the channel 6.

[0035] The receiver 10 includes a gated clock generator 10-1, N (N≥2) counters 10-2 and N (N≥2) comparators 10-3 connected in sequence; the single-photon detector 9 is connected to the gated clock generator 10-1 and the comparators 10-3 are connected to the second computer 11.

[0036] The weak light signal arriving through channel 6 is focused by convex lens 7, then passes through narrowband filter 8, and arrives at single-photon detector 9. Single-photon detector 9 outputs discrete pulse signals and sends them to receiver 10 for processing.

[0037] The specific steps of the receiving end in the embodiment are as follows:

[0038] like Figure 1 Figure 2 As shown, photon counting detection is a light intensity detection technology with single-photon limited sensitivity. Its principle is that the light signal sent by laser 4 becomes a weak light signal after passing through channel 6 and illuminates the single-photon detector 9. After receiving the weak light signal, the single-photon detector 9 outputs discrete electrical pulses.

[0039] The dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection includes the following steps:

[0040] S1), such as Figure 3 Figure 4 As shown, N independent and parallel gated clocks are set at the receiving end. The frequency of each gated clock is the same as the clock frequency at the transmitting end, f1, and the phase difference between two adjacent gated clocks is Δθ. Furthermore, in the diagram, N=30, and the gated clocks for the 30 parallel operations use Clk1, Clk2, ..., Clk respectively. 30 express;

[0041] S2), each of the 30 gated clock channels is assigned a corresponding counter Cnt1, Cnt2, ..., Cnt. 30 ;

[0042] S3), set a high-frequency clock Clk. h Its clock period is T1, T1 = 4ns, and the time slot width of the minimum electrical pulse output by the single-photon detector is T2, T2 = 10ns;

[0043] S4), such as Figure 5 As shown, the gated clock Clk is illustrated in detail. i The counter Cnt corresponding to (i∈[1,30]) i The counting method for (i∈[1,30]): when the gated clock Clk i When (i∈[1,30]) is high, the electrical pulse output by the single-photon detector after responding to the weak light signal is used as the counter Cnt. i The enable signal, and simultaneously, the high-frequency clock Clk. h As a counter Cnt i The counting signal, even when the enable signal is present, turns on the counter Cnt. i And the counter Cnt is triggered every time a high-frequency clock is used. i At that time, the counter Cnt i Then count once, when the gate clock Clk i When it is low, the counter Cnt i Pause counting until the gated clock Clk i The voltage level is high, and at this time the single-photon detector outputs an electrical pulse, and the counter Cnt... i Continue counting;

[0044] S5), such as Figures 3-5 As shown, the counter Cnt is displayed in detail. i (i∈[1,30]) Output count value method: gate clock Clk iOne clock cycle of (i∈[1,30]) is used as the counter Cnt i One counting cycle, when the counter Cnt i After counting for M cycles, the counter Cnt... i Output a count value Count i (i∈[1,30]), Figure 2 M=4, Figure 3 Medium counter Cnt i m counting cycles have been performed;

[0045] like Figures 3-4 As shown, the counter Cnt i The four counting cycles of (i∈[1,30]) are respectively used with Cnt i _1、Cnt i _2、……、Cnt i _4 represents the counters Cnt1, Cnt2, ..., Cnt 30 The output count values ​​are Count1 = 33, Count2 = 21, Count3 = 15, ..., Count... 30 =26;

[0046] like Figures 3-4 As shown, a comparator is used to compare Count1, Count2, ..., Count. 30 The relative magnitudes are used to select the maximum count value, and the gate clock corresponding to the maximum count value is used as the synchronization clock.

[0047] At this point, clock synchronization is complete.

[0048] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection, characterized in that, Includes the following steps: S1, at the receiving end, N independent and parallel gated clocks are set. The frequency of each gated clock is the same as the clock frequency at the transmitting end, f1, and the phase difference between two adjacent gated clocks is Δθ. And N≥2; S2 provides a corresponding counter unit Cnt1, Cnt2, ..., Cnt for each of the N gated clocks. N ; S3, Set a high-frequency clock channel Clk h Its clock period is T1, the time slot width of the minimum electrical pulse output by the single-photon detector is T2, nT1<T2, and n takes an integer greater than or equal to 2; S4, when the gated clock Clk i When (i∈[1,N]) is high, the electrical pulse output by the single-photon detector after responding to the weak light signal is used as the counter Cnt. i The enable signal; simultaneously, the high-frequency clock Clk. h As a counter Cnt i The counter Cnt is started when the enable signal is present. i And in each high-frequency clock Clk h Trigger counter Cnt i At that time, the counter Cnt i Then count once, and when the gate clock Clk... i When it is low, the counter Cnt i Pause counting until the gated clock Clk i The voltage level is high, and at this time the single-photon detector outputs an electrical pulse, and the counter Cnt... i Continue counting; S5, gate clock Clk i One clock cycle of (i∈[1,N]) is used as the counter Cnt i (i∈[1,N]) is a counting cycle when the counter Cnt i After counting for M (M≥1) count cycles, the counter Cnt... i Output a count value Count i Compare N count values: Count1, Count2, ..., Count3. N Based on the relative magnitudes, select the maximum count value and use the gated clock corresponding to the maximum count value as the synchronization clock.

Images