Chip testing methods, apparatus, and testing machines for asynchronous half-duplex communication protocols

Abstract

This application relates to the field of chip testing technology and discloses a chip testing method for asynchronous half-duplex communication protocols. The method includes: sending test commands and standard duration signals to the chip when it is powered on to calculate the deviation ratios between internal clock signals and external clock signals at multiple levels; wherein, the internal clock signals at different levels correspond one-to-one with the deviation ratios; sampling the standard duration signal using the internal clock to obtain deviation data for dynamic calibration; comparing the signal sampling results of multiple external input protocol frames with the expected deviation results to obtain multiple sets of calculated deviation values, and calculating an average deviation value based on this data; wherein, the multiple deviation values ​​are the deviation values ​​of a single protocol frame obtained from each comparison; and calculating a correction value for the clock deviation to calibrate the clock deviation based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signal. This method can calibrate clock deviations during chip testing.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and for example to a chip testing method and apparatus, and a testing machine for asynchronous half-duplex communication protocols. Background Technology

[0002] The tape-out and testing of a digital SoC (System on Chip) is a complete process from design specification definition to final product verification, encompassing key steps such as architecture design, hardware design, software design, integration testing, physical design, tape-out and packaging, and system verification and optimization. In this process, engineers need to perform detailed simulation testing, select appropriate functional modules, write software programs, conduct system-level testing, optimize circuit design, and ultimately transform the design into an actual semiconductor chip.

[0003] To achieve SoC simulation testing, related technologies disclose a method for synchronously testing chips using an external clock input. This method includes: generating patterns usable by the test equipment for test items at different clock frequencies; and the test equipment performing corresponding chip test item checks based on the patterns. The test equipment inputs a synchronous clock and communication interaction signals to the test chip, dividing the communication process signals into fixed-interval test points using the external clock. The test equipment receives feedback signals from the chip and compares the test points with the patterns to determine the test results.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] During the transmission of asynchronous half-duplex communication protocols, the protocol itself does not have a synchronous clock signal. The chip needs to operate based on its internal clock to complete communication processing. When the chip's internal clock signal undergoes frequency conversion processing or temperature drift occurs, the time base may change, resulting in clock deviation and making it impossible to test the chip's asynchronous half-duplex communication protocol. In addition, clock deviation may cause preset patterns to be unsuitable for large-scale chip testing. To reduce the impact of clock deviation on testing, engineers need to adjust the patterns one by one.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a chip testing method, apparatus, and testing machine for asynchronous half-duplex communication protocols, which can calibrate clock deviations when testing chips for asynchronous half-duplex communication protocols.

[0009] In some embodiments, the chip testing method for an asynchronous half-duplex communication protocol includes: sending a test command and a standard duration signal to the chip when the chip is powered on, to calculate the deviation ratios of internal clock signals and external clock signals at multiple levels; wherein the internal clock signals at multiple levels correspond one-to-one with multiple deviation ratios; sampling the standard duration signal using the internal clock to obtain deviation data for dynamic calibration; comparing the sampling results of multiple sets of externally input protocol frame signals with the expected deviation results to obtain multiple deviation values, and iteratively calculating the average deviation value; wherein the multiple deviation values ​​are single protocol frame deviation values ​​obtained in each comparison; and calculating a clock deviation correction value to calibrate the clock deviation based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signal.

[0010] Optionally, calculating the average deviation value based on the deviation values ​​includes: calculating the total number of deviations sequentially based on multiple deviation values; and calculating the average deviation value when the total number of deviations exceeds the upper limit of the number of times.

[0011] Optionally, the total number of deviations is calculated sequentially based on multiple deviation values. The deviation data includes the maximum allowable range and the reasonable threshold range, including: if the current deviation value exceeds the allowable range, determining whether the current deviation value exceeds the reasonable threshold range; if the current deviation value exceeds the reasonable threshold range, determining the direction of the current deviation value exceeding the limit; and calculating the total number of deviations based on the direction of the exceeding limit.

[0012] Optionally, the total number of deviations is calculated based on the direction of the deviation exceeding the limit, including: increasing the total number of deviations by 1 when the current deviation value is a positive deviation; and decreasing the total number of deviations by 1 when the current deviation value is a negative deviation.

[0013] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: adjusting the maximum limit of the deviation value when the current deviation value does not exceed the allowable range.

[0014] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: adjusting a reasonable threshold range for the deviation value when the total number of deviations exceeds the upper limit of the number of tests.

[0015] Optionally, a correction value for the clock skew is calculated to calibrate the clock skew based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signal, including calculating the correction value according to the following formula:

[0016] Ut =K gp ×(e t +D td )

[0017] Among them, U t K is the correction value for clock skew. gp e represents the deviation ratio. t D is the internal count value of the protocol frame signal. td This represents the average deviation value.

[0018] Optionally, calculating the deviation ratio between the internal clock signal and the external clock signal includes: performing frequency division processing on the internal clock signal to obtain a frequency-divided clock signal; counting the duration of the standard duration signal based on the frequency-divided clock signal and the external clock signal, respectively; and calculating the deviation ratio based on the counting results.

[0019] In some embodiments, the chip testing apparatus for an asynchronous half-duplex communication protocol includes a processor and a memory storing program instructions, wherein the processor is configured to execute the chip testing method for an asynchronous half-duplex communication protocol as described above when running the program instructions.

[0020] In some embodiments, the test equipment includes: a test equipment body; and a chip testing device for an asynchronous half-duplex communication protocol, as described above, installed on the test equipment body.

[0021] The chip testing method, apparatus, and testing machine for asynchronous half-duplex communication protocols provided in this disclosure can achieve the following technical effects:

[0022] In this embodiment, the deviation ratio is calculated for internal calibration counting results. Multiple externally input protocol frame signals are sampled to calculate the average deviation value. Finally, based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signals, a clock deviation correction value is calculated. This correction value achieves clock deviation calibration, solving the problem of communication timing mismatch with the test equipment caused by clock deviation in asynchronous half-duplex communication protocols. This enables large-scale testing feasibility of the chip's asynchronous half-duplex communication protocol. Simultaneously, it avoids the need for manual debugging during testing due to clock deviation, reducing manual debugging time and significantly improving testing efficiency.

[0023] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0025] Figure 1 This is a schematic diagram of the implementation environment for the chip testing method for asynchronous half-duplex communication protocol provided in the embodiments of this disclosure;

[0026] Figure 2 This is a schematic diagram of a chip testing method for an asynchronous half-duplex communication protocol provided in an embodiment of this disclosure;

[0027] Figure 3 This is a schematic diagram of another chip testing method for an asynchronous half-duplex communication protocol provided in an embodiment of this disclosure;

[0028] Figure 4 This is a schematic diagram of another chip testing method for an asynchronous half-duplex communication protocol provided in this disclosure embodiment;

[0029] Figure 5 This is a schematic diagram illustrating the calculation of the average deviation value according to an embodiment of this disclosure;

[0030] Figure 6 This is a schematic diagram of a chip testing device for an asynchronous half-duplex communication protocol provided in an embodiment of this disclosure. Detailed Implementation

[0031] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0032] The terms "first," "second," etc., used in the technical solutions described in this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0033] Unless otherwise stated, the term "multiple" means two or more.

[0034] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0035] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0036] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0037] Currently, system-on-a-chip testing requires testing asynchronous half-duplex communication protocols in the CP (Chip-Probing) and FT (Functional Test) stages. Compared to related technologies that use external clock sources to assist in testing, the embodiments of this disclosure calibrate the chip output signal through dynamic calibration to address standard clock deviation and clock temperature drift deviation.

[0038] Figure 1 This is a schematic diagram illustrating the implementation environment of the chip testing method for the asynchronous half-duplex communication protocol provided in this embodiment of the disclosure. Figure 1 As shown, the implementation environment may include a test instrument 100 and a test chip 200. The test chip includes a clock comparison module 201, a dynamic calibration module 202, and a communication module 203.

[0039] The testing equipment 100 can send preset commands to cause the testing chip 200 to execute clock calibration test procedures. The testing equipment 100 sends a test command, the testing chip 200 recognizes the command and enters the corresponding test procedure. The clock comparison module 201 counts the duration of the standard duration signal sent by the testing equipment 100 based on internal and external clock signals, obtains the difference between the internal and external clock signals, and calculates the deviation ratio between the internal and external clock signals. The dynamic calibration module 202 calculates the average deviation value based on the sampling results of the protocol frame signal and the expected deviation result. The communication module 203 inputs the internal count value of the protocol frame signal into the dynamic calibration module 202, so that the dynamic calibration module 202 calculates the clock deviation correction value based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signal to calibrate the clock deviation.

[0040] Combination Figure 2 As shown, this disclosure provides a chip testing method for an asynchronous half-duplex communication protocol, including:

[0041] S201, when the chip is powered on, the test equipment sends test commands and standard duration signals to the chip, so that the test chip can calculate the deviation ratio between the internal clock signal and the external clock signal for multiple ranges; wherein, the internal clock signal for multiple ranges corresponds one-to-one with multiple deviation ratios.

[0042] S202, the test chip uses an internal clock to sample a standard duration signal to obtain deviation data for dynamic calibration.

[0043] S203, the test equipment will control the output of multiple sets of protocol frame signals to excite through instructions. The test chip receives the instructions and compares the sampling results of the external excitation with the expected deviation results to obtain multiple deviation values, and iterates the deviation values ​​to calculate the average deviation value; among them, the multiple deviation values ​​are the single protocol frame deviation values ​​obtained in each comparison.

[0044] S204, the test chip calculates the clock deviation correction value to calibrate the clock deviation based on the deviation ratio, average deviation value, and internal count value of the protocol frame signal.

[0045] The chip testing method for asynchronous half-duplex communication protocols provided in this disclosure calculates a deviation ratio for internal calibration counting results. Multiple externally input protocol frame signals are sampled to calculate an average deviation value. Finally, a clock deviation correction value is calculated based on the deviation ratio, average deviation value, and internal count value of the protocol frame signals. This correction value calibrates the clock deviation, solving the problem of communication timing mismatch with the test equipment caused by clock deviation in asynchronous half-duplex communication protocols. This enables large-scale testing of asynchronous half-duplex communication protocols for chips. Simultaneously, it avoids the need for manual debugging during testing due to clock deviation, reducing manual debugging time and significantly improving testing efficiency.

[0046] Optionally, calculating the average deviation value based on multiple deviation values ​​includes: sequentially calculating the total number of deviations based on the multiple deviation values; and, if the total number of deviations is greater than the upper limit of the number of times, calculating the average deviation value based on the deviation value of the current time and the deviation value of the previous time.

[0047] Combination Figure 3 As shown, this disclosure provides another chip testing method for asynchronous half-duplex communication protocols, including:

[0048] S301: When the chip is powered on, the test instrument sends test commands and standard duration signals to the chip. The test chip calculates the deviation ratio between the internal clock signal and the external clock signal for multiple ranges. The internal clock signal for each range corresponds one-to-one with the deviation ratio.

[0049] The S302 test chip uses its internal clock to sample a standard duration signal to obtain deviation data for dynamic calibration.

[0050] S303: The test equipment uses commands to control and output multiple sets of protocol frame signals for excitation. The test chip receives the external excitation and compares the sampling results with the expected deviation results to obtain multiple deviation values.

[0051] S304, the test chip iteratively calculates the total number of deviations based on multiple deviation values.

[0052] S305, when the total number of deviations exceeds the upper limit of the test count, calculates the average deviation value.

[0053] The S306 test chip calculates a correction value for the clock deviation based on the deviation ratio, average deviation value, and internal count value of the protocol frame signal to calibrate the clock deviation.

[0054] In this embodiment, the average deviation value (Deviation_ave) is the average of the cumulative deviation values ​​within a single adjustment of the dynamic threshold. The process of iteratively calculating the average deviation value based on multiple deviation values ​​includes sequentially calculating the total number of deviations based on the multiple deviation values, and calculating the average deviation value when the total number of deviations exceeds a preset upper limit. By accumulating multiple deviation values ​​and calculating the average after reaching a certain number, a more stable and reliable deviation index is obtained. By setting an upper limit on the number of deviations, the influence of individual extreme deviation values ​​on the average deviation value can be avoided, thereby ensuring the stability and reliability of the test results. Furthermore, it can help testers better understand the distribution of deviation data, providing strong data support for further analysis and calibration.

[0055] Optionally, the total number of deviations is calculated sequentially based on multiple deviation values. The deviation data includes the maximum allowable range and the reasonable threshold range, including: if the current deviation value exceeds the allowable range, determining whether the current deviation value exceeds the reasonable threshold range; if the current deviation value exceeds the reasonable threshold range, determining the direction of the current deviation value exceeding the limit; and calculating the total number of deviations based on the direction of the exceeding limit.

[0056] In this embodiment of the disclosure, a maximum limit and a reasonable threshold range are included. The maximum limit (Max_range) refers to the boundary range within which the dynamic threshold can be adjusted, that is, the upper limit (Upper_threshold) and the lower limit (Lower_threshold) of the dynamic threshold. The reasonable threshold range (Range_reasonable) is a fixed value, and the upper and lower limits change dynamically during the calculation process.

[0057] The testing equipment sends a standard duration signal and samples the signal using an internal clock at the maximum operating temperature, minimum operating temperature, and normal temperature. The deviation range of the same signal count values ​​under these three temperature conditions is used as the deviation limit for the dynamic calibration process. Specifically, the upper limit of the dynamic threshold is measured at the chip's maximum operating temperature limit, and the lower limit is measured at the chip's minimum operating temperature limit. The result measured at normal temperature is used as the expected deviation result.

[0058] In this embodiment of the disclosure, the total number of deviations is calculated based on whether the current deviation value exceeds a threshold. Each deviation value is compared with a preset maximum limit and a reasonable threshold range to determine whether the deviation value needs to be included in the calculation of the total number of deviations.

[0059] By setting maximum and reasonable threshold ranges, the process of collecting deviation data can be controlled more precisely, avoiding the impact of extreme deviation values ​​on the overall test results. Simultaneously, a flexible deviation data processing mechanism is provided, which can dynamically adjust the maximum and reasonable threshold ranges according to changes in test conditions and environment, thereby improving the adaptability and accuracy of the test.

[0060] Optionally, the total number of deviations is calculated based on the direction of the deviation exceeding the limit, including: increasing the total number of deviations by 1 when the current deviation value is a positive deviation; and decreasing the total number of deviations by 1 when the current deviation value is a negative deviation.

[0061] This disclosure provides a method for calculating the total number of deviations based on the positive or negative direction of the deviation value. Specifically, when the current deviation value is positive, the total number of deviations increases; when the current deviation value is negative, the total number of deviations decreases. The directionality of each deviation value is determined, and the total number of deviations is adjusted accordingly based on the determination result.

[0062] This allows the testing process to more accurately reflect the actual impact of clock skew. Consequently, clock skew can be identified and corrected more effectively, thereby improving testing accuracy and the synchronization of communication protocols.

[0063] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: adjusting the maximum limit of the deviation value when the current deviation value does not exceed the allowable range.

[0064] In this embodiment of the disclosure, the deviation value is dynamically adjusted to the maximum extent possible while the current deviation value does not exceed the allowable range, so as to adapt to different test conditions and environmental changes.

[0065] By dynamically adjusting the maximum deviation value, the flexibility and adaptability of the testing method can be improved. When testing conditions or the environment change, adjusting the maximum limit can ensure the accuracy and reliability of the test results. Furthermore, it helps testers better understand the trend of deviation value changes, providing strong data support for further analysis and calibration.

[0066] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: adjusting a reasonable threshold range for the deviation value when the total number of deviations exceeds the upper limit of the number of tests.

[0067] In this embodiment of the disclosure, when the total number of deviations exceeds the upper limit of the number of tests, the deviation value is dynamically adjusted within a reasonable threshold range to ensure the stability and reliability of the test results.

[0068] By adjusting a reasonable threshold range when the total number of deviations exceeds a preset upper limit, instability in test results caused by a large number of deviation values ​​can be avoided. At the same time, it helps testers better control the distribution of deviation data, ensuring the accuracy of the testing process and the synchronization of communication protocols.

[0069] In practical applications, combined with Figure 5 The diagram shown illustrates the calculation of the average deviation value. The test chip's dynamic adjustment module has pre-configured registers for setting the dynamic threshold deviation range and the total number of threshold deviations. These configuration values ​​can be gradually adjusted during subsequent testing. The purpose of pre-setting the dynamic threshold deviation range is to eliminate errors caused by input / output delays or synchronization signals; therefore, it should not be set too large.

[0070] After configuration, the entire set of protocol frames received from external input is sampled. The communication module outputs results according to the protocol specifications, including the number of frames and the duration of received data. The dynamic calibration module calculates the average count per unit protocol frame and then records the deviation per unit duration between two consecutive sets of protocol frames. If the current deviation value does not exceed the allowable range, the average deviation value is calculated based on multiple deviation values, and a reasonable threshold range is adjusted. If the current deviation value exceeds the allowable range, it is determined whether the current deviation value exceeds the reasonable threshold range. If the current deviation value exceeds the reasonable threshold range, the direction of the deviation is determined. If the current deviation value does not exceed the reasonable threshold range, the average deviation value is calculated based on multiple deviation values, and a reasonable threshold range is adjusted. If the current deviation value is positive, the total deviation count is increased by 1. If the current deviation value is negative, the total deviation count is decreased by 1. If the total deviation count is greater than the maximum number of counts, the average deviation value is calculated based on multiple deviation values, and the reasonable threshold range for the deviation value is adjusted. The dynamic adjustment module outputs the average deviation value result. If the total deviation count is less than or equal to the maximum number of counts, the deviation value does not need to be included in the calculation of the total deviation count.

[0071] The allowable range refers to the boundary range within which the dynamic value can be adjusted. The maximum allowable range (Max_range) includes the maximum upper limit (Upper_threshold) and the minimum lower limit (Lower_threshold) of the dynamic value. It defines the maximum acceptable deviation range. Deviation values ​​exceeding this range are considered unacceptable and require special handling.

[0072] A reasonable threshold range is a fixed value whose upper and lower limits change dynamically during the calculation process. It describes the expected range of deviation values ​​under normal operating conditions. The reasonable threshold range is used to identify deviation values ​​that, although within the maximum allowable range, may still require attention or adjustment. In short, the maximum allowable range defines the maximum acceptable deviation range, while the reasonable threshold range further refines this maximum allowable range, defining a more reasonable and expected deviation range.

[0073] Optionally, a correction value for the clock skew is calculated to calibrate the clock skew based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signal, including calculating the correction value according to the following formula:

[0074] U t =K gp ×(e t +D td )

[0075] Among them, U t K is the correction value for clock skew. gp e represents the deviation ratio. t D is the internal count value of the protocol frame signal. td This represents the average deviation value.

[0076] In this embodiment of the disclosure, a correction value for the clock offset is calculated using a specific formula based on the offset ratio, the average offset value, and the internal count value of the protocol frame signal. This allows for the comprehensive consideration of the offset ratio, the average offset value, and the internal count value to calculate an accurate correction value.

[0077] By applying the formula, the required correction amount for clock skew can be accurately calculated, thereby achieving precise calibration of the chip clock. This improves the synchronization and overall performance of the communication protocol, ensuring the accuracy and reliability of data transmission during asynchronous half-duplex communication.

[0078] Furthermore, the communication module of the test chip can choose whether or not to use the correction value.

[0079] Optionally, calculating the deviation ratio between the internal clock signal and the external clock signal includes: performing frequency division processing on the internal clock signal to obtain a frequency-divided clock signal; counting the duration of the standard duration signal based on the frequency-divided clock signal and the external clock signal, respectively; and calculating the deviation ratio based on the counting results.

[0080] Combination Figure 4 As shown, this disclosure provides another chip testing method for asynchronous half-duplex communication protocols, including:

[0081] S401: When the chip is powered on, the test equipment sends a test command and a standard duration signal. The test chip performs frequency division processing on the internal clock signal to obtain a frequency-divided clock signal.

[0082] The S402 test chip counts the duration of the standard duration signal based on the frequency division signal and the external clock signal, respectively.

[0083] S403, the test chip iteratively calculates the deviation ratio based on the counting results.

[0084] The S404 test chip uses its internal clock to sample a standard duration signal to obtain deviation data for dynamic calibration.

[0085] S405, the test equipment will control the output of multiple sets of protocol frame signals to excite through instructions. The test chip receives the instructions and compares the sampling results of the external excitation with the expected deviation results to obtain multiple deviation values, and iterates the deviation values ​​to calculate the average deviation value; among them, the multiple deviation values ​​are the single protocol frame deviation values ​​obtained in each comparison.

[0086] The S406 test chip calculates a correction value for the clock deviation based on the deviation ratio, the average deviation value, and the internal count value of the protocol frame signal to calibrate the clock deviation.

[0087] In this embodiment of the disclosure, when the chip is powered on, the deviation ratio is calculated by frequency division processing of the internal clock signal and the duration of the counting standard duration signal. Frequency division processing of the internal clock signal yields a frequency-divided signal synchronized with the external clock signal. Then, the duration of the standard duration signal is counted based on the frequency-divided clock signal and the external clock signal. Finally, the deviation ratio is calculated based on the counting result.

[0088] By dividing and counting the clock frequency, clock skew can be accurately measured and calculated, providing accurate foundational data for subsequent dynamic calibration and communication protocol optimization. It also helps testers better understand the nature and impact of clock skew, providing strong data support for further analysis and calibration.

[0089] For example, in practical applications, the internal clock signal is divided into a frequency of approximately 1MHz and then fed into the clock comparison module. At the same time, the 1MHz standard clock signal emitted by the test machine is used as the external clock signal and fed into the external clock interface of the chip. The external input clock is synchronized with the internal clock signal and then fed into the clock comparison module.

[0090] Furthermore, the test chip actively sends a standard duration signal of the same length, uses an undivided clock for counting and inputs the calibration value corresponding to the division ratio, and the test equipment measures it to determine the accuracy of the deviation ratio.

[0091] Combination Figure 6 As shown, this disclosure provides a chip testing apparatus 60 for an asynchronous half-duplex communication protocol, including a processor 600 and a memory 601. Optionally, the apparatus 60 may further include a communication interface 602 and a bus 603. The processor 600, communication interface 602, and memory 601 can communicate with each other via the bus 603. The communication interface 602 can be used for information transmission. The processor 600 can call logical instructions in the memory 601 to execute the chip testing method for the asynchronous half-duplex communication protocol described in the above embodiment.

[0092] Furthermore, the logic instructions in the aforementioned memory 601 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0093] The memory 601, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 600 executes functional applications and data processing by running the program instructions / modules stored in the memory 601, thereby implementing the chip testing method for asynchronous half-duplex communication protocols described in the above embodiments.

[0094] The memory 601 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 601 may include high-speed random access memory and may also include non-volatile memory.

[0095] This disclosure provides a test bench, including a test bench body and the aforementioned chip testing device 60 for asynchronous half-duplex communication protocols. The chip testing device 60 for asynchronous half-duplex communication protocols is used within the test bench body. The usage described herein is not limited to placement within the test bench body, but also includes connection methods with other components of the test bench, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the chip testing device 60 for asynchronous half-duplex communication protocols can be adapted to suitable test bench bodies to achieve other feasible embodiments.

[0096] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0097] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0098] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0099] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A chip testing method for an asynchronous half-duplex communication protocol, characterized in that, include: When the chip is powered on, test commands and standard duration signals are sent to the chip to calculate the deviation ratio between the internal clock signal and the external clock signal for multiple ranges; wherein, the internal clock signal for multiple ranges corresponds one-to-one with multiple deviation ratios. The standard duration signal is sampled using an internal clock to obtain deviation data for dynamic calibration; The sampling results of multiple sets of externally input protocol frame signals are compared with the expected deviation results to obtain multiple deviation values, and the average deviation value is calculated iteratively; wherein, the multiple deviation values ​​are the single protocol frame deviation values ​​obtained in each comparison. The clock deviation correction value is calculated based on the deviation ratio, average deviation value, and internal count value of the protocol frame signal to calibrate the clock deviation.

2. The chip testing method according to claim 1, characterized in that, The average deviation value is calculated based on the deviation value, including: Calculate the total number of deviations based on multiple deviation values ​​in sequence; If the total number of deviations exceeds the upper limit of the number of times, calculate the average deviation value.

3. The chip testing method according to claim 2, characterized in that, Deviation data includes the maximum allowable range and the reasonable threshold range. The total deviation is calculated sequentially based on multiple deviation values, including: If the current deviation value exceeds the allowable range, determine whether the current deviation value exceeds a reasonable threshold range; If the current deviation value exceeds the reasonable threshold range, determine the direction of the current deviation value exceeding the limit; Calculate the total deviation based on the direction of the out-of-limit.

4. The chip testing method according to claim 3, characterized in that, The total deviation is calculated based on the direction of exceeding the limit, including: If the current deviation is a positive deviation, the total number of deviations increases by 1; If the current deviation value is a negative deviation, the total number of deviations decreases by 1.

5. The chip testing method according to claim 3, characterized in that, Also includes: If the current deviation value does not exceed the allowable range, adjust the maximum deviation value.

6. The chip testing method according to claim 3, characterized in that, Also includes: If the total number of deviations exceeds the upper limit of the number of times, adjust the reasonable threshold range of the deviation value.

7. The chip testing method according to any one of claims 1 to 6, characterized in that, Based on the deviation ratio, average deviation value, and internal count value of the protocol frame signal, a correction value for the clock deviation is calculated to calibrate the clock deviation, including calculating the correction value according to the following formula: U t =K gp ×(e t +D td ) Among them, U t K is the correction value for clock skew. gp e represents the deviation ratio. t D is the internal count value of the protocol frame signal. td This represents the average deviation value.

8. The chip testing method according to any one of claims 1 to 6, characterized in that, Calculate the deviation ratio between the internal clock signal and the external clock signal, including: The internal clock signal is divided to obtain the divided signal; The duration of the standard duration signal is counted based on the frequency division signal and the external clock signal, respectively. The deviation ratio is calculated based on the counting results.

9. A chip testing device for an asynchronous half-duplex communication protocol, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to run the program instructions to perform the chip testing method for an asynchronous half-duplex communication protocol as described in any one of claims 1 to 8.

10. A testing machine, characterized in that, include: The testing machine itself; The chip testing device for asynchronous half-duplex communication protocol as described in claim 9 is installed on the testing machine body.

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