Network card system, network card system data sending method and device, and storage medium
By building PHY circuits in the network card system and using signal identification generation circuits to generate flag sideband signals, the problems of slow response speed and high storage resource consumption of network card system are solved, and more efficient data communication and resource utilization are achieved.
Patent Information
- Application Number
- CN202411708347.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-03-28
AI Technical Summary
The existing network card system is slow to respond when communicating between computers and networks, and requires a large amount of storage resources, resulting in excessive consumption of chip resources.
By building a PHY circuit in the network card system, the PHY_RX in the PHY circuit and the NIC_TX control circuit in the transceiver control circuit use a same-origin clock source, and the signal identification generation circuit generates a flag sideband signal during the GMII interface signal transmission process to control the PHY_RX clock and avoid collecting signals in the invalid interval.
It improves the response speed of the network card, reduces the consumption of storage resources, ensures that the receiving end circuit only collects valid signals, can quickly send data in the buffer, and ensures that PHY_RX accurately receives data.
Smart Images
Figure CN119728613A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a network card and a method, device, and storage medium for transmitting data in a network card system. Background Art
[0002] With the continuous development of network communication technology, the communication capability of computers in the network has become increasingly important. The Network Interface Controller (NIC), as the key bridge between the computer and the network, is used in the physical layer and data link layer of the Open System Interconnect (OSI reference model). It controls the flow of data packets between the computer and the network, converts the data in the computer into network data packets for transmission, and can also receive network data packets. Therefore, the performance of the NIC will directly affect the network communication capability of the computer.
[0003] Generally, the NIC can be divided into two circuits: the receiving circuit (NIC_RX) and the transmitting circuit (NIC_TX). The NIC_RX is mainly used to receive TX packets from the external sender, parse, process, and transmit them to the CPU, while the NIC_TX is mainly used to convert the data processed by the CPU and need to be sent into the format of network data packets and send them to the external receiver.
[0004] Typically, NIC design must consider both the ability to fully receive network data packets and the ability to encapsulate data into network data packets for transmission. To meet these requirements, existing technologies typically use a PAUSE frame to prevent the sender from sending packets or directly discarding them if the NIC_RX circuit experiences a low processing rate and is unable to process cached data in a timely manner. On the NIC_TX side, the internal cache of the NIC_TX circuit must accumulate a certain amount of packet data. This means that the NIC_TX circuit's internal FIFO (First Input First Output) must have a complete set of packet data before it can send the packet to the external PHY via the GMII interface.
[0005] However, with the increasing demand for network responsiveness, storing a complete packet before sending it can severely impact circuit performance for devices with low latency tolerance. Furthermore, existing solutions result in a large number of long or even extremely long packets on the network. To cache these packets, existing solutions consume a significant amount of static random-access memory (SRAM) storage resources, significantly increasing chip resource consumption.
[0006] Therefore, how to improve the communication response speed between computers and networks while reducing chip resource consumption has become a technical problem that needs to be solved urgently in existing technologies. Summary of the Invention
[0007] The embodiment of the present application provides a network card system to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0008] The embodiment of the present application also provides a network card system data sending method to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0009] The embodiment of the present application also provides a network card system data sending device to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0010] The embodiment of the present application also provides a network card system data sending device to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0011] The embodiment of the present application also provides a computer-readable storage medium to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0012] The embodiments of this application adopt the following technical solutions: A network card system includes: a physical interface PHY circuit, a signal identification generating circuit, a chip core circuit, a transceiver control circuit, a data cache module, a memory access DMA module and a memory MEM circuit; the physical interface PHY circuit exchanges data with the transceiver control circuit via a Gigabit Media Independent II (GMII) interface, and is used to convert digital signals into physical signals for transmission and / or convert received physical signals into digital signals; the data cache module includes a receive data cache module RX_FIFO and a transmit data cache module TX_FIFO; the transceiver control circuit includes a receive control NIC_RX circuit and a transmit control NIC_TX circuit, and the NIC_RX circuit interacts with the physical interface PHY circuit. The RX_FIFO is connected, and the NIC_TX circuit is connected to the TX_FIFO; the signal identification generating circuit is respectively connected to the NIC_TX circuit and the physical interface PHY circuit, and is used to generate a flag sideband signal that identifies the validity of the GMII standard interface signal, and transmit the flag sideband signal to the physical interface PHY circuit through the GMII interface; the memory access DMA module is respectively connected to the RX_FIFO, the TX_FIFO and the memory MEM circuit, and is used to transmit packet data between the RX_FIFO and the memory MEM circuit, and between the TX_FIFO and the memory MEM circuit.
[0013] A data transmission method based on a network card system comprises: obtaining packet data from a TX_FIFO via a NIC_TX circuit of the network card system; storing the packet data in a data buffer; obtaining current stored data in the TX_FIFO via a signal identification generating circuit of the network card system; obtaining cached packet data in the data buffer via the signal identification generating circuit; generating a flag sideband signal for identifying the validity of a GMII standard interface signal based on the stored data and the cached packet data, and sending the flag sideband signal to the NIC_TX circuit; and when the NIC_TX circuit determines that an interface signal is valid based on the flag sideband signal, reading the cached packet data from the data buffer and sending the data to a physical interface PHY circuit via the GMII interface.
[0014] A network card system data transmitting device comprises: a packet data reading unit for obtaining packet data from a TX_FIFO; a cache unit for storing the packet data in a data buffer; a signal validity analysis unit for obtaining data currently stored in the TX_FIFO; a signal validity analysis unit for obtaining cached packet data in the data buffer; a signal validity analysis unit for generating a flag sideband signal for identifying the validity of a GMII standard interface signal based on the stored data and the cached packet data, and sending the flag sideband signal to the NIC_TX circuit; and a data transmitting unit for reading the cached packet data from the data buffer when determining that an interface signal is valid based on the flag sideband signal, and sending the cached packet data to a physical interface PHY circuit via a GMII interface.
[0015] A network card system data sending device, comprising: a processor; and a memory arranged to store computer-executable instructions, wherein the executable instructions, when executed, cause the processor to perform the following operations: obtain packet data from a TX_FIFO through a NIC_TX circuit of a network card system; store the packet data in a data buffer; obtain current stored data in the TX_FIFO through a signal identification generating circuit of the network card system; obtain cached packet data in the data buffer through the signal identification generating circuit; the signal identification generating circuit generates a flag sideband signal for identifying the validity of a GMII standard interface signal based on the stored data and the cached packet data, and sends the flag sideband signal to the NIC_TX circuit; and when the NIC_TX circuit determines that the interface signal is valid based on the flag sideband signal, reads the cached packet data from the data buffer and sends the data to a physical interface PHY circuit through the GMII interface.
[0016] A computer-readable storage medium stores one or more programs. When executed by an electronic device including multiple application programs, the one or more programs cause the electronic device to perform the following operations: obtain packet data from a TX_FIFO via a NIC_TX circuit of a network card system; store the packet data in a data buffer; obtain the current stored data in the TX_FIFO via a signal identification generating circuit of the network card system; obtain the cached packet data in the data buffer via the signal identification generating circuit; the signal identification generating circuit generates a flag sideband signal for identifying the validity of a GMII standard interface signal based on the stored data and the cached packet data, and sends the flag sideband signal to the NIC_TX circuit; and when the NIC_TX circuit determines that an interface signal is valid based on the flag sideband signal, reads the cached packet data from the data buffer and sends it to a physical interface PHY circuit via the GMII interface.
[0017] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: The network card system provided by the embodiment of the present application has a built-in PHY circuit in the network card system, so that the PHY_RX in the PHY circuit can use the same clock source as the NIC_TX control circuit in the transceiver control circuit, and thus, in the same clock domain, the clock of the PHY_RX can be controlled by the signal identifier generated by the NIC_TX side. At the same time, through the signal identifier generating circuit, during the GMII interface signal transmission process, a flag sideband signal that can indicate whether the GMII standard interface signal is valid is generated, and the clock of the PHY_RX is controlled by the flag sideband signal, so that the PHY_RX can filter the signal indicating the invalid interval according to the flag sideband signal, and thus the PHY_RX will not collect the GMII interface signal in the invalid interval. Since the network card system provided by the embodiment of the present application is used, the signals collected by the receiving circuit are all valid signals. By splicing these valid signals, the fragmented packets can be spliced into a complete data packet. Therefore, when sending data, the NIC_TX control circuit can quickly send the data in the buffer without waiting for a full-length packet, and can ensure that the built-in PHY_RX accurately receives the data, greatly improving the response speed of the network card. At the same time, because the NIC_TX control circuit no longer needs to store full-length packets, the consumption of network card storage resources during data communication is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a schematic diagram of the internal structure of an existing network card system; Figure 2 This is the timing waveform diagram of the interface part when using the existing network card system for data transmission; Figure 3 A schematic diagram of the internal structure of a network card system provided in an embodiment of the present application; Figure 4 A communication flow diagram of a network card system is provided based on an embodiment of the present application; Figure 5 A schematic diagram of the specific structure of the MX_CELL_GCK circuit in the network card system provided in an embodiment of the present application; Figure 6 This is the timing waveform diagram of the interface part when using the existing network card system for data transmission; Figure 7 A schematic diagram of a specific flow chart of a method for sending data through a network card system provided in an embodiment of the present application; Figure 8 A schematic diagram of the specific structure of a network card system data sending device provided in an embodiment of the present application; Figure 9 A schematic diagram of the specific structure of a network card system data sending device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0019] The existing network interface card (NIC) system design structure is as follows Figure 1 As shown, in order to ensure that the data packet can be received completely, in the existing NIC system, NIC_TX needs to wait for the internal TX_FIFO to buffer a complete packet data before sending the packet to the external PHY through the GMII interface to complete the data communication.
[0020] In the Gigabit Media Independent Interface (GMII) protocol, it is generally believed that the data corresponding to NIC_TXD[7:0] is valid only when the NIC_TXEN signal is high. Once the interface signal NIC_TXEN is pulled low, it is considered that a packet has ended. At the same time, a certain interval is required between each packet to recover and prepare for receiving the next packet. This interval is called the inter-packet gap (IPG).
[0021] When the existing NIC system is sending data, the timing waveform of the interface is as follows: Figure 2 As shown in the figure, if the NIC system's NIC_TX side begins to pull NIC_TXEN high and transmits the Preamble and SFD (Start of Frame Descriptor) before a frame's worth of data has been prepared (i.e., the NIC_TX's internal TX_FIFO has not yet buffered a complete packet), the external PHY receiver circuit will interpret this as the start of data transmission. However, since the NIC_TX side is not prepared for a frame's worth of data, the NIC_TX's TX_FIFO will be empty during transmission. At this point, the interface signal NIC_TXEN will be pulled low, and the frame data on the NIC_TXD[7:0] signals will be filled with invalid data. The PHY circuit, upon detecting that NIC_TXEN has been pulled low, assumes that the frame has been received. When the remaining data for the packet is stored in the NIC_TX's TX_FIFO, NIC_TXEN will be raised again, and the Preamble and SFD will not be transmitted on NIC_TXD. In this case, the NIC_TXEN bit of NIC_TX will be repeatedly pulled high and then low according to the data in the cache space. Obviously, the data packet of this frame is divided into multiple incomplete data, that is, the so-called "fragmented packet". The PHY circuit can only recognize the first fragmented packet containing the Preamble and SFD fields. This will lead to a large amount of frame data loss during data transmission between the computer and the network side.
[0022] In the prior art, conventional NIC systems do not allow the above fragmented packet situation to occur, otherwise it will cause packet data transmission errors in the entire device. Therefore, when designing the existing NIC system, it is necessary to ensure that at least one complete packet is cached in the NIC_TX circuit before sending the data packet to the PHY circuit through the GMII interface. This means that the TX_FIFO in the NIC_TX circuit must be able to store a maximum packet, and the packet length does not have a clear length limit in the actual circuit. If 14 bits are used to represent the packet length, the packet can be up to 16KB in length. The 64-bit TX_FIFO requires a depth of 2K to store the packet. Obviously, the 16KB TX_FIFO consumes more hardware resources and occupies a larger chip area. It is not cost-effective to use a larger TX_FIFO to store packets simply for the above limitations.
[0023] In addition, storing a complete packet before sending it will seriously affect circuit performance for devices with low latency tolerance. Assuming that the CPU only sends very long packets and only sends one packet at a time, the NIC_TX circuit will need to wait for a packet to be fully buffered before sending it. The delay in receiving the packet on the other end will become very large.
[0024] In order to solve the above-mentioned problems existing in the existing NIC system, the embodiments of the present application design a new network card NIC system, and a data sending method based on the NIC system. In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0025] The following describes in detail the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.
[0026] The embodiment of the present application provides a network card system to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0027] In one embodiment, the internal structure of the network card system is as follows: Figure 3 As shown, it mainly consists of the following parts: built-in physical interface PHY circuit, signal identification generation circuit, chip core circuit, transceiver control circuit, data cache module, memory access DMA module and memory MEM circuit.
[0028] The following is a detailed introduction to the connection relationship, operation logic and functions of each of the above parts in the network card system.
[0029] A major difference between the network card system designed in the embodiment of the present application and the existing network card system is that in the network card system designed in the embodiment of the present application, the PHY circuit is integrated into the network card system, rather than the independent PHY circuit used in the existing network card system. The PHY circuit integrated into the network card system can exchange data with the transceiver control circuit of the network card system through the GMII interface, and can then cooperate with the network card system circuit by adding custom sideband signals and corresponding processing circuits, thereby realizing subsequent coordinated data communication between the PHY circuit and the NIC_TX control circuit in the transceiver control circuit, thereby avoiding the problem of fragmented packets.
[0030] In the embodiment of the present application, the PHY circuit serves as a physical interface transceiver, which defines the data encoding, clock reference, line status, electrical and optical signals for data transmission and reception. It can interact / communicate with digital circuits such as the receiving control NIC_RX circuit and the transmitting control NIC_TX circuit in the network card system through the GMII interface. At the same time, it can also convert packet data in the form of digital signals into physical signals for transmission or convert received physical signals into digital signals. Among them, the PHY circuit can be specifically divided into: a receiving PHY_RX circuit and a transmitting PHY_TX circuit.
[0031] In an embodiment of the present application, the transceiver control circuit of the network card system may specifically be composed of a receiving control NIC_RX circuit and a transmitting control NIC_TX circuit. The NIC_RX circuit is connected to the receiving data buffer module RX_FIFO in the data buffer module, and the NIC_TX circuit is connected to the transmitting data buffer module TX_FIFO in the data buffer module.
[0032] In an embodiment of the present application, the NIC_RX control circuit is used to exchange data with the PHY circuit through the GMII interface, parse the packet data on the GMII interface of the PHY circuit, and store it in the RX_FIFO memory according to a specific format.
[0033] Among them, the RX_FIFO memory can be divided into an asynchronous FIFO structure (ASYNC_FIFO) and a synchronous FIFO structure (synchronous SYNC_FIFO). The ASYNC_FIFO has a smaller depth and is only used to synchronize the GMII interface data across clock domains and synchronize the data to the main clock domain of the network card system, while the SYNC_FIFO is used to store packet data.
[0034] In the embodiment of the present application, since using SRAM as the storage space can save a lot of chip area compared to Register when the amount of data to be stored is large, in order to save chip area, the SYNC_FIFO result only retains the control logic of FIFO, and replaces its internal storage space from the original register Register to static random access memory SRAM.
[0035] At the same time, the NIC_RX control circuit also calls the Direct Memory Access (DMA) module in the network card system. The DMA module can transfer network data directly from the network card system to system memory, or from system memory to the network card system, without CPU intervention, thereby reducing the CPU burden. In the embodiment of the present application, the DMA module is primarily responsible for moving packet data. Once a certain amount of packet data exists in the SYNC_FIFO, the NIC_RX control circuit will initiate a DMA request. The DMA determines whether to initiate a burst transmission (burst) based on the amount of data in the SYNC_FIFO and the remaining amount of packet data, moving the data to the memory MEM space for storage. The memory MEM space is a system-dedicated storage space dedicated to storing network card system data packets and is directly accessible by the CPU.
[0036] In an embodiment of the present application, the NIC_TX control circuit is used to retrieve the packet data from the TX_FIFO memory and store it in the data buffer, and to exchange data with the PHY circuit through the GMII interface. When NIC_TXEN / NIC_TXD is valid, 1 Byte of data is read from the buffer in sequence according to the GMII interface and sent to the built-in PHY circuit. Finally, the PHY circuit converts the packet data into an analog signal and sends it to the link.
[0037] The TX_FIFO memory also consists of an asynchronous FIFO memory and a synchronous FIFO memory. The synchronous FIFO memory's storage space is still replaced by SRAM instead of the original register. After the CPU processes the packet data to be transmitted, it stores it in the MEM space and then notifies the NIC_TX control circuit to fetch the packet. Based on the received notification, the NIC_TX control circuit calls the DMA module to fetch the packet data from the MEM space and store it in the TX_FIFO memory.
[0038] In one embodiment, the embodiment of the present application provides a structural basis for the NIC_TX control circuit to coordinately regulate the clock of the PHY circuit during data transmission in the network card system by integrating the PHY circuit into the network card system architecture. On this structural basis, the NIC_TX control circuit coordinates the clock of the PHY circuit so that even if the NIC_TX control circuit sends a "fragmented packet", it can be accurately received by the PHY circuit.
[0039] In order to achieve the above functions, the embodiment of the present application adds a signal identification generation circuit (hereinafter referred to as CLK_VLD_FLG generation circuit) to the network card system. The CLK_VLD_FLG generation circuit is connected to the NIC_TX control circuit and the PHY circuit respectively. During the transmission process of the GMII interface signal NIC_TXEN / NIC_TXD, it is used to simultaneously generate a flag sideband signal that identifies the validity of the GMII standard interface signal, and transmit the flag sideband signal to the PHY circuit through the GMII interface. Then, the receiving clock of the PHY circuit can be gated by the flag sideband signal in combination with the sending clock signal NIC_TXC of the NIC_TX control circuit to generate a clock (CLOCK_GATING).
[0040] In one embodiment, the CLK_VLD_FLG generating circuit may generate a flag sideband signal according to the amount of data stored in the TX_FIFO memory and the byte data transmission status of the NIC_TX control circuit during the transmission process.
[0041] Specifically, during the actual data communication process of the network card system, the following situations may be encountered. In these situations, the CLK_VLD_FLG generating circuit can determine and generate the flag sideband signal in the following manner: 1. When the TX_FIFO memory is not empty: When the CLK_VLD_FLG generation circuit determines that there is data in the TX_FIFO memory based on the acquired TX_FIFO storage data, then during the data transmission process, there must be data in the data buffer of the NIC_TX control circuit, indicating that the NIC_TX control circuit can currently send valid byte data. The CLK_VLD_FLG generation circuit will then generate a first flag sideband signal to indicate that the GMII standard interface signal is valid.
[0042] 2. When the TX_FIFO memory is empty but there is data in the data buffer: When the CLK_VLD_FLG generation circuit determines that there is no data in the TX_FIFO memory based on the obtained TX_FIFO storage data, but determines that there is data in the data buffer buffer based on the obtained cache byte data, it means that the NIC_TX control circuit is currently sending valid data, then the CLK_VLD_FLG generation circuit will generate a first flag sideband signal for indicating that the GMII standard interface signal is valid.
[0043] 3. When both the TX_FIFO memory and the buffer are empty: After the last byte of data in the CLK_VLD_FLG data buffer is sent by the NIC_TX control circuit, there is no data in the data buffer, indicating that the NIC_TX control circuit has completed sending the previous packet data retrieved from the TX_FIFO memory. At this time, the NIC_TX control circuit will retrieve a new packet data from the TX_FIFO memory and send it. If the TX_FIFO memory is still empty at this time, it indicates that the NIC_TX control circuit cannot currently send valid data, and the CLK_VLD_FLG generation circuit will generate a second flag sideband signal to indicate that the GMII standard interface signal is invalid.
[0044] In addition, it should be noted that, in order to avoid the generation of glitches, in the embodiment of the present application, the CLK_VLD_FLG generation circuit generates the flag sideband signal based on a D flip-flop (D Flip Flop, DFF).
[0045] In the embodiment of the present application, the communication process between the NIC_TX control circuit and the PHY circuit is as follows: Figure 4 As shown, in the network card system architecture provided in the embodiment of the present application, the PHY_RX circuit and the NIC_TX circuit exchange data via the GMII interface, and the NIC_TX control circuit and the PHY_RX in the PHY circuit use the same clock source, which has a clock frequency of 125MHz. In the same clock domain, the clock of the PHY_RX circuit can be controlled by the flag sideband signal generated by the NIC_TX control circuit via the CLK_VLD_FLG generation circuit.
[0046] like Figure 4 As shown in the figure, NIC_TXC is the transmit clock in the GMII interface, NIC_TXD[7:0] is the 8-bit transmit data, NIC_TXEN is the transmit enable, and CLK_VLD_FLG is the flag sideband signal generated by the CLK_VLD_FLG generator, which instructs the PHY_RX circuit how to accurately receive packets that are considered fragmented packets under conventional interfaces. The MX_CELL_GCK circuit is an internal circuit module, typically provided directly in the process library without requiring specialized design. Its function is similar to other integrated clock gating (ICG) circuits. Common ICG circuits typically have two structures: AND gates and OR gates. They are mainly used for: 1. Eliminating glitches during dynamic clock switching; 2. In low-power management, shutting down the clock signal to stop circuit operation and reduce circuit power consumption; and 3. Clock frequency division during clock processing.
[0047] The AND gate structure ICG circuit, only when CLOCK_IN is low level "0", the scan_mode signal TE (Test Enable) connected to the DFT or the control signal E (Enable) of the functional circuit will pass through the latch and be latched, so its output first waveform is the rising edge. The OR gate structure is the opposite, and the output first waveform is the falling edge. Therefore, the AND gate structure ICG is generally used in the circuit of rising edge sampling. Therefore, in one embodiment, the MX_CELL_GCK circuit used in the embodiment of the present application can be an AND gate structure, such as Figure 5 As shown, the embodiment of the present application utilizes MX_CELL_GCK to dynamically switch the clock, and uses the flag sideband signal CLK_VLD_FLG generated by the CLK_VLD_FLG generating circuit as the Enable signal, which can well achieve the clock gating effect of the PHY_RX clock. The processed PHY_RX clock can be free of "fragmented packets", that is, it ignores the invalid NIC_TXE / NIC_TXD interval that occurs during the transmission process of a packet, and the PHY end can still accurately and completely sample and receive the data frame.
[0048] In one embodiment, using Figure 4 The communication process shown in the figure shows the timing waveform of the GMII interface part of the PHY_RX circuit receiving the GMII interface from the NIC_TX control circuit. Figure 6 As shown, the NIC_TX control circuit can start transmitting data without waiting for a complete packet to be stored. When the buffer space inside the NIC_TX control circuit has read the remaining 1-byte packet data, but the remaining data has not yet been retrieved from the MEM space into the buffer, the GMII interface signal of the NIC_TX control circuit will enter one or more invalid intervals during data transmission. During this period, the NIC_TXD data bus is filled with invalid data or the last data result is maintained by the NIC_TX control circuit.
[0049] In existing network card systems, the external PHY circuit cannot coordinate with the NIC_TX control circuit. Therefore, the PHY_RX side clock of the existing network card system uses the unprocessed NIC_TXC clock for rising edge sampling. At this time, the NIC_TXEN / NIC_TXD in the invalid range of the interface will also be sampled by the PHY_RX circuit. At this time, there are two situations: In case a, if NIC_TXEN remains low in the invalid range, according to the GMII interface protocol, the PHY_RX circuit will regard the packet transmission as complete. Even if the NIC_TX control circuit subsequently sends the remaining packet data in sequence, the PHY_RX circuit will not recognize the subsequent packet data according to the protocol.
[0050] In case b, if NIC_TXEN is maintained at a high level in the invalid range, according to the GMII interface protocol, the PHY_RX circuit will mistakenly believe that the NIC_TXD value in the invalid range is a normal transmitted packet data. Obviously, the PHY_RX circuit will receive an erroneous packet.
[0051] It can be seen that the existing network card system will lead to packet error transmission in the above two situations. However, the network card system structure provided by the embodiment of the present application, through the built-in PHY circuit and the newly added CLK_VLD_FLG generating circuit, can make the PHY_RX and NIC_TX control circuit use the same clock source and be in the same NIC_TXC clock domain. The NIC_TX control circuit uses the flag sideband signal CLK_VLD_FLG and the NIC_TXC clock signal provided by the CLK_VLD_FLG generating circuit. After being processed by the ICG circuit, the PHY_RX side clock realizes Clock gating. The final PHY_RX side clock is as follows. Figure 6 As shown in the PHY_RXC signal, the NIC_TXEN / NIC_TXD in the invalid range will not be recognized by the PHY receiving circuit, so the so-called fragmented packets will be spliced. At the same time, the NIC_TXEN signal in the invalid range no longer needs to be frequently pulled low. From the perspective of the receiving circuit, the intermediate process control signal of the fragmented packet is basically consistent with the GMII standard, and the complete valid data on NIC_TXD can be received.
[0052] The network card system provided by the embodiment of the present application has a built-in PHY circuit in the network card system, so that the PHY_RX in the PHY circuit can use the same clock source as the NIC_TX control circuit in the transceiver control circuit, and thus, in the same clock domain, the clock of the PHY_RX can be controlled by the signal identifier generated by the NIC_TX side. At the same time, through the signal identifier generation circuit, during the GMII interface signal transmission process, a flag sideband signal that can indicate whether the GMII standard interface signal is valid is generated, and the clock of the PHY_RX is controlled by the flag sideband signal, so that the PHY_RX can filter the signal indicating the invalid interval according to the flag sideband signal, and thus the PHY_RX will not collect the GMII interface signal in the invalid interval. Since the network card system provided by the embodiment of the present application is used, the signals collected by the receiving circuit are all valid signals. By splicing these valid signals, the fragmented packets can be spliced to obtain a complete data packet. Therefore, when sending data, the NIC_TX control circuit can quickly send the data in the buffer without waiting for a full-length packet, and can ensure that the built-in PHY_RX accurately receives the data, greatly improving the response speed of the network card. At the same time, because the NIC_TX control circuit no longer needs to store full-length packets, the consumption of network card storage resources during data communication is greatly reduced.
[0053] In one embodiment, the present application also provides a data sending method based on the above-mentioned network card system to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network.
[0054] Based on the above network card system, the specific implementation flow diagram of the network card system data sending method provided in this application is as follows: Figure 7 As shown, it mainly includes the following steps: Step 11: Obtain packet data from the TX_FIFO memory through the NIC_TX control circuit of the network card system.
[0055] In step 12, the NIC_TX control circuit stores the packet data into the data buffer.
[0056] Step 13: The signal identification generating circuit of the network card system generates a flag sideband signal for identifying the validity of the GMII standard interface signal according to the data transmission status of the NIC_TX circuit and the amount of remaining data in the data buffer, and sends the flag sideband signal together with the GMII interface to the PHY_RX circuit.
[0057] In step 14, when the NIC_TX circuit determines that the interface signal is valid based on the flag sideband signal, it reads the cached packet data from the data buffer. The NIC_TX circuit sends the packet data through the GMII interface. Simultaneously, the signal identification generating circuit sends the flag sideband signal. When the sideband signal is valid, the packet data is read from the data buffer. When the sideband signal is invalid, the packet data is filled with an invalid value and sent to the physical interface PHY circuit through the GMII interface.
[0058] By adopting the network card method provided in the embodiment of the present application, a PHY circuit is built into the network card system so that the PHY_RX in the PHY circuit can use the same clock source as the NIC_TX control circuit in the transceiver control circuit. Therefore, in the same clock domain, the clock of the PHY_RX can be controlled by the signal identifier generated by the NIC_TX side. At the same time, through the signal identifier generation circuit, during the GMII interface signal transmission process, a flag sideband signal that can indicate whether the GMII standard interface signal is valid is generated, and the clock of the PHY_RX is controlled by the flag sideband signal, so that the PHY_RX can filter the signal indicating the invalid interval according to the flag sideband signal, and thus the PHY_RX will not collect the GMII interface signal in the invalid interval. Since the network card system provided in the embodiment of the present application is used, the signals collected by the receiving circuit are all valid signals. By splicing these valid signals, the fragmented packets can be spliced into a complete data packet. Therefore, when sending data, the NIC_TX control circuit can quickly send the data in the buffer without waiting for a full-length packet, and can ensure that the built-in PHY_RX accurately receives the data, greatly improving the response speed of the network card. At the same time, because the NIC_TX control circuit no longer needs to store full-length packets, the consumption of network card storage resources during data communication is greatly reduced.
[0059] In one embodiment, the present application also provides a data transmission device based on a network card system to solve the problem that the existing network card system has a slow response speed and consumes a large amount of storage resources when realizing communication between a computer and a network. Figure 8 As shown, it includes: a packet data reading unit 81, a buffer unit 82, a signal validity analysis unit 83 and a data sending unit 84.
[0060] Wherein, the packet data reading unit 81 is used to obtain the packet data from the TX_FIFO; The cache unit 82 is used to store the packet data in a data buffer; a signal validity analysis unit 83 for generating a flag sideband signal for identifying the validity of a GMII standard interface signal based on the data transmission status of the NIC_TX circuit and the amount of remaining data in the data buffer, and sending the flag sideband signal to the NIC_TX circuit; The data sending unit 84 is configured to read the cached packet data from the data buffer and send the cached packet data to the physical interface PHY circuit via the GMII interface when determining that the interface signal is valid according to the flag sideband signal.
[0061] The data transmission device based on the network card system provided in the embodiment of the present application is adopted. By building a PHY circuit into the network card system, the PHY_RX in the PHY circuit can use the same clock source as the NIC_TX control circuit in the transceiver control circuit. Therefore, in the same clock domain, the clock of the PHY_RX can be controlled by the signal identifier generated by the NIC_TX side. At the same time, the signal identifier generating circuit generates a flag sideband signal that can indicate whether the GMII standard interface signal is valid during the GMII interface signal transmission process. The flag sideband signal is used to control the clock of the PHY_RX, so that the PHY_RX can filter the signal indicating the invalid interval according to the flag sideband signal. Therefore, the PHY_RX will not collect the GMII interface signal in the invalid interval. Since the network card system provided in the embodiment of the present application is used, the signals collected by the receiving circuit are all valid signals. By splicing these valid signals, the fragmented packets can be spliced into a complete data packet. Therefore, when sending data, the NIC_TX control circuit can quickly send the data in the buffer without waiting for a full-length packet, and can ensure that the built-in PHY_RX accurately receives the data, greatly improving the response speed of the network card. At the same time, because the NIC_TX control circuit no longer needs to store full-length packets, the consumption of network card storage resources during data communication is greatly reduced.
[0062] Figure 9 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. Figure 9 At the hardware level, the electronic device includes a processor and, optionally, an internal bus, a network interface, and memory. The memory may include internal memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the electronic device may also include other hardware required for its services.
[0063] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 9 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.
[0064] The memory is used to store programs. Specifically, the program may include program code, which includes computer operating instructions. The memory may include internal memory and non-volatile memory, and provides instructions and data to the processor.
[0065] The processor reads the corresponding computer program from the non-volatile memory into the internal memory and then runs it, forming a network card system data transmission device at the logical level. The processor executes the program stored in the memory and is specifically configured to perform the following operations: obtain packet data from the TX_FIFO through the NIC_TX circuit of the network card system; store the packet data in a data buffer; obtain the current stored data in the TX_FIFO through the signal identification generation circuit of the network card system; obtain the cached packet data in the data buffer through the signal identification generation circuit; the signal identification generation circuit generates a flag sideband signal for indicating the validity of the GMII standard interface signal based on the stored data and the cached packet data, and sends the flag sideband signal to the NIC_TX circuit; when the NIC_TX circuit determines that the interface signal is valid based on the flag sideband signal, it reads the cached packet data from the data buffer and sends it to the physical interface PHY circuit via the GMII interface.
[0066] The above application Figure 9The methods performed by the electronic device for transmitting data in a network card system disclosed in the illustrated embodiments can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the aforementioned method can be performed by hardware integrated logic circuits within the processor or by software instructions. The aforementioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules within the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.
[0067] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.
[0068] The embodiment of the present application also provides a computer-readable storage medium, which stores one or more programs, wherein the one or more programs include instructions, which, when executed by a portable electronic device including multiple application programs, can enable the portable electronic device to execute Figure 7 The method of the embodiment shown is specifically used to perform the following operations: The NIC_TX circuit of the network card system obtains packet data from the TX_FIFO; stores the packet data in a data buffer; obtains the current stored data in the TX_FIFO through the signal identification generating circuit of the network card system; obtains the cached packet data in the data buffer through the signal identification generating circuit; the signal identification generating circuit generates a flag sideband signal for identifying the validity of the GMII standard interface signal based on the stored data and the cached packet data, and sends the flag sideband signal to the NIC_TX circuit; when the NIC_TX circuit determines that the interface signal is valid based on the flag sideband signal, it reads the cached packet data from the data buffer and sends it to the physical interface PHY circuit through the GMII interface.
[0069] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0070] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0071] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0072] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0073] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.
[0074] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
[0075] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can be implemented using any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change RAM (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.
[0076] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.
[0077] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0078] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.
Claims
1. A network card system, characterized in that: include: Physical interface PHY circuit, signal identification generation circuit, chip core circuit, transceiver control circuit, data cache module, memory access DMA module and memory MEM circuit; The physical interface PHY circuit performs data exchange with the transceiver control circuit via a Gigabit medium-independent GMII interface, and is used to convert digital signals into physical signals for transmission and / or convert received physical signals into digital signals; The data buffer module includes a receiving data buffer module RX_FIFO and a transmitting data buffer module TX_FIFO; The transceiver control circuit includes a receiving control NIC_RX circuit and a sending control NIC_TX circuit, the NIC_RX circuit is connected to the RX_FIFO, and the NIC_TX circuit is connected to the TX_FIFO; The signal identification generating circuit is connected to the NIC_TX circuit and the physical interface PHY circuit respectively, and is used to generate a flag sideband signal identifying the validity of the GMII standard interface signal, and transmit the flag sideband signal to the physical interface PHY circuit through the GMII interface; The memory access DMA module is connected to the RX_FIFO, the TX_FIFO and the memory MEM circuit respectively, and is used for transmitting packet data between the RX_FIFO and the memory MEM circuit, and between the TX_FIFO and the memory MEM circuit.
2. The network card system according to claim 1, characterized in that: The signal identification generating circuit is used to generate the flag sideband signal according to the data transmission status of the NIC_TX circuit and the amount of remaining data in the data buffer.
3. The network card system according to claim 2, characterized in that: When the signal identification generating circuit determines that there is data in the TX_FIFO, the signal identification generating circuit generates a first flag sideband signal for indicating that the GMII standard interface signal is valid; When the signal identification generating circuit determines that there is no data in the TX_FIFO, and the signal identification generating circuit determines that there is an integer multiple of byte data in the cache according to the acquired cache byte data, the signal identification generating circuit generates a first flag sideband signal for indicating that the GMII standard interface signal is valid; When the signal identification generating circuit determines that there is no data in the TX_FIFO, and the signal identification generating circuit determines that there is no byte data in the cache based on the acquired cache byte data, the signal identification generating circuit generates a second flag sideband signal for indicating that the GMII standard interface signal is invalid.
4. The network card system according to claim 1, characterized in that: The physical interface PHY circuit includes a receiving PHY_RX circuit and a sending PHY_TX circuit; The PHY_RX circuit and the NIC_TX circuit use the same clock source. The PHY_RX circuit exchanges data with the NIC_TX circuit via the GMII interface. The clock frequency of the clock source is 125 MHz.
5. The network card system according to claim 4, characterized in that: The PHY_RX circuit includes an integrated clock gating circuit, which is configured as an AND gate structure.
6. A data transmission method based on the network card system according to claim 1, characterized in that: include: Get the packet data from TX_FIFO through the NIC_TX circuit of the network card system; Storing the packet data in a data buffer; Generate a flag sideband signal for identifying the validity of a GMII standard interface signal through the signal identification generating circuit of the network card system according to the data transmission status of the NIC_TX circuit and the amount of remaining data in the data buffer, and send the flag sideband signal to the PHY_RX circuit; When the NIC_TX circuit determines that the interface signal is valid according to the flag sideband signal, it reads the cached packet data from the data buffer and sends it to the physical interface PHY circuit through the GMII interface.
7. A data sending device based on the network card system according to claim 1, characterized in that: include: A packet data reading unit, used for obtaining packet data from TX_FIFO; A cache unit, used for storing the packet data in a data buffer; A signal validity analysis unit, used for generating a flag sideband signal for identifying the validity of a GMII standard interface signal according to a data transmission state of the NIC_TX circuit and the amount of remaining data in a data buffer, and sending the flag sideband signal to the NIC_TX circuit; The data sending unit is used to read the cached packet data from the data buffer buffer and send it to the physical interface PHY circuit through the GMII interface when determining that the interface signal is valid according to the flag sideband signal.
8. A network card system data sending device, comprising: processor; A memory arranged to store computer executable instructions, which, when executed, cause the processor to execute the network card system data sending method as claimed in claim 6.
9. A computer-readable storage medium storing one or more programs, which, when executed by an electronic device including a plurality of application programs, enables the electronic device to execute the network card system data sending method according to claim 6.