Data processing method and device

Abstract

The invention discloses a data processing method and device and belongs to the technical field of communication. The method is applied to the flexible Ethernet (FlexE), and the method is applied to the flexible Ethernet (FlexE). The method comprises: receiving an initial data stream sent by a FlexE instance, periodically inserting a filling sequence in the initial data stream to obtain a first data stream, the first data stream comprising the periodically appearing filling sequence, the filling sequence comprising continuous n filling code blocks, and n being an integer greater than or equal to 4. The invention provides a FlexE (FlexE)-oriented method capable of inserting more filling code blocks into a data stream, which can be suitable for PHY (Physical Layer) interfaces with higher rate, such as a 800 gigabit Ethernet (GE) PHY interface, a 1.6 TE PHY interface and the like, and can adapt to the evolution of the Ethernet standard.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly relates to a data processing method and apparatus. Background Art

[0002] In the field of communication, in order to implement functions such as multi-channel alignment and code block delimit in the physical layer (PHY), the Ethernet technology will insert alignment markers (AM). Specifically, the PHY interface at the sending end periodically inserts AM code blocks into the data stream and sends the data stream containing the AM code blocks; after the PHY interface at the receiving end receives the data stream containing the AM code blocks, it will find and delete the AM code blocks in the data stream, and then send the remaining code blocks to the upper layer for processing. Generally, PHY interfaces with different rates insert AM code blocks into the data stream at different ratios. For example, according to the current standard, the AM insertion ratio of a 100 gigabit Ethernet (GE) PHY interface is 1 / 16384 (that is, the PHY interface with a rate of 100GE inserts one AM code block every 16383 code blocks in the data stream), and the AM insertion ratios of 50GE, 200GE, 400GE, and 800GE PHY interfaces are all 1 / 20480, and the AM insertion ratio of a 1.6 terabit Ethernet (TE) PHY interface is 1 / 81920.

[0003] The flexible Ethernet (FlexE) protocol is a standard protocol defined by the Optical Internetworking Forum (OIF) standardization organization. The FlexE protocol introduces the concept of a FlexE port. A FlexE port includes several 50GE PHY interfaces, 100GE PHY interfaces, 200GE PHY interfaces, and / or 400GE PHY interfaces, and may also include 800GE PHY interfaces, 1.6TE PHY interfaces, etc. in the future. The available bandwidth of a FlexE port is the sum of the available bandwidths provided by the PHY interfaces in the FlexE port to the FlexE port. The available bandwidth provided by a PHY interface to a FlexE port is the bandwidth of the PHY interface after deducting the AM overhead (i.e., the bandwidth occupied by the AM code block). Since the AM insertion ratios of PHY interfaces with different rates are different, the available bandwidths provided by PHY interfaces with different rates to a FlexE port are different. In order for FlexE ports composed of PHY interfaces with different rates to communicate with each other, it is necessary to insert padding (pad) code blocks into the data stream sent by the FlexE port with a larger available bandwidth to occupy positions, thereby reducing the available bandwidth of the FlexE port.

[0004] In the method for inserting padding code blocks defined by the current FlexE standard, the sender inserts two padding code blocks into the data stream every 163,830 code blocks. However, the method for inserting padding code blocks defined by the current FlexE standard is mainly for 50GE PHY interfaces, 200GE PHY interfaces, and 400GE PHY interfaces. With the evolution of the Ethernet standard, the rates of PHY interfaces are increasing continuously to 800GE, 1.6TE, etc. The method for inserting padding code blocks defined by the current FlexE standard is difficult to apply to PHY interfaces with higher rates such as 800GE PHY interfaces and 1.6TE PHY interfaces. Summary of the Invention

[0005] This application provides a data processing method and device. The technical solution of this application is applicable to FlexE, can insert more padding code blocks into the data stream, is applicable to PHY interfaces with higher rates such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of the Ethernet standard. The solution of this application is as follows.

[0006] In a first aspect, a data processing method is provided, which is applied to FlexE. The method includes: receiving an initial data stream sent by a FlexE instance; periodically inserting a padding sequence into the initial data stream to obtain a first data stream, the first data stream includes the periodically occurring padding sequence, the padding sequence includes n consecutive padding code blocks, and n is an integer greater than or equal to 4.

[0007] Among them, the data processing method can be executed by the FlexE shim at the sending end, specifically by the pad processing module in the FlexE shim.

[0008] In the technical solution provided by this application, the stuffing sequence periodically inserted in the initial data stream includes consecutive n stuffing code blocks, where n is an integer greater than or equal to 4. It can be seen that this application provides a method for inserting more stuffing code blocks into the data stream for FlexE, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0009] In a second aspect, a data processing method is provided, which is applied to FlexE. The method includes: receiving an initial data stream, which is obtained by interleaving multiple data streams sent by multiple FlexE instances; periodically inserting a stuffing sequence into the initial data stream to obtain a first data stream, the first data stream includes the periodically appearing stuffing sequence, the stuffing sequence includes consecutive n stuffing code blocks, and n is an integer greater than or equal to 16.

[0010] Among them, the data processing method can be executed by the FlexE shim at the sending end, specifically by the pad processing module in the FlexE shim.

[0011] In the technical solution provided by this application, the stuffing sequence periodically inserted in the initial data stream includes consecutive n stuffing code blocks, and n is an integer greater than or equal to 16. It can be seen that this application provides a method for inserting more stuffing code blocks into the data stream for FlexE, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0012] Optionally, in the above first aspect and second aspect, the n stuffing code blocks include x first stuffing code blocks and y second stuffing code blocks. The first stuffing code block is a control code block that is globally unique in the first data stream, and the second stuffing code block is an error code block. x is a positive integer, and y is a positive integer. For example, the first stuffing code block is the P1 code block in the current FlexE standard, and the second stuffing code block is the P2 code block in the current FlexE standard.

[0013] In the technical solution provided by this application, since the padding sequence inserted by the FlexE shim at the sending end in the initial data stream includes a globally unique first padding code block, it is convenient for the FlexE shim at the receiving end to find the first padding code block, and then find the padding sequence based on the first padding code block. Since the first padding code block is the P1 code block in the current FlexE standard and the second padding code block is the P2 code block in the current FlexE standard, the technical solution provided by this application can preferably inherit the pad encapsulation format of the current FlexE standard and is simple to implement.

[0014] Optionally, in the first aspect and the second aspect, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the x first padding code blocks and the y second padding code blocks satisfy any one of the following:

[0015] x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0016] n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or,

[0017] n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group includes a first padding code block and a second padding code block, in each code block group, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or,

[0018] The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks, the y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks, the x1 first padding code blocks, the y second padding code blocks and the x2 first padding code blocks are consecutive, x1 + x2 = x, and both x1 and x2 are positive integers.

[0019] Optionally, in the first aspect and the second aspect, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0020] The y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks and the z third padding code blocks are consecutive; or,

[0021] The z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive.

[0022] Optionally, in the above first aspect and second aspect, the third padding code block is a data code block.

[0023] In the technical solution provided by this application, since the third padding code block is a data code block, while the first padding code block and the second padding code block are both control code blocks, therefore, in the case where n consecutive padding code blocks in the padding sequence include x first padding code blocks, y second padding code blocks, and z third padding code blocks, setting the z third padding code blocks between the x first padding code blocks and the y second padding code blocks makes the z third padding code blocks not adjacent to the actual data code blocks in the first data stream, which can avoid confusion between the third padding code blocks and the actual data code blocks in the first data stream, and thus can avoid the third padding code blocks from contaminating the actual data code blocks in the first data stream.

[0024] Optionally, in the above first aspect and second aspect, the third padding code block includes at least one code block identifier. For example, the at least one code block identifier is multiple code block identifiers.

[0025] In the technical solution provided by this application, since the third padding code block includes at least one code block identifier, when the FlexE shim at the receiving end is looking for the third padding code block, it only needs to identify the code block identifier in the third padding code block to identify the third padding code block, which can simplify the process of the FlexE shim at the receiving end looking for the third padding code block. In the case where the third padding code block includes multiple code block identifiers, even if some of the identifiers in the multiple code block identifiers are in error during the transmission of the third padding code block, the FlexE shim at the receiving end can still find the third padding code block based on the correct code block identifiers in the multiple code block identifiers, which can improve the fault tolerance of the FlexE shim at the receiving end in looking for the third padding code block.

[0026] This application reduces the dependency relationship between the padding code blocks in the padding sequence by setting that the third padding code block includes a code block identifier. Even if some padding code blocks in the padding sequence are in error, it does not affect the FlexE shim at the receiving end from looking for the padding sequence in the first data stream.

[0027] Optionally, in the above first aspect and second aspect, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier in the third padding code block. That is, the third padding code block includes at least one code block identifier and at least one check identifier. For example, the third padding code block includes multiple code block identifiers and multiple check identifiers.

[0028] Since the third padding code block provided by the present application includes at least one code block identifier and at least one check identifier, when the FlexE shim at the receiving end is searching for the third padding code block, it can verify the correctness of the at least one code block identifier based on the at least one check identifier, and then identify the third padding code block based on the correct code block identifier among the at least one check identifier, which can simplify the process of the FlexE shim at the receiving end searching for the third padding code block. When the third padding code block includes multiple code block identifiers and multiple check identifiers, even if some of the multiple code block identifiers and / or the multiple check identifiers have error codes during the transmission of the third padding code block, the FlexE shim at the receiving end can still verify the correctness of the multiple code block identifiers based on the correct check identifiers among the multiple check identifiers, and then find the third padding code block based on the correct code block identifiers among the multiple code block identifiers, improving the fault tolerance of the FlexE shim at the receiving end in searching for the third padding code block.

[0029] Optionally, in the first aspect and the second aspect, in the third padding code block, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd.

[0030] In the technical solution provided by this application, setting the number of block identifiers in the third padding code block to be equal to the number of check identifiers, or the sum of the number of block identifiers and the number of check identifiers being odd, can facilitate the FlexE shim at the receiving end to find the third padding code block. For example, for any third padding code block, when the number of block identifiers in the third padding code block is equal to the number of check identifiers, the block identifiers and check identifiers in the third padding code block can be in one-to-one correspondence, and each check identifier is used to verify the correctness of the corresponding block identifier. When at least one block identifier in the third padding code block is successfully verified by the FlexE shim at the receiving end, the FlexE shim at the receiving end considers the at least one block identifier to be correct, and the FlexE shim at the receiving end then considers that the third padding code block has been successfully identified, that is, it is considered that the third padding code block has been found. For another example, for any third padding code block, when the sum of the number of block identifiers and the number of check identifiers in the third padding code block is odd, during the process of the FlexE shim at the receiving end looking for the third padding code block, if the FlexE shim at the receiving end determines that the sum of the number of correct block identifiers and the number of correct check identifiers in the third padding code block exceeds half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block, the FlexE shim at the receiving end then considers that the third padding code block has been successfully identified, that is, it is considered that the third padding code block has been found. Optionally, when the sum of the number of block identifiers and the number of check identifiers in the third padding code block is odd, half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block is not an integer. In this case, the ceiling of half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block can be taken for identification and judgment.

[0031] In a third aspect, a data processing method is provided, which is applied to FlexE. The method includes: obtaining a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, and the first data stream includes a periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 4; looking for padding code blocks in the first data stream to find the padding sequence; and determining that the padding sequence has been found when multiple consecutive padding code blocks found in the first data stream meet a preset condition, where the preset condition includes: the number of the multiple padding code blocks is greater than a preset threshold and the number of the multiple padding code blocks is less than or equal to n.

[0032] Among them, the data processing method can be executed by the FlexE shim at the receiving end, specifically by the pad processing module in the FlexE shim.

[0033] In the technical solution provided by this application, since the first data stream includes a periodically occurring padding sequence, and this padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 4, this application provides a method for FlexE-oriented that can insert more padding code blocks into the data stream, which can be applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards. Since the FlexE shim at the receiving end determines that the padding sequence is found when the number of consecutive padding code blocks found in the first data stream is greater than a preset threshold and less than or equal to n, rather than the number of consecutive padding code blocks found must be equal to n, that is, it is not necessary for all padding code blocks in the padding sequence to be detected correctly, this application provides a method for finding the padding sequence in a soft decision manner. The process of the FlexE shim at the receiving end finding the padding sequence is relatively relaxed, the fault tolerance ability of finding the padding sequence is good, and the probability of successfully finding the padding sequence can be maintained without deterioration.

[0034] Fourthly, a data processing method is provided, which is applied to FlexE. The method includes: obtaining a first data stream, where the first data stream is obtained by periodically inserting a padding sequence into an initial data stream, and the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances. The first data stream includes the periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 16; finding padding code blocks in the first data stream to find the padding sequence; determining that the padding sequence is found when the number of consecutive padding code blocks found in the first data stream meets a preset condition, and the preset condition includes: the number of the padding code blocks is greater than a preset threshold and the number of the padding code blocks is less than or equal to n.

[0035] Among them, this data processing method can be executed by the FlexE shim at the receiving end, specifically executed by the pad processing module in the FlexE shim.

[0036] The technical solution provided by this application, since the first data stream includes a periodically occurring padding sequence, and the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16, this application provides a method for FlexE-oriented that can insert more padding code blocks into the data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards. Since the FlexE shim at the receiving end determines that the padding sequence is found when the number of multiple padding code blocks continuously found in the first data stream is greater than a preset threshold and less than or equal to n, rather than the number of multiple padding code blocks continuously found must be equal to n, that is, it is not necessary for all padding code blocks in the padding sequence to be detected correctly. Therefore, this application provides a method for finding the padding sequence in a soft decision manner. The process of the FlexE shim at the receiving end finding the padding sequence is relatively relaxed, the fault tolerance of finding the padding sequence is better, and the probability of successfully finding the padding sequence can be maintained without deterioration.

[0037] Optionally, in the above third and fourth aspects, the n padding code blocks include x first padding code blocks and y second padding code blocks. The first padding code block is a control code block that is globally unique in the first data stream, and the second padding code block is an error code block. x is a positive integer, and y is a positive integer.

[0038] Optionally, in the above third and fourth aspects, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the x first padding code blocks and the y second padding code blocks satisfy any one of the following:

[0039] x = 1, y = n - 1. The y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0040] n is an even number, x = y = n / 2. The y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or,

[0041] n is an even number, x = y = n / 2. The padding sequence includes n / 2 code block groups, each code block group includes a first padding code block and a second padding code block. In each code block group, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or,

[0042] The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks. The y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks. The x1 first padding code blocks, the y second padding code blocks, and the x2 first padding code blocks are consecutive, where x1 + x2 = x, and both x1 and x2 are positive integers.

[0043] Optionally, in the above third and fourth aspects, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0044] The y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks, and the z third padding code blocks are consecutive; or,

[0045] The z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive.

[0046] Optionally, in the above third and fourth aspects, the third padding code blocks are data code blocks.

[0047] Optionally, in the above third and fourth aspects, the third padding code blocks include at least one code block identifier.

[0048] Optionally, in the above third and fourth aspects, the third padding code blocks further include at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

[0049] Optionally, in the above third and fourth aspects, in the third padding code blocks, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd.

[0050] Optionally, in the above third and fourth aspects, the n padding code blocks include x first padding code blocks, and the first padding code blocks are control code blocks that are globally unique in the first data stream. x is a positive integer. Finding the padding code blocks in the first data stream to find the padding sequence includes: finding the first padding code blocks in the first data stream; and based on the first padding code blocks found in the first data stream, finding the padding sequence in the first data stream.

[0051] Optionally, in the above third and fourth aspects, finding the filling sequence in the first data stream based on the first filling code block found in the first data stream includes: determining n-1 code blocks after the first first filling code block found in the first data stream, where the n-1 code blocks are consecutive and the n-1 code blocks are consecutive with the first first filling code block; detecting the n-1 code blocks to find filling code blocks in the n-1 code blocks. Optionally, the multiple filling code blocks continuously found in the first data stream include the first first filling code block found in the first data stream and the filling code blocks found in the n-1 code blocks after the first first filling code block.

[0052] In the technical solution provided by this application, after the FlexE shim at the receiving end finds the first first filling code block in the first data stream, it searches for filling code blocks in the n-1 code blocks after the first first filling code block. This can avoid the length of the data segment between the first filling code block and the last filling code block among the multiple filling code blocks continuously found by the FlexE shim at the receiving end in the first data stream from being greater than n, that is, it can avoid that the multiple filling code blocks continuously found by the FlexE shim at the receiving end are not filling code blocks in the same filling sequence.

[0053] Optionally, detecting the n-1 code blocks to find filling code blocks in the n-1 code blocks includes: mapping the first first filling code block and the n-1 code blocks to a code block bitmap; detecting the n-1 code blocks based on the code block bitmap to find filling code blocks in the n-1 code blocks.

[0054] In the technical solution provided by this application, during each process of finding the filling sequence, the FlexE shim at the receiving end maps the first first filling code block found in the first data stream and the n-1 code blocks after the first first filling code block to the code block bitmap, and then searches for filling code blocks based on the code block bitmap, which can avoid that the multiple filling code blocks continuously found by the FlexE shim at the receiving end are not filling code blocks in the same filling sequence.

[0055] Optionally, the n filling code blocks include a third filling code block, and the third filling code block includes at least one code block identifier. Mapping the first first filling code block and the n-1 code blocks to the code block bitmap includes: mapping the third filling code block to the code block bitmap based on the code block identifier in the third filling code block.

[0056] In the technical solution provided by this application, since the third filling code block includes a code block identifier, the FlexE shim at the receiving end can conveniently map the third filling code block to the code block bitmap based on the code block identifier in the third filling code block.

[0057] Optionally, the third padding code block further includes at least one check identifier. Mapping the third padding code block to the code block bitmap based on the code block identifier in the third padding code block includes: verifying the correctness of the at least one code block identifier based on the at least one check identifier; mapping the third padding code block to the code block bitmap based on the correct code block identifiers among the at least one code block identifier.

[0058] In the technical solution provided by this application, since the third padding code block includes a check identifier, the FlexE shim at the receiving end can verify the correctness of the code block identifier in the third padding code block based on the check identifier in the third padding code block, which can prevent the FlexE shim at the receiving end from mapping the third padding code block to the code block bitmap based on an incorrect code block identifier, and improve the accuracy of the FlexE shim at the receiving end in mapping the third padding code block.

[0059] In a fifth aspect, a data processing device is provided, which is applied to FlexE. The data processing device includes at least one functional unit, and the at least one functional unit is used to execute the method provided in the first aspect or any optional manner of the first aspect. The at least one functional unit can be implemented based on software, hardware, or a combination of software and hardware, and the at least one functional unit can be combined or divided based on specific implementations.

[0060] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is used to execute the transceiver operations in the method provided in the first aspect or any optional manner of the first aspect, and the processing unit is used to execute operations other than the transceiver operations in the method provided in the first aspect or any optional manner of the first aspect.

[0061] Optionally, the transceiver unit is used to receive an initial data stream sent by a FlexE instance;

[0062] The processing unit is used to periodically insert a padding sequence into the initial data stream to obtain a first data stream, the first data stream includes the periodically occurring padding sequence, the padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 4.

[0063] In a sixth aspect, a data processing device is provided, which is applied to FlexE. The data processing device includes at least one functional unit, and the at least one functional unit is used to execute the method provided in the second aspect or any optional manner of the second aspect. The at least one functional unit can be implemented based on software, hardware, or a combination of software and hardware, and the at least one functional unit can be combined or divided based on specific implementations.

[0064] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the second aspect or any optional implementation manner of the second aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the second aspect or any optional implementation manner of the second aspect.

[0065] Optionally, the transceiver unit is configured to receive an initial data stream, which is obtained by interleaving multiple data streams sent to multiple FlexE instances;

[0066] The processing unit is configured to periodically insert a padding sequence into the initial data stream to obtain a first data stream, the first data stream includes the periodically occurring padding sequence, the padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 16.

[0067] Optionally, in the fifth and sixth aspects above, the n padding code blocks include x first padding code blocks and y second padding code blocks, the first padding code blocks are control code blocks that are globally unique in the first data stream, the second padding code blocks are error code blocks, x is a positive integer, and y is a positive integer.

[0068] Optionally, in the fifth and sixth aspects above, the x first padding code blocks and the y second padding code blocks satisfy any one of the following:

[0069] x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0070] n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or,

[0071] n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one first padding code block and one second padding code block, in each code block group, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or,

[0072] The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks. The y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks. The x1 first padding code blocks, the y second padding code blocks, and the x2 first padding code blocks are consecutive, where x1 + x2 = x, and both x1 and x2 are positive integers.

[0073] Optionally, in the above fifth and sixth aspects, the n padding code blocks further include z third padding code blocks, where z is a positive integer.

[0074] The y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks. The x first padding code blocks, the y second padding code blocks, and the z third padding code blocks are consecutive; or,

[0075] The z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks. The x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive.

[0076] Optionally, in the above fifth and sixth aspects, the third padding code block is a data code block.

[0077] Optionally, in the above fifth and sixth aspects, the third padding code block includes at least one code block identifier.

[0078] Optionally, in the above fifth and sixth aspects, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

[0079] Optionally, in the above fifth and sixth aspects, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd.

[0080] In a seventh aspect, a data processing device is provided, which is applied to FlexE. The data processing device includes at least one functional unit, and the at least one functional unit is used to execute the method provided in the above third aspect or any optional manner of the third aspect. The at least one functional unit can be implemented based on software, hardware, or a combination of software and hardware, and the at least one functional unit can be combined or divided based on specific implementations.

[0081] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the above-mentioned third aspect or any optional implementation manner of the third aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the above-mentioned third aspect or any optional implementation manner of the third aspect.

[0082] Optionally, the transceiver unit is configured to obtain a first data stream, where the first data stream is one of the multiplexed data streams obtained by deinterleaving, and the first data stream includes a periodically occurring padding sequence, and the padding sequence includes n consecutive padding code blocks, and n is an integer greater than or equal to 4;

[0083] The processing unit is configured to search for padding code blocks in the first data stream to search for the padding sequence; and, to determine that the padding sequence is found when a plurality of continuously found padding code blocks in the first data stream meet a preset condition, where the preset condition includes: the number of the plurality of padding code blocks is greater than a preset threshold and the number of the plurality of padding code blocks is less than or equal to n.

[0084] In an eighth aspect, a data processing device is provided, which is applied to FlexE. The data processing device includes at least one functional unit, and the at least one functional unit is configured to perform the method provided in the above-mentioned fourth aspect or any optional implementation manner of the fourth aspect. The at least one functional unit may be implemented based on software, hardware, or a combination of software and hardware, and the at least one functional unit may be combined or divided based on specific implementations.

[0085] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the above-mentioned third aspect or any optional implementation manner of the third aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the above-mentioned fourth aspect or any optional implementation manner of the fourth aspect.

[0086] Optionally, the transceiver unit is configured to obtain a first data stream, where the first data stream is obtained by periodically inserting a padding sequence into an initial data stream, the initial data stream is obtained by interleaving multiplexed data streams sent by multiple FlexE instances, the first data stream includes the periodically occurring padding sequence, and the padding sequence includes n consecutive padding code blocks, and n is an integer greater than or equal to 16;

[0087] The processing unit is configured to find a padding code block in the first data stream to find the padding sequence; and, to determine that the padding sequence is found when a plurality of consecutively found padding code blocks in the first data stream meet a preset condition, where the preset condition includes: the number of the plurality of padding code blocks is greater than a preset threshold and the number of the plurality of padding code blocks is less than or equal to n.

[0088] Optionally, in the above seventh and eighth aspects, the n padding code blocks include x first padding code blocks and y second padding code blocks, where the first padding code block is a control code block that is globally unique in the first data stream, the second padding code block is an error code block, x is a positive integer, and y is a positive integer.

[0089] Optionally, in the above seventh and eighth aspects, the x first padding code blocks and the y second padding code blocks satisfy any one of the following:

[0090] x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0091] n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or,

[0092] n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one first padding code block and one second padding code block, in each code block group, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or,

[0093] The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks, the y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks, the x1 first padding code blocks, the y second padding code blocks, and the x2 first padding code blocks are consecutive, x1 + x2 = x, and both x1 and x2 are positive integers.

[0094] Optionally, in the above seventh and eighth aspects, the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0095] The y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks, and the z third padding code blocks are consecutive; or,

[0096] The z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive.

[0097] Optionally, in the above seventh and eighth aspects, the third padding code block is a data code block.

[0098] Optionally, in the above seventh and eighth aspects, the third padding code block includes at least one code block identifier.

[0099] Optionally, in the above seventh and eighth aspects, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

[0100] Optionally, in the above seventh and eighth aspects, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd.

[0101] Optionally, in the above seventh and eighth aspects, the n padding code blocks include x first padding code blocks, the first padding code blocks are control code blocks that are globally unique in the first data stream, x is a positive integer, and the processing module is configured to: find the first padding code blocks in the first data stream; and find the padding sequence in the first data stream based on the first padding code blocks found in the first data stream.

[0102] Optionally, in the above seventh and eighth aspects, the processing module is configured to: determine n - 1 code blocks after the first found first padding code block in the first data stream, the n - 1 code blocks are consecutive, and the n - 1 code blocks are consecutive with the first found first padding code block; and detect the n - 1 code blocks to find padding code blocks in the n - 1 code blocks.

[0103] Optionally, in the above seventh and eighth aspects, the processing module is configured to: map the first found first padding code block and the n - 1 code blocks to a code block bitmap; and detect the n - 1 code blocks based on the code block bitmap to find padding code blocks in the n - 1 code blocks.

[0104] Optionally, in the above seventh and eighth aspects, the n padding code blocks include third padding code blocks, the third padding code blocks include at least one code block identifier, and the processing module is configured to map the third padding code blocks to the code block bitmap based on the code block identifiers in the third padding code blocks.

[0105] Optionally, in the above seventh aspect and eighth aspect, the third padding code block further includes at least one check identifier, and the processing module is configured to: verify the correctness of the at least one code block identifier based on the at least one check identifier; map the third padding code block to the code block bitmap based on the correct code block identifiers among the at least one code block identifier.

[0106] In a ninth aspect, a data processing apparatus is provided, including a memory and a processor; the memory is used for storing a computer program; the processor is configured to execute the computer program stored in the memory so that the data processing apparatus executes the method provided in the above first aspect or any optional manner of the first aspect, or executes the method provided in the above second aspect or any optional manner of the second aspect, or executes the method provided in the above third aspect or any optional manner of the third aspect, or executes the method provided in the above fourth aspect or any optional manner of the fourth aspect.

[0107] In a tenth aspect, a communication system is provided, and the communication system includes a sending end and a receiving end. The sending end includes the data processing apparatus provided in the above fifth aspect, any optional manner of the fifth aspect, sixth aspect, any optional manner of the sixth aspect, or ninth aspect. The receiving end includes the data processing apparatus provided in the above seventh aspect, any optional manner of the seventh aspect, eighth aspect, any optional manner of the eighth aspect, or ninth aspect.

[0108] In an eleventh aspect, a computer-readable storage medium is provided, in which a computer program is stored, and when the computer program is executed, it implements the method provided in the above first aspect or any optional manner of the first aspect, or implements the method provided in the above second aspect or any optional manner of the second aspect, or implements the method provided in the above third aspect or any optional manner of the third aspect, or implements the method provided in the above fourth aspect or any optional manner of the fourth aspect.

[0109] In a twelfth aspect, a computer program product is provided, and the computer program product includes a program or code, and when the program or code is executed, it implements the method provided in the above first aspect or any optional manner of the first aspect, or implements the method provided in the above second aspect or any optional manner of the second aspect, or implements the method provided in the above third aspect or any optional manner of the third aspect, or implements the method provided in the above fourth aspect or any optional manner of the fourth aspect.

[0110] In a thirteenth aspect, a chip is provided, which includes a programmable logic circuit and / or program instructions. When the chip runs, it is used to implement the method provided in the first aspect or any optional manner of the first aspect, or to implement the method provided in the second aspect or any optional manner of the second aspect, or to implement the method provided in the third aspect or any optional manner of the third aspect, or to implement the method provided in the fourth aspect or any optional manner of the fourth aspect.

[0111] Optionally, the chip is a FlexE shim.

[0112] For the technical effects of the second aspect to the thirteenth aspect, reference may be made to the technical effects of the first aspect, which will not be elaborated here. Description of the Drawings

[0113] Figure 1 is an architecture diagram of a FlexE protocol provided by an embodiment of the present application;

[0114] Figure 2 is a schematic diagram of a switch provided by an embodiment of the present application;

[0115] Figure 3 is a schematic diagram of the bandwidth of a FlexE port provided by an embodiment of the present application;

[0116] Figure 4 is a schematic diagram of a data stream including padding code blocks provided by an embodiment of the present application;

[0117] Figure 5 is a schematic diagram of a P1 code block provided by an embodiment of the present application;

[0118] Figure 6 is a schematic diagram of a P2 code block provided by an embodiment of the present application;

[0119] Figure 7 is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0120] Figure 8 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0121] Figure 9 is a schematic diagram of yet another application scenario provided by an embodiment of the present application;

[0122] Figure 10 is a flowchart of a data processing method provided by an embodiment of the present application;

[0123] Figure 11 is a schematic diagram of a schematic diagram of a third padding code block provided by an embodiment of the present application;

[0124] Figure 12 It is a schematic diagram of another third filling code block provided by an embodiment of the present application;

[0125] Figure 13 It is a schematic diagram of yet another third filling code block provided by an embodiment of the present application;

[0126] Figure 14 It is a schematic diagram of yet another third filling code block provided by an embodiment of the present application;

[0127] Figure 15 It is a schematic diagram of a first data stream provided by an embodiment of the present application;

[0128] Figure 16 It is a schematic diagram of another first data stream provided by an embodiment of the present application;

[0129] Figure 17 It is a schematic diagram of yet another first data stream provided by an embodiment of the present application;

[0130] Figure 18 It is a schematic diagram of yet another first data stream provided by an embodiment of the present application;

[0131] Figure 19 It is a schematic diagram of yet another first data stream provided by an embodiment of the present application;

[0132] Figure 20 It is a schematic diagram of yet another first data stream provided by an embodiment of the present application;

[0133] Figure 21 It is a schematic diagram of yet another first data stream provided by an embodiment of the present application;

[0134] Figure 22 It is a flowchart of another data processing method provided by an embodiment of the present application;

[0135] Figure 23 It is a schematic diagram of a code block bitmap provided by an embodiment of the present application;

[0136] Figure 24 It is a flowchart of yet another data processing method provided by an embodiment of the present application;

[0137] Figure 25 It is a flowchart of yet another data processing method provided by an embodiment of the present application;

[0138] Figure 26 It is a schematic diagram of a data processing device provided by an embodiment of the present application;

[0139] Figure 27 It is a schematic diagram of another data processing device provided by an embodiment of the present application;

[0140] Figure 28 It is a schematic diagram of yet another data processing device provided by an embodiment of the present application;

[0141] Figure 29 It is a schematic diagram of another data processing device provided by an embodiment of the present application. Detailed implementation manners

[0142] The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0143] In the communication field, in order to implement functions such as multi-channel alignment and code block delimit in the physical layer (PHY), the Ethernet technology will insert alignment markers (AM). Specifically, the PHY interface at the sending end periodically inserts AM code blocks into the data stream and sends the data stream containing the AM code blocks; after the PHY interface at the receiving end receives the data stream containing the AM code blocks, it will find and delete the AM code blocks in the data stream, and then send the remaining code blocks to the upper layer for processing. Specifically, the PHY includes a physical coding sublayer (PCS), and the AM code blocks are inserted by the PCS at the sending end, and the AM code blocks are searched for and deleted by the PCS at the receiving end. Usually, the proportion of AM code blocks inserted into the data stream by PHY interfaces with different rates is different. For example, according to the current standard, the AM insertion proportion of the 100GE PHY interface is 1 / 16384, and the AM insertion proportions of the 50GE PHY interface, 200GE PHY interface, 400GE PHY interface, and 800GE PHY interface are all 1 / 20480, and the AM insertion proportion of the 1.6TE PHY interface is 1 / 81920.

[0144] The flexible Ethernet (FlexE) protocol is a standard protocol defined by the Optical Internetworking Forum (OIF) standardization organization. The FlexE protocol introduces the concept of a FlexE port, which is also known as a physical interface group, a physical link group, a PHY group, or a FlexE group, etc. A FlexE port includes several 50GE PHY interfaces, 100GE PHY interfaces, 200GE PHY interfaces, and / or 400GE PHY interfaces, and may also include higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces in the future. A FlexE port supports one or more FlexE instances. Each FlexE instance introduces a fixed periodic frame structure and performs time slot division based on the time-division multiplexing (TDM) mechanism. One or more time slots support an Ethernet data stream or carry a flexible Ethernet client (FlexE client) data stream. That is, an Ethernet data stream corresponds to one or more time slots, or a FlexE client data stream is carried by one or more time slots, and different FlexE client data streams are carried on different time slots. For example, for a 100 gigabits per second (Gbps) FlexE instance, its periodic frame structure includes 20 time slots, the bandwidth of each time slot is 5Gbps, each time slot has 1023×8 = 8184 66-bit transmission windows, and the bandwidth of each 66-bit transmission window is 5Gbps / 8184 = 0.61 million bits per second (Mbps).

[0145] The FlexE protocol realizes the decoupling of the rates between the medium access control (MAC) layer and the physical layer (PHY) by introducing a FlexE shim layer. That is, the rate of the MAC layer does not need to correspond one-to-one with the rate of the PHY. For example, Figure 1 is an architecture diagram of the FlexE protocol. As shown in Figure 1As shown, the FlexE protocol defines FlexE client, FlexE shim, and FlexE group (i.e., FlexE group, FlexE port). The FlexE client is for MAC layer services. The MAC layer services are data streams encoded using 64B / 66B. The data stream includes multiple code blocks each with a length of 66 bits. The rate of the MAC layer services is 10 Gbps, 40 Gbps, or m * 25 Gbps, where m is a positive integer. The FlexE group includes several PHY interfaces to provide greater bandwidth. The FlexE shim is used for multiplexing and demultiplexing data streams based on TDM technology. For example, the FlexE shim at the transmitting end is used for multiplexing data streams based on TDM technology, and the FlexE shim at the receiving end is used for demultiplexing data streams based on TDM technology. Exemplarily, Figure 1 p FlexE clients are shown, and it is shown that the FlexE group includes k PHY interfaces, where both p and k are positive integers. Each FlexE client represents a data stream encoded using 64B / 66B at the MAC layer. The rates of the p FlexE clients can be equal or unequal. As Figure 1 shown, the FlexE shim at the transmitting end is used to map the code blocks of the p FlexE clients to the FlexE group for transmission in a TDM manner, and the FlexE shim at the transmitting end is used to insert overhead (OH) code blocks encoded using 64B / 66B at fixed intervals in the code block stream (i.e., data stream) mixing the code blocks of the p FlexE clients. The OH code blocks are used by the FlexE shim at the receiving end for code block delimitating and demultiplexing. The FlexE shim at the receiving end is used to first lock and parse the OH code blocks after obtaining the code block stream mixing the code blocks of the p FlexE clients and inserted with OH code blocks, and then demultiplex the code blocks of each FlexE client based on the OH code blocks.

[0146] The current FlexE port can be composed of multiple 50GE PHY interfaces, or can be composed of multiple 100GE PHY interfaces, multiple 200GE PHY interfaces, or multiple 400GE PHY interfaces. In the future, the FlexE port may also be composed of 800GE PHY interfaces, 1.6TE PHY interfaces, or even higher-rate PHY interfaces. There is a need for docking between FlexE ports composed of PHY interfaces with different rates. To achieve intercommunication between FlexE ports composed of PHY interfaces with different rates, the available bandwidths of different FlexE ports composed of PHY interfaces with different rates need to be equal. Exemplarily, as Figure 2As shown, a switch supporting the FlexE function has an uplink FlexE port with 2 100GE PHY interfaces and a downlink FlexE port with 1 200GE PHY interface. The uplink FlexE port is docked with the downlink FlexE port through FlexE cross-connection. To enable communication between the uplink FlexE port and the downlink FlexE port, the available bandwidth of the uplink FlexE port needs to be equal to that of the downlink FlexE port. In fact, although PHY interfaces with different rates (such as 50GE, 100GE, 200GE, 400GE, 800GE, 1.6TE) show an integer multiple relationship in the nominal bandwidth, there are differences in the available bandwidth they provide to the FlexE port. Specifically, the available bandwidth provided by a PHY interface to a FlexE port is the bandwidth of the PHY interface minus the AM overhead, and the available bandwidth of a FlexE port is the sum of the available bandwidths provided by the PHY interfaces in the FlexE port to the FlexE port. Since the AM insertion ratios of PHY interfaces with different rates are different, the available bandwidths provided by PHY interfaces with different rates to the FlexE port are different. To enable communication between FlexE ports composed of PHY interfaces with different rates, that is, to make the available bandwidths of different FlexE ports composed of PHY interfaces with different rates equal, it is necessary to insert padding code blocks into the data stream sent by the FlexE port with a larger available bandwidth to occupy positions and reduce the available bandwidth of this FlexE port. For example, it is necessary to insert padding code blocks into the data stream sent by the downlink FlexE port of the switch shown in Figure 2 to occupy positions.

[0147] Exemplarily, 64 50GE PHY interfaces, 32 100GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, 4 800GE PHY interfaces, or 2 1.6TE PHY interfaces can all form a FlexE port with a total bandwidth of 3.2 terabits per second (Tbps). However, since the AM insertion ratio of 100GE PHY interfaces is 1 / 16384, the AM insertion ratios of 50GE PHY interfaces, 200GE PHY interfaces, 400GE PHY interfaces, and 800GE PHY interfaces are all 1 / 20480, and the AM insertion ratio of 1.6TE PHY interfaces is 1 / 81920. Therefore, the available bandwidths of the FlexE ports formed by 32 100GE PHY interfaces, the FlexE ports formed by 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces, and the available bandwidth of the FlexE port formed by 2 1.6TE PHY interfaces are all different. To make the available bandwidths of the FlexE ports formed by 32 100GE PHY interfaces, the FlexE ports formed by 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces, and the available bandwidth of the FlexE port formed by 2 1.6TE PHY interfaces equal, it is necessary to insert padding code blocks into the data streams sent by the FlexE ports formed by 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces, and it is also necessary to insert padding code blocks into the data streams sent by the FlexE port formed by 2 1.6TE PHY interfaces. Moreover, the ratio of inserting padding code blocks into the data streams sent by the FlexE port formed by 2 1.6TE PHY interfaces is higher than the ratio of inserting padding code blocks into the data streams sent by the FlexE ports formed by 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces. Exemplarily, such as Figure 3As shown, 32 100GE PHY interfaces, 4 800GE PHY interfaces, or 2 1.6TE PHY interfaces can all form a FlexE port with a total bandwidth of 3.2 Tbps. However, since the AM insertion ratio of 100GE PHY interfaces is higher than that of 800GE PHY interfaces, and the AM insertion ratio of 800GE PHY interfaces is higher than that of 1.6TE PHY interfaces, therefore, stuffing code blocks are inserted respectively in the data streams sent by the FlexE port composed of the 4 800GE PHY interfaces and the FlexE port composed of the 2 1.6TE PHY interfaces for placeholder, and the ratio of stuffing code blocks inserted in the data stream sent by the FlexE port composed of the 2 1.6TE PHY interfaces is higher than that inserted in the data stream sent by the FlexE port composed of the 4 800GE PHY interfaces. In this way, the available bandwidth of the FlexE port composed of the 2 1.6TE PHY interfaces and the available bandwidth of the FlexE port composed of the 4 800GE PHY interfaces are reduced, and the available bandwidth of the FlexE port composed of the 32 100GE PHY interfaces, the available bandwidth of the FlexE port composed of the 4 800GE PHY interfaces, and the available bandwidth of the FlexE port composed of the 2 1.6TE PHY interfaces are made equal, thus realizing the interconnection between the FlexE port composed of the 32 100GE PHY interfaces, the FlexE port composed of the 4 800GE PHY interfaces, and the FlexE port composed of the 2 1.6TE PHY interfaces.

[0148] In the current FlexE standard, specifically the FlexE 2.2 implementation agreement, the defined method for inserting stuffing code blocks and the method for detecting stuffing code blocks, the FlexE shim at the sending end inserts two stuffing code blocks into the data stream every 163,830 code blocks and sends the data stream containing the stuffing code blocks. After the FlexE shim at the receiving end receives the data stream containing the stuffing code blocks, the FlexE shim at the receiving end performs stuffing code block detection on the data stream to find the two stuffing code blocks. The FlexE shim at the receiving end determines that the detection is successful when both of the two stuffing code blocks are detected correctly, that is, the FlexE shim at the receiving end has found the two stuffing code blocks. Furthermore, the FlexE shim at the receiving end deletes the stuffing code blocks in the data stream, and then sends the remaining code blocks to the upper layer for processing. By way of example, Figure 4 shows the data stream after inserting stuffing code blocks using the method for inserting stuffing code blocks defined by the current FlexE standard. In this data stream, every 163,830 code blocks ( Figure 4For the sake of easy distinction, these 163,830 code blocks (referred to as data code blocks) have two padding code blocks, namely P1 code block and P2 code block respectively. The lengths of both the P1 code block and the P2 code block are 66 bits. The P1 code block is a control code block that is globally unique in the data stream, and the P2 code block is an error code block. After the FlexE shim at the receiving end receives the data stream containing the P1 code block and the P2 code block, the FlexE shim at the receiving end first detects and locks the globally unique P1 code block, and then detects whether the code block immediately adjacent to the locked P1 code block is the P2 code block. If the FlexE shim at the receiving end detects and determines that the code block immediately adjacent to the P1 code block is the P2 code block, the FlexE shim at the receiving end considers that both the P1 code block and the P2 code block are detected successfully. The FlexE shim at the receiving end deletes the P1 code block and the P2 code block from the data stream, and then sends the remaining code blocks to the upper layer for processing. If the FlexE shim at the receiving end detects and determines that the code block immediately adjacent to the P1 code block is not the P2 code block, the FlexE shim at the receiving end considers that the detection of the P2 code block fails. The FlexE shim at the receiving end re-detects and locks the P1 code block from the current detection position backward, and detects whether the code block immediately adjacent to the locked P1 code block is the P2 code block until the detection is successful.

[0149] As an example, please refer to Figure 5 which shows a schematic diagram of a P1 code block. The length of the P1 code block is 66 bits. The 1st to 2nd bits in the P1 code block represent the type of the P1 code block, and the value "10" of the 1st to 2nd bits indicates that the P1 code block is a control code block. The value "0x4B" of the 3rd to 10th bits in the P1 code block indicates that the 11th to 34th bits in the P1 code block are data information. The 35th to 38th bits in the P1 code block are a separator field, which is used to separate the data information of the 11th to 34th bits and the control information of the 39th to 66th bits. The value "0x5" of the 35th to 38th bits is a globally used value. When the value of the 35th to 38th bits is "0x5", the 11th to 14th bits reuse the value "0x0" in the FlexE standard, and the 15th to 34th bits reuse the value "0xF_FFFF" in the FlexE standard.

[0150] As an example, please refer to Figure 6, which shows a schematic diagram of a P2 code block. The length of the P2 code block is 66 bits. The 1st to 2nd bits in the P2 code block represent the type of the P2 code block, and the value "10" of the 1st to 2nd bits indicates that the P2 code block is a control code block. The 3rd to 10th bits in the P1 code block represent the specific type of the control code block, and the value "0x1E" of the 3rd to 10th bits indicates that the P2 code block is specifically an error code block. The values of the 11th to 17th bits, the 18th to 24th bits, the 25th to 31st bits, the 32nd to 38th bits, the 39th to 45th bits, the 46th to 52nd bits, the 53rd to 59th bits, and the 60th to 66th bits in the P2 code block are all "0x1E".

[0151] It should be noted that the bit positions in the P1 code block and the P2 code block are described in the order from high to low above. It is also possible to describe the bit positions in the P1 code block and the P2 code block in the order from low to high. No matter which order is used to describe the bit positions in the P1 code block and the P2 code block, it does not affect the meanings of the respective fields in the P1 code block and the respective fields in the P2 code block. In addition, only an exemplary introduction to the P1 code block and the P2 code block is provided in this article. For the specific introduction to the P1 code block and the P2 code block, please refer to the relevant standard documents.

[0152] The current insertion method of the padding code block defined by the FlexE standard is mainly for 50GE PHY interfaces, 200GE PHY interfaces, and 400GE PHY interfaces. With the evolution of the Ethernet standard, the rates of PHY interfaces are continuously increasing towards 800GE, 1.6TE, etc. The current insertion method of the padding code block defined by the FlexE standard is difficult to be applicable to higher-rate PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces. For example, according to the current FlexE standard, the number of padding code blocks to be inserted within a pad period (such as 163830 code blocks) is 2. With the evolution of the Ethernet standard, the FlexE port may include 800GE PHY interfaces and 1.6TE PHY interfaces, and the number of padding code blocks to be inserted within a pad period may evolve to 4, 8, 16, or even more. Therefore, a new insertion method needs to be provided to adapt to the evolution of the Ethernet standard.

[0153] In addition, in the detection method of the padding code blocks defined by the current FlexE standard, the receiving-end FlexE shim determines that the detection is successful only when all the padding code blocks inserted within a pad period are detected correctly (the receiving-end FlexE shim considers the detection successful only when it finds consecutive P1 and P2 code blocks), which results in poor fault tolerance of this detection method. Specifically, at the same bit error rate, that is, at the same probability of bit error (BER), as the number of padding code blocks inserted within a pad period increases, the probability of joint detection failure of multiple padding code blocks increases, leading to poor fault tolerance of this detection method. For example, according to the detection method of the padding code blocks defined by the current FlexE standard, when BER = 1×10 -13 , if the transmitting-end FlexE shim inserts 2 padding code blocks within a pad period, the receiving-end FlexE shim needs to jointly detect the padding code blocks with 2 code blocks. The probability of joint detection failure of 2 code blocks is approximately 1.3×10 -11 (the total length of the two code blocks is 66×2 = 132 bits. When 1 bit in these 132 bits is in error, the detection is considered a failure. So the probability of detection failure is 132×1×10 -13 , approximately equal to 1.3×10 -11 ). If the transmitting-end FlexE shim inserts 8 padding code blocks within a pad period, the receiving-end FlexE shim needs to jointly detect the padding code blocks with 8 code blocks. The probability of joint detection failure of 8 code blocks is approximately 5.3×10 -11 . If the transmitting-end FlexE shim inserts 16 padding code blocks within a pad period, the receiving-end FlexE shim needs to jointly detect the padding code blocks with 16 code blocks. The probability of joint detection failure of 16 code blocks is approximately 1×10 -10 . If the transmitting-end FlexE shim inserts 32 padding code blocks within a pad period, the receiving-end FlexE shim needs to jointly detect the padding code blocks with 32 code blocks. The probability of joint detection failure of 32 code blocks is approximately 2.1×10 -10 . If the transmitting-end FlexE shim inserts 64 padding code blocks within a pad period, the receiving-end FlexE shim needs to jointly detect the padding code blocks with 64 code blocks. The probability of joint detection failure of 64 code blocks is 4.2×10 -10 . If the transmitting-end FlexE shim inserts 128 padding code blocks within a pad period, the receiving-end FlexE shim needs to jointly detect the padding code blocks with 128 code blocks. The probability of detection failure of 128 code blocks is approximately 8.5×10 -10If the FlexE shim at the sending end inserts 256 padding code blocks within one pad period, the FlexE shim at the receiving end needs to jointly detect the padding code blocks from 256 code blocks. The probability of joint detection failure for 256 code blocks is approximately 1.7×10 -9 . It can be seen that as the number of padding code blocks inserted within one pad period increases, the probability of joint detection failure for multiple code blocks grows exponentially, which is likely to affect the normal operation of FlexE.

[0154] The embodiments of the present application provide a data processing method and apparatus, which are related to the insertion and detection (or searching and identification) of padding code blocks. In the data processing method provided by the embodiments of the present application, the FlexE shim at the sending end (specifically, the pad processing module in the FlexE shim at the sending end) periodically inserts a padding sequence into the initial data stream to obtain a first data stream, and the padding sequence includes n consecutive padding code blocks. After the FlexE shim at the receiving end (specifically, the pad processing module in the FlexE shim at the receiving end) obtains the first data stream, it searches for the padding code blocks in the first data stream to search for the padding sequence. When the number of multiple padding code blocks continuously found by the FlexE shim at the receiving end in the first data stream is greater than a preset threshold and less than or equal to n, it is determined that the padding sequence is found, that is, it is determined that the padding sequence detection is successful (or the pad detection is successful). n is an integer greater than or equal to 4, or n is an integer greater than or equal to 16. For example, when the initial data stream is the data stream of one FlexE instance in the FlexE shim at the sending end, n is an integer greater than or equal to 4. When the initial data stream is a data stream obtained by interleaving the multi-channel data streams of multiple FlexE instances in the FlexE shim at the sending end, n is an integer greater than or equal to 16. It can be seen that the embodiments of the present application provide a method for FlexE that can insert more padding code blocks into the data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6T E PHY interfaces, and can adapt to the evolution of Ethernet standards. Moreover, since the FlexE shim at the receiving end determines that the padding sequence is found, that is, the pad detection is successful, when the number of multiple padding code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n, without the number of multiple padding code blocks continuously found necessarily being equal to n, that is, without all the padding code blocks in the padding sequence being detected correctly, the process of the FlexE shim at the receiving end searching for the padding sequence is relatively loose, the fault tolerance ability of searching for the padding sequence is good, and the probability of successfully searching for the padding sequence can be maintained without deterioration.

[0155] The technical solution of the present application will be introduced below. First, the application scenario of the present application will be introduced.

[0156] Please refer to Figure 7 , which shows a schematic diagram of an application scenario of an embodiment of the present application. This application scenario provides a communication system. The communication system includes a sending end and a receiving end. The sending end and the receiving end are communicatively connected. For example, the sending end and the receiving end are connected by an optical fiber.

[0157] Specifically, both the sending end and the receiving end include PHY interfaces. The PHY interface of the sending end is connected to the PHY interface of the receiving end by an optical fiber. For example, the sending end includes a PHY interface with at least one rate among 50GE, 100GE, 200GE, 400GE, 800GE, and 1.6TE, and the receiving end includes a PHY interface with at least one rate among 50GE, 100GE, 200GE, 400GE, 800GE, and 1.6TE. As Figure 7 shown, both the sending end and the receiving end include a physical layer (also referred to as the PHY layer or PHY chip), and the PHY interface is located in the physical layer. The PHY interface includes a physical coding sublayer (PCS), a physical medium attachment (PMA), a physical medium dependent (PMD), etc. The sending end and the receiving end transmit data streams through the PHY interface. When the PHY interface of the sending end sends a data stream to the receiving end, it will periodically insert an AM code block into the data stream and send the data stream containing the AM code block. After the PHY interface of the receiving end receives the data stream containing the AM code block, it will find and delete the AM code block in the data stream, and then send the remaining code blocks to the upper layer for processing. In this way, functions such as multi-channel alignment and code block delimiters can be achieved at the physical layer through the AM code block. Among them, the AM insertion ratio of PHY interfaces with different rates is different. For example, according to the current standard, the AM insertion ratio of a 100GE PHY interface is 1 / 16384, and the AM insertion ratios of 50GE, 200GE, 400GE, and 800GE PHY interfaces are 1 / 20480, and the AM insertion ratio of a 1.6TE PHY interface is 1 / 81920.

[0158] In the embodiments of the present application, both the sending end and the receiving end support the FlexE function. Both the sending end and the receiving end include a FlexE shim and at least one FlexE port. One FlexE port includes at least one PHY interface. For example, one FlexE port is composed of multiple PHY interfaces. The available bandwidth of the FlexE port is the sum of the available bandwidths provided by the PHY interfaces in the FlexE port to the FlexE port. The available bandwidth provided by the PHY interface to the FlexE port is the bandwidth of the PHY interface minus the AM overhead. Since the AM insertion ratios of PHY interfaces with different rates are different, the available bandwidths provided by PHY interfaces with different rates to the FlexE port are different. As Figure 7 shown, both the sending end and the receiving end also include a MAC layer, and the FlexE shim is located between the MAC layer and the physical layer. The FlexE shim is used to implement communication between the MAC layer and the physical layer and to decouple the rates between the MAC layer and the physical layer. At the sending end, after the FlexE shim receives the data stream sent by the MAC layer, it processes the data stream and then sends the processed data stream to the physical layer. At the receiving end, after the FlexE shim receives the data stream sent by the physical layer, it processes the data stream and then sends the processed data stream to the MAC layer. Among them, the processing of the data stream sent by the MAC layer by the FlexE shim at the sending end includes slot mapping of the data stream, inserting padding code blocks into the data stream, interleaving multiple data streams, etc. The processing of the data stream sent by the physical layer by the FlexE shim at the receiving end includes deinterleaving the data stream, finding and deleting the padding code blocks in the data stream, slot demapping of the data stream, etc. As Figure 7 shown, in the embodiments of the present application, the FlexE shim at the sending end and the FlexE shim at the receiving end both include a pad processing module. The pad processing module in the FlexE shim at the sending end inserts padding code blocks into the data stream, and the pad processing module in the FlexE shim at the receiving end finds and deletes the padding code blocks in the data stream. The pad processing module in the FlexE shim at the sending end is also called a pad insertion module, and the pad processing module in the FlexE shim at the receiving end is also called a pad deletion module. Among them, the data stream exchanged between the MAC layer and the FlexE shim is also called a FlexE client data stream.

[0159] In the embodiment of the present application, the FlexE shim at the sending end may first insert padding code blocks into the data stream, and then perform interleaving on multiple data streams including the padding code blocks. Correspondingly, the FlexE shim at the receiving end may first perform deinterleaving on the data stream to obtain multiple data streams, and then search for and delete the padding code blocks in the multiple data streams. Alternatively, the FlexE shim at the sending end may first perform interleaving on multiple data streams, and then insert padding code blocks into the interleaved data stream. Correspondingly, the FlexE shim at the receiving end may first search for and delete the padding code blocks in the data stream, and then perform deinterleaving on the data stream after deleting the padding code blocks. Based on this, the application scenarios of the embodiment of the present application are introduced in two cases below.

[0160] The first case: The FlexE shim at the sending end first inserts padding code blocks into the data stream, and then performs interleaving on multiple data streams including the padding code blocks. Correspondingly, the FlexE shim at the receiving end first performs deinterleaving on the data stream to obtain multiple data streams, and then searches for and deletes the padding code blocks in the multiple data streams. Please refer to Figure 8 , which shows a schematic diagram of another application scenario provided by the embodiment of the present application. The communication system provided by this application scenario includes a sending end and a receiving end, and both the sending end and the receiving end include a MAC layer, a FlexE shim, and a physical layer.

[0161] As Figure 8 shown, the FlexE shim at the sending end includes an overhead (OH) processing module, a time slot allocation scheduler (calendar), p idle add / delete modules, multiple FlexE instances, multiple pad processing modules, and multiple interleaving modules, where p is a positive integer. The OH processing module, the p idle add / delete modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances. The multiple FlexE instances are connected to the multiple pad processing modules in a one-to-one correspondence. Each interleaving module is connected to at least two pad processing modules, and different interleaving modules are connected to different pad processing modules. Moreover, the interleaving module at the sending end is connected to the PHY interface at the sending end. For example, the multiple interleaving modules at the sending end are connected to the multiple PHY interfaces at the sending end in a one-to-one correspondence.

[0162] As Figure 8As shown in the figure, the FlexE shim of the receiving end includes an OH processing module, a time slot allocation scheduler, p idle addition / removal modules, multiple FlexE instances, multiple pad processing modules, and multiple deinterleaving modules. The OH processing module, the p idle addition / removal modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances. The multiple FlexE instances are connected to the multiple pad processing modules in a one-to-one correspondence. Each deinterleaving module among the multiple deinterleaving modules is connected to at least two pad processing modules, and different deinterleaving modules are connected to different pad processing modules. Moreover, the deinterleaving module of the receiving end is connected to the PHY interface of the receiving end. For example, the multiple deinterleaving modules of the receiving end are connected to the multiple PHY interfaces of the receiving end in a one-to-one correspondence.

[0163] As Figure 8 shown, the multiple PHY interfaces of the sending end are connected to the multiple PHY interfaces of the receiving end in a one-to-one correspondence.

[0164] As Figure 8 shown, FlexE client 1 to p are p data streams for interaction between the MAC layer and the FlexE shim. These p data streams are all data streams encoded with 64B / 66B. Each of these p data streams includes multiple code blocks with a length of 66 bits. The interleaving module in the FlexE shim of the sending end is also called a 66b interleaving module, and the deinterleaving module in the FlexE shim of the receiving end is also called a 66b deinterleaving module.

[0165] Referring to Figure 8 , the processing flow of the sending end includes: the MAC layer obtains p data streams (i.e., FlexE client 1 to p) and sends these p data streams to the FlexE shim; the FlexE shim processes these p data streams and sends the processed data streams to the physical layer; the physical layer performs some physical layer processing on the data stream sent by the FlexE shim (such as inserting AM code blocks into the data stream, etc.) and sends the processed data stream to the receiving end through the PHY interface.

[0166] Among them, referring to Figure 8 , the processing process of the FlexE shim of the sending end is as follows.

[0167] Each of the p idle addition / removal modules is used to: receive a data stream (FlexE client) sent by the MAC layer, perform idle addition / removal on the data stream (add idle code blocks or remove some code blocks in the data stream), and send the data stream after idle addition / removal to the time slot allocation scheduler. By performing idle addition / removal on the data stream, the rate of the data stream can be adapted to the rate of the time slot allocation scheduler.

[0168] The time slot allocation scheduler is used to: receive the p data streams sent by the p idle addition / removal modules, perform time slot mapping on the p data streams in the TDM manner to obtain multiple data streams mixed with code blocks of the p data streams (each data stream in the multiple data streams includes code blocks in the multiple data streams of the p data streams), insert OH code blocks into the multiple data streams under the control of the OH processing module, and send the multiple data streams after inserting OH code blocks to the multiple FlexE instances one by one.

[0169] Each of the multiple FlexE instances is used to: receive a data stream sent by the time slot allocation scheduler, perform sub-time slot mapping on the data stream in the TDM manner, insert OH code blocks into the data stream under the control of the OH processing module, and send the data stream after inserting OH code blocks to the corresponding pad processing module. Among them, the FlexE instance is also called a sub-time slot allocation scheduler (sub calendar), and the FlexE instance can be a 100GE FlexE instance, which is not limited in the embodiments of the present application.

[0170] Each of the multiple pad processing modules is used to: receive a data stream sent by the corresponding FlexE instance, periodically insert a padding sequence into the data stream, and send the data stream after inserting the padding sequence to the corresponding interleaving module. Among them, the padding sequence includes n consecutive padding code blocks. For Figure 8 the application scenario shown, n is an integer greater than or equal to 4.

[0171] Each of the multiple interleaving modules is used to: receive multiple data streams containing padding sequences sent by the corresponding multiple pad processing modules, perform interleaving on the multiple data streams to obtain an interleaved data stream, and send the one data stream to the physical layer.

[0172] Reference Figure 8, the processing flow of the receiving end includes: the physical layer receives the data stream through the PHY interface, the physical layer performs some physical layer processing on the data stream (such as deleting the AM code blocks in the data stream, etc.), and sends the processed data stream to the FlexE shim; the FlexE shim processes the data stream to obtain p data streams (i.e., FlexE client1 to p), and sends the p data streams to the MAC layer.

[0173] Among them, refer to Figure 8 , the processing process of the FlexE shim at the receiving end is as follows.

[0174] Each of the multiple deinterleaving modules is used to: receive the data stream sent by the physical layer, deinterleave the data stream to obtain multiple data streams, and send the multiple data streams to the corresponding multiple pad processing modules one by one.

[0175] Each of the multiple pad processing modules is used to: receive a data stream sent by the corresponding deinterleaving module, find and delete the padding sequence in the data stream, and send the data stream after deleting the padding sequence to the corresponding FlexE instance. Among them, the padding sequence includes n consecutive padding code blocks. For Figure 8 the application scenario shown, n is an integer greater than or equal to 4.

[0176] Each of the multiple FlexE instances is used to: receive a data stream sent by the corresponding pad processing module, find and delete the OH code blocks in the data stream under the control of the OH processing module, perform sub-slot demapping on the data stream in the TDM manner, and send the demapped data stream to the time slot allocation scheduler. Among them, the FlexE instance is also called a sub-slot allocation scheduler (sub calendar), and the FlexE instance can be a 100GE FlexE instance, which is not limited in the embodiments of the present application.

[0177] The time slot allocation scheduler is used to: receive the multiple data streams sent by the multiple FlexE instances, find and delete the OH code blocks in the multiple data streams under the control of the OH processing module, perform time slot demapping on the multiple data streams in the TDM manner to obtain p data streams, and send the p data streams to the p idle addition and deletion modules one by one.

[0178] Each of the p idle addition and deletion modules is used to: receive a data stream sent by the time slot allocation scheduler, perform idle addition and deletion (add idle code blocks or delete some code blocks in the data stream) on the data stream to obtain a FlexE client, and send the FlexE client to the MAC layer.

[0179] The second case: The FlexE shim at the sending end first interleaves multiple data streams, and then inserts padding code blocks into the interleaved data stream. Correspondingly, the FlexE shim at the receiving end first searches for and deletes the padding code blocks in the data stream, and then deinterleaves the data stream after deleting the padding code blocks. Please refer to Figure 9 , which shows a schematic diagram of another application scenario provided by the embodiments of the present application. The communication system provided by this application scenario includes a sending end and a receiving end, and both the sending end and the receiving end include a MAC layer, a FlexE shim, and a physical layer.

[0180] As Figure 9 shown, the FlexE shim at the sending end includes an OH processing module, a time slot allocation scheduler, p idle addition and deletion modules, multiple FlexE instances, multiple interleaving modules, and multiple pad processing modules, where p is a positive integer. The OH processing module, the p idle addition and deletion modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances. Each interleaving module is connected to at least two FlexE instances, different interleaving modules are connected to different FlexE instances, and the multiple interleaving modules are connected to the multiple pad processing modules in one-to-one correspondence. Moreover, the pad processing module at the sending end is connected to the PHY interface of the sending end. For example, the multiple pad processing modules at the sending end are connected to the multiple PHY interfaces of the sending end in one-to-one correspondence.

[0181] As Figure 9 shown, the FlexE shim at the receiving end includes an OH processing module, a time slot allocation scheduler, p idle addition and deletion modules, multiple FlexE instances, multiple deinterleaving modules, and multiple pad processing modules. The OH processing module, the p idle addition and deletion modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances. Each deinterleaving module in the multiple deinterleaving modules is connected to at least two FlexE instances, and different deinterleaving modules are connected to different FlexE instances. The multiple pad processing modules are connected to the multiple deinterleaving modules in one-to-one correspondence. Moreover, the pad processing module in the FlexE shim at the receiving end is connected to the PHY interface of the receiving end. For example, the multiple pad processing modules at the receiving end are connected to the multiple PHY interfaces of the receiving end in one-to-one correspondence.

[0182] As Figure 9 shown, the multiple PHY interfaces at the sending end are connected to the multiple PHY interfaces at the receiving end in one-to-one correspondence.

[0183] As Figure 9As shown, FlexE client 1 to p are p data streams for the MAC layer to interact with the FlexE shim. These p data streams are all data streams encoded using 64B / 66B. Each of these p data streams includes multiple code blocks with a length of 66 bits.

[0184] Reference Figure 9 , the processing flow of the sender includes: The MAC layer obtains p data streams (i.e., FlexE client 1 to p) and sends these p data streams to the FlexE shim; the FlexE shim processes these p data streams and sends the processed data stream to the physical layer; the physical layer performs some physical layer processing on the data stream sent by the FlexE shim (such as inserting AM code blocks into the data stream, etc.) and sends the processed data stream to the receiver through the PHY interface.

[0185] Among them, reference Figure 9 , the processing process of the FlexE shim at the sender is as follows.

[0186] Each of the p idle addition and deletion modules is used to: receive a data stream (FlexE client) sent by the MAC layer, perform idle addition and deletion on the data stream (add idle code blocks or delete some code blocks in the data stream), and send the data stream after idle addition and deletion to the time slot allocation scheduler. By performing idle addition and deletion on the data stream, the rate of the data stream can be adapted to the rate of the time slot allocation scheduler.

[0187] The time slot allocation scheduler is used to: receive the p data streams sent by the p idle addition and deletion modules, perform time slot mapping on these p data streams in the TDM manner to obtain multiple data streams mixed with the code blocks of these p data streams, insert OH code blocks into these multiple data streams respectively under the control of the OH processing module, and send the multiple data streams after inserting OH code blocks to the multiple FlexE instances one by one.

[0188] Each of the multiple FlexE instances is used to: receive a data stream sent by the time slot allocation scheduler, perform sub-time slot mapping on the data stream in the TDM manner, insert an OH code block into the data stream under the control of the OH processing module, and send the data stream after inserting the OH code block to the corresponding interleaving module. Among them, the FlexE instance is also called a sub-time slot allocation scheduler. The FlexE instance can be a 100GE FlexE instance, and the embodiments of the present application do not limit this.

[0189] Each interleaving module among the multiple interleaving modules is configured to: receive multiple data streams sent by corresponding multiple FlexE instances, interleave the multiple data streams to obtain one interleaved data stream, and send the one interleaved data stream to a corresponding pad processing module.

[0190] Each pad processing module among the multiple pad processing modules is configured to: receive one data stream sent by a corresponding interleaving module, periodically insert a padding sequence into the data stream, and send the data stream with the inserted padding sequence to the physical layer. Wherein, the padding sequence includes n consecutive padding code blocks, and for Figure 9 the application scenario shown, n is an integer greater than or equal to 16.

[0191] Refer to Figure 9 , the processing flow at the receiving end includes: the physical layer receives a data stream through a PHY interface, the physical layer performs some physical layer processing on the data stream (such as deleting AM code blocks in the data stream, etc.), and sends the processed data stream to the FlexE shim; the FlexE shim processes the data stream to obtain p data streams (i.e., FlexE client1 - p), and sends the p data streams to the MAC layer.

[0192] Among them, refer to Figure 9 , the processing process of the FlexE shim at the receiving end is as follows.

[0193] Each pad processing module among the multiple pad processing modules is configured to: receive the data stream sent by the physical layer, find and delete the padding sequence in the data stream, and send the data stream after deleting the padding sequence to a corresponding deinterleaving module. Wherein, the padding sequence includes n consecutive padding code blocks, and for Figure 9 the application scenario shown, n is an integer greater than or equal to 16.

[0194] Each deinterleaving module among the multiple deinterleaving modules is configured to: receive one data stream sent by a corresponding pad processing module, deinterleave the data stream to obtain multiple data streams, and send the multiple data streams to corresponding multiple FlexE instances one by one.

[0195] Each FlexE instance among the multiple FlexE instances is configured to: receive one data stream sent by a corresponding deinterleaving module, find and delete the OH code blocks in the data stream under the control of the OH processing module, perform sub - time - slot demapping on the data stream in a TDM manner, and send the demapped data stream to the time - slot allocation scheduler. Wherein, the FlexE instance is also called a sub - time - slot allocation scheduler, and the FlexE instance can be a 100GE FlexE instance, and the embodiments of the present application do not make limitations thereto.

[0196] The time slot allocation scheduler is used to: receive multiple data streams sent by multiple FlexE instances, search for and delete OH code blocks in the multiple data streams under the control of the OH processing module, perform time slot demapping on the multiple data streams in the TDM manner to obtain p data streams, and send the p data streams to p idle addition / removal modules one by one.

[0197] Each of the p idle addition / removal modules is used to: receive one data stream sent by the time slot allocation scheduler, perform idle addition / removal on the data stream (add idle code blocks or delete some code blocks in the data stream) to obtain one FlexE client, and send the FlexE client to the MAC layer.

[0198] Comparison Figure 8 and Figure 9 It can be seen that in the Figure 8 shown application scenario, at the sending end, the processing flow of the pad processing module (specifically the pad insertion module) is before the processing flow of the interleaving module, and at the receiving end, the processing flow of the deinterleaving module is before the processing flow of the pad processing module (specifically the pad deletion module). In the Figure 9 shown application scenario, at the sending end, the processing flow of the interleaving module is before the processing flow of the pad processing module (specifically the pad insertion module), and at the receiving end, the processing flow of the pad processing module (specifically the pad deletion module) is before the processing flow of the deinterleaving module. For the Figure 8 shown application scenario, at the sending end, the structures, periods, etc. of the padding sequences inserted by different pad processing modules connected to the same interleaving module in the data stream can be different. For example, different pad insertion modules can use different insertion methods among the multiple insertion methods provided in the embodiments of the present application (such as the insertion methods provided in the method embodiments below, such as Figures 15 to 21 the provided insertion method) to insert padding sequences in the data stream. Thus, the padding sequences included in the multiple data streams interleaved by the interleaving module can be different. For the Figure 9 shown application scenario, at the sending end, the structures, periods, etc. of the padding sequences inserted by different pad processing modules connected to different interleaving modules in the data stream can be different. For example, different pad processing modules can use different insertion methods among the multiple insertion methods provided in the embodiments of the present application to insert padding sequences in the data stream. It can be seen that the embodiments of the present application support the insertion of differentiated padding sequences, so that some pad processing modules can reduce the complexity in the function of inserting padding sequences, and some other pad processing modules can introduce slightly higher complexity in the function of inserting padding sequences to improve performance. The embodiments of the present application do not limit this.

[0199] It should be noted that both the sending end and the receiving end in the embodiments of the present application support the FlexE function. For example, both the sending end and the receiving end are forwarding devices, user terminal devices, or server devices that support the FlexE function. The forwarding device can be a router or a switch. For example, both the sending end and the receiving end are forwarding devices, user terminal devices, or server devices in a slicing packet network (SPN). In some embodiments, the sending end is also referred to as the sending end device, and the receiving end is also referred to as the receiving end device. In addition, the sending end and the receiving end are relative. In some embodiments, the sending end in the embodiments of the present application can also be used as the receiving end, and the receiving end in the embodiments of the present application can also be used as the sending end. The above descriptions of the sending end and the receiving end are merely exemplary. The sending end and the receiving end may also have other structures and / or functions not shown and / or described above. The embodiments of the present application do not limit this and will not elaborate here. In addition, the application scenarios shown above are only examples of the application scenarios of the embodiments of the present application and are not used to limit the application scenarios of the embodiments of the present application. The application scenarios of the embodiments of the present application can be flexibly adjusted as the business develops.

[0200] The above is the introduction of the application scenario of the present application. The following introduces the method embodiments of the present application.

[0201] Please refer to Figure 10 , which shows a flowchart of a data processing method provided by the embodiments of the present application. The data processing method is applied to FlexE. The data processing method is executed by the pad processing module in the FlexE shim in the sending end. Specifically, it is executed by the pad processing module in the FlexE shim. Optionally, the FlexE shim in the sending end includes multiple pad processing modules, and the data processing method is executed by any one of the multiple pad processing modules. By way of example, Figure 10 The data processing method shown is executed by Figure 8 Any one of the pad processing modules in the FlexE shim in the sending end shown. Refer to Figure 10 , the data processing method includes the following steps S1001 to S1002.

[0202] S1001. Receive the initial data stream sent by the FlexE instance.

[0203] In the FlexE shim of the sending end, the FlexE instance can send a data stream to the pad processing module, and the pad processing module receives the data stream sent by the FlexE instance. In order to facilitate distinction in this embodiment, the data stream sent by the FlexE instance to the pad processing module is referred to as the initial data stream.

[0204] S1002. Periodically insert a padding sequence into the initial data stream to obtain a first data stream. The first data stream includes the periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 4.

[0205] Among them, in the FlexE shim at the sending end, the pad processing module periodically inserts a padding sequence into the initial data stream, that is, the pad processing module inserts a padding sequence into the initial data stream every certain number of code blocks. Among them, the first data stream includes the periodically occurring padding sequence, and the period of the padding sequence appearing in the first data stream can be set according to the actual situation, and the embodiments of the present application do not limit this.

[0206] In the embodiments of the present application, the periodically occurring padding sequence in the first data stream includes consecutive n padding code blocks. The n padding code blocks are all code blocks encoded by 64B / 66B, and the length of each of the n padding code blocks is 66 bits. In an alternative embodiment, the n padding code blocks include a first padding code block and a second padding code block. The first padding code block is a control code block that is globally unique in the first data stream. The second padding code block is an error code block. By way of example, the first padding code block is the P1 code block as shown in Figure 5 and the second padding code block is the P2 code block as shown in Figure 6

[0207] In an alternative embodiment, the n padding code blocks further include at least one third padding code block, and the third padding code block is a data code block.

[0208] ​In an alternative embodiment, the third padding code block includes at least one code block identifier. The code block identifier included in any third padding code block is used to uniquely identify the third padding code block, and the code block identifier included in any third padding code block is used for the pad processing module in the FlexE shim at the receiving end to identify (or detect, find) the third padding code block. Among them, the code block identifier may include one or a combination of more of numbers, English letters, and American Standard Code for Information Interchange (ASCII) of Chinese characters. For example, the code block identifier may be numbers such as 1, 2, 3, 4, etc., or letters such as A, B, C, D, etc., or the ASCII of Chinese characters such as Jia, Yi, Bing, Ding, etc. The code block identifier may be a sequence number. Optionally, for any third padding code block, when the third padding code block includes multiple code block identifiers, the number of the multiple code block identifiers may be odd or even, and the multiple code block identifiers may be the same or different. The embodiments of the present application do not limit this. The embodiments of the present application set that the third padding code block includes multiple code block identifiers, which can avoid that during the transmission of the third padding code block, one or more of the code block identifiers in the third padding code block have error codes, resulting in the pad processing module in the FlexE shim at the receiving end being unable to identify the third padding code block. For example, if the third padding code block only includes one code block identifier and the code block identifier has an error during the transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end will not be able to identify the code block identifier and thus will not be able to identify the third padding code block. However, if the third padding code block includes multiple code block identifiers, as long as there is an error-free code block identifier in the third padding code block during the transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end can identify the error-free code block identifier and identify the third padding code block based on the error-free code block identifier.

[0209] In an alternative embodiment, the third padding code block further includes at least one check identifier. That is, the third padding code block includes at least one code block identifier and at least one check identifier, and the at least one check identifier is used to verify the correctness of the at least one code block identifier. Among them, the check identifier can be a cyclic redundancy check (CRC), or a bit-reversed code of the code block identifier (that is, the check identifier can be obtained by bit-reversing the code block identifier). For example, the code block identifier is a sequence number, and the bit-reversed code of the code block identifier is a bit-reversed sequence number. Optionally, for any third padding code block, when the third padding code block includes multiple check identifiers, the number of the multiple check identifiers can be odd or even, and the multiple check identifiers can be the same or different. The embodiments of the present application do not limit this. By setting that the third padding code block includes multiple check identifiers in the embodiments of the present application, it can be avoided that during the transmission of the third padding code block, one or more of the check identifiers in the third padding code block have error codes, resulting in the pad processing module in the FlexE shim at the receiving end being unable to verify the correctness of the code block identifier in the third padding code block. For example, if the third padding code block only includes one check identifier and this check identifier has an error code during the transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end will not be able to recognize this check identifier and thus will not be able to verify the correctness of the code block identifier in the third padding code block. However, if the third padding code block includes multiple check identifiers, as long as there is a check identifier that has not had an error code in the third padding code block during the transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end can recognize this check identifier that has not had an error code, and verify the correctness of the code block identifier in the third padding code block based on this check identifier that has not had an error code.

[0210] In an alternative embodiment, for any third padding code block, when the third padding code block includes at least one code block identifier and at least one check identifier: the number of the at least one code block identifier is equal to the number of the at least one check identifier. For example, the number of the at least one code block identifier and the number of the at least one check identifier are both 1, 2, 3, or 4. Alternatively, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd. For example, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is 3, 5, 7, etc. In the embodiments of the present application, setting the number of code block identifiers in the third padding code block to be equal to the number of check identifiers, or setting the sum of the number of code block identifiers and the number of check identifiers to be odd, can facilitate the pad processing module in the FlexE shim at the receiving end to identify the third padding code block. For example, for any third padding code block, when the number of code block identifiers in the third padding code block is equal to the number of check identifiers, the code block identifiers and the check identifiers in the third padding code block are in one-to-one correspondence, and each check identifier is used to verify the correctness of the corresponding code block identifier. When at least one code block identifier in the third padding code block is successfully verified by the pad processing module in the FlexE shim at the receiving end, the pad processing module in the FlexE shim at the receiving end considers the at least one code block identifier to be correct, and the pad processing module then considers that the third padding code block is successfully identified, that is, the pad processing module finds the third padding code block. It can be seen that when the number of code block identifiers in the third padding code block is equal to the number of check identifiers, the pad processing module in the FlexE shim at the receiving end can easily identify the third padding code block. For another example, for any third padding code block, when the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is odd, during the process of the pad processing module in the FlexE shim at the receiving end identifying (or detecting, searching for) the third padding code block, if the pad processing module determines that the sum of the number of correct code block identifiers and the number of correct check identifiers in the third padding code block exceeds half of the sum of the number of code block identifiers and the number of check identifiers in the third padding code block, the pad processing module then considers that the third padding code block is successfully identified, that is, the pad processing module finds the third padding code block. It can be seen that when the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is odd, the pad processing module in the FlexE shim at the receiving end can easily identify the third padding code block.Optionally, when the sum of the number of block identifiers and the number of check identifiers in the third padding code block is odd, half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block is not an integer. In this case, the ceiling of half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block can be used for identification and determination, and the embodiments of the present application do not limit this.

[0211] In an optional embodiment, in the third padding code block, the lengths of the block identifier and the check identifier are equal. For example, the lengths of both the block identifier and the check identifier are 8 bits.

[0212] As an example, please refer to Figure 11 , which shows a schematic diagram of a third padding code block provided by the embodiments of the present application. The length of the third padding code block is 66 bits. The 1st to 2nd bits in the third padding code block represent the type of the third padding code block, and the value "10" of the 1st to 2nd bits indicates that the third padding code block is a data code block. The 3rd to 10th bits in the third padding code block represent the block identifier of the third padding code block. The 59th to 66th bits in the third padding code block are the check identifier, and the check identifier is a CRC code. The part between the block identifier and the check identifier (i.e., the 11th to 58th bits) is a reserved field. Among them, the CRC code (i.e., the check identifier) is obtained by performing CRC calculation based on the block identifier. Since the check identifier is a CRC code, it is convenient for the pad processing module in the FlexE shim at the receiving end to use an encoder and a circuit, etc., to check the correctness of the block identifier in the third padding code block based on the CRC code.

[0213] As another example, please refer to Figure 12, which shows another schematic diagram of the third padding code block provided by the embodiment of the present application. The length of the third padding code block is 66 bits. The 1st to 2nd bits in the third padding code block represent the type of the third padding code block, and the value "10" of the 1st to 2nd bits indicates that the third padding code block is a data code block. The 3rd to 10th bits, the 11th to 18th bits, and the 19th to 26th bits in the third padding code block all represent the code block identifiers of the third padding code block. The third padding code block includes 3 code block identifiers, and the length of each code block identifier is 8 bits. The 3 code block identifiers can be the same or different. The 27th to 66th bits in the third padding code block are reserved fields. In this example, setting the third padding code block to include an odd number of code block identifiers can avoid the situation that during the transmission of the third padding code block, one or more of the code block identifiers in the third padding code block have bit errors, resulting in the pad processing module in the FlexE shim at the receiving end being unable to recognize the third padding code block. For example, during the process of the pad processing module in the FlexE shim at the receiving end recognizing (or detecting, searching for) the third padding code block, if the pad processing module determines that the number of correct code block identifiers in the third padding code block exceeds half of the total number of code block identifiers in the third padding code block, the pad processing module considers that the recognition of the third padding code block is successful, that is, the pad processing module finds the third padding code block. It can be seen that even if there are bit errors in some of the code block identifiers in the third padding code block, the pad processing module can still find the third padding code block. Optionally, when the number of code block identifiers in the third padding code block is odd, half of the number of code block identifiers in the third padding code block is not an integer, and the pad processing module in the FlexE shim at the receiving end can round up half of the number of code block identifiers in the third padding code block for recognition and judgment. The embodiment of the present application does not limit this.

[0214] As yet another example, please refer to Figure 13 , which shows another schematic diagram of the third padding code block provided by the embodiment of the present application. The length of the third padding code block is 66 bits. The 1st to 2nd bits in the third padding code block represent the type of the third padding code block, and the value "10" of the 1st to 2nd bits indicates that the third padding code block is a data code block. The 3rd to 10th bits, the 11th to 18th bits, the 19th to 26th bits, and the 27th to 34th bits in the third padding code block all represent the code block identifiers of the third padding code block. The 35th to 42nd bits, the 43rd to 50th bits, the 51st to 58th bits, and the 59th to 66th bits in the third padding code block all represent parity identifiers, and the parity identifier is the bit flip code of the code block identifier. Figure 13The third padding code block shown includes 4 code block identifiers and 4 check identifiers. The length of each code block identifier is 8 bits, and the 4 code block identifiers can be the same or different. The length of each check identifier is 8 bits, and the 4 check identifiers can be the same or different. Figure 13 The number of code block identifiers in the third padding code block shown is equal to the number of check identifiers. Optionally, the 4 code block identifiers correspond one-to-one with the 4 code block identifiers. Each check identifier is the bit flip code of the corresponding code block identifier. Each check identifier is used to check the correctness of the corresponding code block identifier. When at least one of the 4 code block identifiers is successfully checked by the pad processing module in the FlexE shim at the receiving end, the pad processing module in the FlexE shim at the receiving end considers the at least one code block identifier to be correct. The pad processing module then considers that the third padding code block has been successfully recognized, that is, the pad processing module has found the third padding code block. It can be seen that the equal number of code block identifiers and check identifiers in the third padding code block facilitates the pad processing module in the FlexE shim at the receiving end to identify the third padding code block.

[0215] As another example, please refer to Figure 14 , which shows a schematic diagram of another third padding code block provided by an embodiment of the present application. The length of the third padding code block is 66 bits. The 1st to 2nd bits in the third padding code block represent the type of the third padding code block. The value "10" of the 1st to 2nd bits indicates that the third padding code block is a data code block. The 3rd to 10th bits, 11th to 18th bits, and 19th to 26th bits in the third padding code block all represent the code block identifiers of the third padding code block. The 27th to 34th bits and 35th to 42nd bits in the third padding code block both represent check identifiers, and the check identifier is the bit flip code of the code block identifier. The 43rd to 66th bits in the third padding code block are reserved fields. Figure 14 The third padding code block shown includes 3 code block identifiers and 2 check identifiers. The length of each code block identifier is 8 bits, and the 3 code block identifiers can be the same or different. The length of each check identifier is 8 bits, and the 2 check identifiers can be the same or different. Figure 14The sum of the number of block identifiers and the number of check identifiers in the third padding code block shown is odd, which can facilitate the pad processing module in the FlexE shim at the receiving end to identify (or detect, find) the third padding code block. Specifically, during the process of the pad processing module in the FlexE shim at the receiving end identifying the third padding code block, if the pad processing module determines that the sum of the number of correct block identifiers and the number of correct check identifiers in the third padding code block exceeds half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block, the pad processing module considers that the identification of the third padding code block is successful, that is, the pad processing module finds the third padding code block. It can be seen that even if there are bit errors in some block identifiers and / or check identifiers in the third padding code block, the pad processing module can still find the third padding code block. Optionally, when the sum of the number of block identifiers and the number of check identifiers in the third padding code block is odd, and half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block is not an integer, the pad processing module in the FlexE shim at the receiving end can round up half of the sum of the number of block identifiers and the number of check identifiers in the third padding code block for identification and judgment. The embodiments of the present application do not make any limitations in this regard.

[0216] It should be noted that the bit positions in the third padding code block are described in the order from high to low above. It is also possible to describe the bit positions in the third padding code block in the order from low to high. No matter which order is used to describe the bit positions in the third padding code block, it does not affect the meanings of the respective fields in the third padding code block. In addition, Figures 11 to 14 Only the third padding code block of the embodiments of the present application is exemplarily shown. The third padding code block can also be other code blocks, and the positions of the respective fields in the third padding code block can be flexibly adjusted. The embodiments of the present application do not make any limitations in this regard. In some embodiments, the third padding code block is also referred to as the P3 code block. The embodiments of the present application do not limit the name of the third padding code block.

[0217] Combined with the above description, the present application embodiment introduces the padding sequence that periodically appears in the first data stream. As described above, the padding sequence includes n consecutive padding code blocks. In a possible case of the present application embodiment, the n padding code blocks include x first padding code blocks and y second padding code blocks, where x + y = n, and both x and y are positive integers. That is to say, the n padding code blocks only include the first padding code blocks and the second padding code blocks, and do not include the third padding code blocks. In other words, the padding sequence is composed of the first padding code blocks and the second padding code blocks. In another possible case of the present application embodiment, the n padding code blocks include x first padding code blocks, y second padding code blocks and z third padding code blocks, where x + y + z = n, and x, y, and z are all positive integers. That is to say, the n padding code blocks include the first padding code blocks, the second padding code blocks and the third padding code blocks. In other words, the padding sequence is composed of the first padding code blocks, the second padding code blocks and the third padding code blocks.

[0218] In an alternative embodiment, the first data stream satisfies any one of the following six implementation manners.

[0219] The first implementation manner: The first data stream includes a periodically appearing padding sequence, the padding sequence includes n consecutive padding code blocks, the n padding code blocks include x first padding code blocks and y second padding code blocks, x = 1, y = n - 1, the y second padding code blocks are located after the x first padding code blocks, the y second padding code blocks are consecutive, and the y second padding code blocks are consecutive with the x first padding code blocks. That is to say, the n padding code blocks include 1 first padding code block and n - 1 second padding code blocks, the n - 1 second padding code blocks are located after the 1 first padding code block, the n - 1 second padding code blocks are consecutive, and the n - 1 second padding code blocks are consecutive with the 1 first padding code block.

[0220] Exemplarily, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the first data stream is as Figure 15 shown. Refer to Figure 15 , in the first data stream, there is a padding sequence every w code blocks ( Figure 15 the w code blocks will be referred to as data code blocks in

[0221] The second implementation method: The first data stream includes a periodically occurring padding sequence, which includes n consecutive padding code blocks. The n padding code blocks include x first padding code blocks and y second padding code blocks. n is an even number, x = y = n / 2. The y second padding code blocks are located after the x first padding code blocks. The x first padding code blocks are consecutive, the y second padding code blocks are consecutive, and the y second padding code blocks are consecutive with the x first padding code blocks. That is, the n padding code blocks include n / 2 first padding code blocks and n / 2 second padding code blocks. The n / 2 second padding code blocks are located after the n / 2 first padding code blocks. The n / 2 first padding code blocks are consecutive, the n / 2 second padding code blocks are consecutive, and the n / 2 second padding code blocks are consecutive with the n / 2 first padding code blocks.

[0222] Exemplarily, the first padding code block is a P1 code block, and the second padding code block is a P2 code block. The first data stream is as Figure 16 shown. Refer to Figure 16 , in the first data stream, every w code blocks ( Figure 16 in

[0223] are referred to as data code blocks) have a padding sequence. Each padding sequence includes n / 2 P1 code blocks and n / 2 P2 code blocks. The n / 2 P2 code blocks are located after the n / 2 P1 code blocks. The n / 2 P1 code blocks are consecutive, the n / 2 P2 code blocks are consecutive, and the n / 2 P2 code blocks are consecutive with the n / 2 P1 code blocks.

[0224] Exemplarily, the first padding code block is a P1 code block, and the second padding code block is a P2 code block. The first data stream is as Figure 17 shown. Refer to Figure 17 , in the first data stream, every w code blocks ( Figure 17The w code blocks (referred to as data code blocks) each have a padding sequence. Each padding sequence includes n / 2 P1 code blocks and n / 2 P2 code blocks, and each padding sequence includes n / 2 code block groups. Each code block group includes 1 P1 code block and 1 P2 code block. The P2 code block is located after the P1 code block and is consecutive with the P1 code block. The padding code blocks in these n / 2 code block groups are consecutive. In other words, the n padding code blocks in the padding sequence are arranged in the order of P1 code block, P2 code block, P1 code block, P2 code block...

[0225] The fourth implementation: The first data stream includes a periodically occurring padding sequence. The padding sequence includes n consecutive padding code blocks. The n padding code blocks include x first padding code blocks and y second padding code blocks. The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks. The y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks. The x1 first padding code blocks, the y second padding code blocks, and the x2 first padding code blocks are consecutive, where x1 + x2 = x and x + y = n.

[0226] Exemplarily, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the first data stream is as Figure 18 shown. Refer to Figure 18 , every w code blocks in the first data stream ( Figure 18 the w code blocks are referred to as data code blocks) each have a padding sequence. Each padding sequence includes x P1 code blocks, y P2 code blocks, and x2 P1 code blocks. The y P2 code blocks are located between the x1 P1 code blocks and the x2 P1 code blocks. The x1 P1 code blocks, the y P2 code blocks, and the x2 P1 code blocks are consecutive.

[0227] The fifth implementation: The first data stream includes a periodically occurring padding sequence. The padding sequence includes n consecutive padding code blocks. The n padding code blocks include x first padding code blocks, y second padding code blocks, and z third padding code blocks, where x + y + z = n. The y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks. The x first padding code blocks, the y second padding code blocks, and the z third padding code blocks are consecutive. That is, the n padding code blocks are arranged in the order of x first padding code blocks, y second padding code blocks, and z third padding code blocks.

[0228] Exemplarily, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the third padding code block is a P3 code block. The first data stream is as Figure 19 shown. Refer to Figure 19 , every w code blocks in the first data stream ( Figure 19The w code blocks (hereinafter referred to as data code blocks) each have a padding sequence, and each padding sequence includes x P1 code blocks, y P2 code blocks, and z P3 code blocks. The y P2 code blocks are located after the x P1 code blocks and before the z P3 code blocks, and the x P1 code blocks, the y P2 code blocks, and the z P3 code blocks are consecutive. That is, the n padding code blocks in the padding sequence are arranged in the order of x P1 code blocks, y P2 code blocks, and z P3 code blocks.

[0229] The sixth implementation: The first data stream includes periodically occurring padding sequences. Each padding sequence includes n consecutive padding code blocks. The n padding code blocks include x first padding code blocks, y second padding code blocks, and z third padding code blocks, where x + y + z = n. The z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive. That is, the n padding code blocks are arranged in the order of x first padding code blocks, z third padding code blocks, and y second padding code blocks.

[0230] Exemplarily, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the third padding code block is a P3 code block. The first data stream is as Figure 20 shown. Refer to Figure 20 . Every w code blocks in the first data stream ( Figure 20 the w code blocks are hereinafter referred to as data code blocks) each have a padding sequence. Each padding sequence includes x P1 code blocks, y P2 code blocks, and z P3 code blocks. The z P3 code blocks are located after the x P1 code blocks and before the y P2 code blocks, and the x P1 code blocks, the z P3 code blocks, and the y P2 code blocks are consecutive. That is, the n padding code blocks in the padding sequence are arranged in the order of x P1 code blocks, z P3 code blocks, and y P2 code blocks. As an example, x = 1, y = 1, z = n - 2, and the first data stream is as Figure 21 shown.

[0231] It should be noted that, in the above first to fourth implementation manners, since the padding sequence only includes the first padding code block (i.e., the P1 code block) and the second padding code block (i.e., the P2 code block), the first to fourth implementation manners inherit the pad encapsulation format of the current FlexE standard to the greatest extent and are simple to implement. In the above fifth to sixth implementation manners, the padding sequence includes the first padding code block (i.e., the P1 code block), the second padding code block (i.e., the P2 code block), and the third padding code block (i.e., the P3 code block). On the one hand, the third padding code block can include a code block identifier, so the process of identifying (or detecting, searching for) the third padding code block by the pad processing module in the FlexE shim at the receiving end can be simplified. On the other hand, the fifth to sixth implementation manners can inherit the pad encapsulation format of the current FlexE standard to achieve a smooth evolution of the FlexE standard. Moreover, in the above sixth implementation manner, z third padding code blocks are arranged between x first padding code blocks and y second padding code blocks. Since both the first padding code block and the second padding code block are control code blocks and the third padding code block is a data code block, this arrangement makes the third padding code block not adjacent to the actual data code blocks in the first data stream, which can avoid confusion between the third padding code block and the actual data code blocks in the first data stream and prevent the third padding code block from contaminating the actual data code blocks in the first data stream.

[0232] It should be noted that Figures 15 to 21 Only as an example of the first data stream in the embodiments of the present application, it does not limit the first data stream. The structure of the padding sequence in the first data stream can also be other structures. The structure of the padding sequence and the number of padding code blocks in the padding sequence (i.e., the value of n) can be flexibly set and adjusted. The period in which the padding sequence appears in the first data stream can be flexibly set and adjusted. That is, Figures 15 to 21 the value of w involved in the description of Figures 15 to 21 can be flexibly adjusted. In addition, for

[0233] In Figure 10In the illustrated embodiment, after the pad processing module in the FlexE shim at the sending end obtains the first data stream, the pad processing module sends the first data stream to the interleaving module in the FlexE shim. After the interleaving module receives multiple data streams including the first data stream sent by multiple pad processing modules, the interleaving module interleaves the multiple data streams to obtain an interleaved data stream. The interleaving module sends the interleaved data stream to the physical layer at the sending end. After the physical layer at the sending end performs related physical layer processing on the data stream (such as inserting an AM code block into the data stream), the processed data stream is sent to the receiving end through the PHY interface at the sending end.

[0234] In summary, for the data processing method provided in the embodiments of the present application, the pad processing module in the FlexE shim at the sending end periodically inserts a padding sequence into the initial data stream sent by the FlexE instance to obtain the first data stream, and the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 4. It can be seen that the embodiments of the present application provide a method for inserting more padding code blocks into a data stream for FlexE, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0235] Please refer to Figure 22 , which shows a flowchart of another data processing method provided in the embodiments of the present application. This data processing method is applied to FlexE. This data processing method is executed by the pad processing module in the FlexE shim at the receiving end, specifically by the pad processing module in the FlexE shim. Optionally, the FlexE shim at the receiving end includes multiple pad processing modules, and this data processing method is executed by any one of the multiple pad processing modules. By way of example, Figure 22 The illustrated data processing method is executed by Figure 8 any one of the pad processing modules in the FlexE shim at the receiving end shown. Refer to Figure 22 , this data processing method includes the following steps S2201 to S2203.

[0236] S2201. Obtain a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, and the first data stream includes a periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 4.

[0237] Optionally, in the FlexE shim at the receiving end, the pad processing module receives the first data stream sent by the deinterleaving module. The first data stream is one of the multiple data streams obtained by the deinterleaving module through deinterleaving a data stream. For example, the first data stream is any one of the multiple data streams. It should be noted that Figure 22 the first data stream in the illustrated embodiment is Figure 10 the same data stream as the first data stream in the Figure 22 illustrated embodiment, but Figure 10 there may be bit errors in the first data stream in the illustrated embodiment compared to Figure 10 the first data stream in the illustrated embodiment. For the description of the first data stream, please refer to Figure 10 the illustrated embodiment and will not be elaborated here.

[0238] Optionally, in the FlexE shim at the receiving end, the deinterleaving module is connected to multiple pad processing modules. The deinterleaving module receives a data stream sent by the physical layer of the receiving end, deinterleaves the data stream to obtain multiple data streams, and sends the multiple data streams to the multiple pad processing modules one by one. The data stream received by one of the multiple pad processing modules from the deinterleaving module is the first data stream. Among them, the data stream sent by the physical layer of the receiving end to the deinterleaving module is the data stream after the physical layer performs relevant processing (such as deleting the AM code block) on the data stream received by the PHY interface of the receiving end.

[0239] S2202. Search for stuffed code blocks in the first data stream to find the stuffing sequence.

[0240] In the embodiments of the present application, the first data stream includes a periodically occurring stuffing sequence, and the stuffing sequence includes n consecutive stuffed code blocks. Optionally, the n stuffed code blocks include x first stuffed code blocks that are globally unique. At the receiving end, the pad processing module first searches for the first stuffed code blocks in the first data stream. After the pad processing module finds the first stuffed code blocks in the first data stream, the pad processing module locks the found first stuffed code blocks. The pad processing module searches for the stuffing sequence in the first data stream based on the first stuffed code blocks found in the first data stream.

[0241] In one embodiment, the pad processing module determines n-1 blocks after the first first padding code block found in the first data stream. The n-1 blocks are consecutive and the n-1 blocks are consecutive with the first first padding code block. The pad processing module searches for padding code blocks in the n-1 blocks by detecting the n-1 blocks. Wherein, the pad processing module detecting the n-1 blocks means that the pad processing module detects whether each of the n-1 blocks is a padding code block. In other words, the pad processing module detects the correctness of each of the n-1 blocks (i.e., detects whether each block is a correct padding code block). For a block among the n-1 blocks that includes a block identifier, the pad processing module detects whether the block is a padding code block based on the block identifier in the block. And, when the block further includes a check identifier, the pad processing module verifies the correctness of the block identifier in the block based on the check identifier in the block.

[0242] In an alternative embodiment, after the pad processing module finds the first first padding code block in the first data stream, the pad processing module obtains the first first padding code block and the n-1 blocks after the first first padding code block. The pad processing module maps (or sets) the first first padding code block and the n-1 blocks to a block bitmap. The pad processing module detects the n-1 blocks based on the block bitmap to search for padding code blocks in the n-1 blocks. Wherein, the block bitmap may be located in the pad processing module. By way of example, Figure 23 FIG. shows a schematic diagram of the block bitmap in the pad processing module. The block bitmap includes n block positions. The pad processing module maps each of the first first padding code block and the n-1 blocks to a block position, and the pad processing module maps different blocks to different block positions. In one example, the n block positions are arranged in sequence. The pad processing module maps the first first padding code block to the first block position among the n block positions (for example Figure 23 the block position identified as 1 in ), and the pad processing module maps the n-1 blocks one by one to the remaining n-1 block positions (i.e., the 2nd to nth block positions) in accordance with the arrangement order of the n-1 blocks.

[0243] In an alternative embodiment, the n padding code blocks include x first padding code blocks, y second padding code blocks, and z third padding code blocks, and the third padding code blocks include at least one code block identifier. After the pad processing module obtains the first first padding code block found in the first data stream and the n - 1 code blocks after the first first padding code block, for each of the n - 1 code blocks, the pad processing module detects whether the code block includes a code block identifier. In the case where the code block includes a code block identifier, the pad processing module maps the code block to the code block bitmap based on the code block identifier. After the pad processing module maps all the code blocks including code block identifiers among the n - 1 code blocks to the code block bitmap, the pad processing module randomly maps the first first padding code block and the code blocks among the n - 1 code blocks that do not include code block identifiers to the remaining positions in the code block bitmap.

[0244] In an alternative embodiment, the third padding code blocks further include at least one check identifier. That is, the third padding code blocks include at least one code block identifier and at least one check identifier. After the pad processing module obtains the first first padding code block found in the first data stream and the n - 1 code blocks after the first first padding code block, for the code blocks among the n - 1 code blocks that include code block identifiers, the pad processing module further detects whether the code block includes a check identifier. In the case where the code block includes a check identifier, the pad processing module verifies the correctness of the code block identifier in the code block based on the check identifier. After successful verification, the pad processing module maps the code block to the code block bitmap based on the code block identifier in the code block. Optionally, when the pad processing module successfully verifies the code block identifier in the code block, the pad processing module determines that the code block is a third padding code block, that is, the pad processing module identifies the third padding code block. In other words, the pad processing module finds the third padding code block. For each code block mapped to the code block bitmap and not including a code block identifier, the pad processing module detects whether the code block is a padding code block based on 66 bits of the code block. Optionally, when the pad processing module determines that the number of bits matching the padding code block among the 66 bits exceeds a target number, the pad processing module determines that the code block is a padding code block, that is, the pad processing module successfully detects the code block and the pad processing module finds the padding code block. In the case where the number of bits matching the padding code block among the 66 bits does not exceed the target number, the pad processing module determines that the code block is not a padding code block, that is, the pad processing module fails to detect the code block.

[0245] In one embodiment, the check identifier included in the third padding code block is a CRC code, and the CRC code is obtained by performing a CRC calculation on the code block identifier in the third padding code block. For example, the third padding code block is as Figure 11As shown. For each of the n - 1 code blocks after the first first padding code block found in the first data stream, including the code block identifier, the pad processing module detects whether the code block includes a CRC code. In the case where the code block includes a CRC code, the pad processing module verifies the correctness of the code block identifier in the code block based on the CRC code. Specifically, the pad processing module obtains the code block identifier and the CRC code in the code block, and the pad processing module performs a CRC calculation on the code block identifier in the code block to obtain a CRC calculation result. The pad processing module determines whether the CRC calculation result matches the CRC code (for example, is the same or the same number of bits reaches a certain number of bits). In the case where the CRC calculation result matches the CRC code, the pad processing module determines that the verification of the code block identifier is successful, and the pad processing module determines that the code block identifier is correct. In the case where the CRC calculation result does not match the CRC code, the pad processing module determines that the verification of the code block identifier fails, and the pad processing module determines that the code block identifier is incorrect.

[0246] In another embodiment, the check identifier included in the third padding code block is the bit - flipped code of the code block identifier included in the third padding code block. For example, the third padding code block is as Figure 13 As shown in FIG. 13 or 14. For each of the n - 1 code blocks after the first first padding code block found in the first data stream, including the code block identifier, the pad processing module detects whether the code block includes a check identifier. In the case where the code block includes a check identifier, the pad processing module verifies the correctness of the code block identifier in the code block based on the check identifier. Specifically, the pad processing module performs a bit flip on the code block identifier in the code block to obtain the bit - flipped code of the code block identifier. The pad processing module determines whether the bit - flipped code of the code block identifier matches the check identifier (for example, is the same or the same number of bits reaches a certain number of bits). In the case where the bit - flipped code of the code block identifier matches the check identifier, the pad processing module determines that the verification of the code block identifier is successful, and the pad processing module determines that the code block identifier is correct. In the case where the bit - flipped code of the code block identifier does not match the check identifier, the pad processing module determines that the verification of the code block identifier fails, and the pad processing module determines that the code block identifier is incorrect.

[0247] In an alternative embodiment, for each of the n - 1 code blocks that include a code block identifier and a check identifier, the pad processing module detects the correctness of the check identifier in the code block. When it is determined that the check identifier in the code block is correct, the pad processing module checks the correctness of the code block identifier in the code block based on the check identifier in the code block. In one embodiment, the code block includes a plurality of code block identifiers and a plurality of check identifiers, and the number of the plurality of code block identifiers is equal to or not equal to the number of the plurality of check identifiers. For example, the number of the plurality of code block identifiers and the number of the plurality of check identifiers are odd numbers. The pad processing module detects the correctness of the plurality of check identifiers, and the pad processing module checks the correctness of the plurality of code block identifiers based on the correct check identifiers among the plurality of check identifiers. In another embodiment, the code block includes a plurality of code block identifiers and a plurality of check identifiers, and the plurality of code block identifiers and the plurality of check identifiers are in one-to-one correspondence. The pad processing module detects the correctness of the plurality of check identifiers, and the pad processing module checks the correctness of the corresponding code block identifiers among the plurality of code block identifiers based on the correct check identifiers among the plurality of check identifiers.

[0248] In an alternative embodiment, for each of the n - 1 code blocks that include a plurality of code block identifiers and a plurality of check identifiers, the number of the plurality of code block identifiers is equal to or not equal to the number of the plurality of check identifiers. For example, the sum of the number of the plurality of code block identifiers and the number of the plurality of check identifiers is an odd number. The pad processing module detects the correctness of the plurality of code block identifiers and the plurality of check identifiers. The pad processing module determines the sum of the number of the correct code block identifiers among the plurality of code block identifiers and the number of the correct check identifiers among the plurality of check identifiers based on the detection result. When the sum of the number of the correct code block identifiers among the plurality of code block identifiers and the number of the correct check identifiers among the plurality of check identifiers exceeds half of the sum of the number of the plurality of code block identifiers and the number of the plurality of check identifiers, the pad processing module determines that the code block is a third padding code block. When the sum of the number of the correct code block identifiers among the plurality of code block identifiers and the number of the correct check identifiers among the plurality of check identifiers does not exceed half of the sum of the number of the plurality of code block identifiers and the number of the plurality of check identifiers, the pad processing module determines that the code block is not a third padding code block. Optionally, when the sum of the number of the plurality of code block identifiers and the number of the plurality of check identifiers is an odd number, half of the sum of the number of the plurality of code block identifiers and the number of the plurality of check identifiers is not an integer, and the pad processing module may round up half of the sum of the number of the plurality of code block identifiers and the number of the plurality of check identifiers for identification and determination. The embodiments of the present application do not make any limitations in this regard.

[0249] The above embodiments are described by taking the example that the pad processing module identifies (or searches for) the third padding code block according to the code block identifier and the check identifier. In the case that the third padding code block includes multiple code block identifiers, the pad processing module may identify (or search for) the third padding code block based on the multiple code block identifiers. In one embodiment, for each of the n-1 code blocks including multiple code block identifiers among the code blocks after the first padding code block found in the first data stream, the pad processing module detects the correctness of the multiple code block identifiers. The pad processing module determines the number of correct code block identifiers among the multiple code block identifiers. In the case that the number of correct code block identifiers among the multiple code block identifiers exceeds half of the number of the multiple code block identifiers, the pad processing module determines that the code block is the third padding code block. In the case that the number of correct code block identifiers among the multiple code block identifiers does not exceed half of the number of the multiple code block identifiers, the pad processing module determines that the code block is not the third padding code block. Optionally, when the number of the multiple code block identifiers is odd and half of the number of the multiple code block identifiers is not an integer, the pad processing module may round up half of the number of the multiple code block identifiers for identification and judgment, and the embodiments of the present application do not limit this.

[0250] Based on the above description, it can be seen that in the embodiments of the present application, the third padding code block is set to include multiple code block identifiers and / or multiple check identifiers. In the case that some of the multiple code block identifiers and / or the multiple check identifiers have error codes, the pad processing module in the FlexE shim at the receiving end can still identify the third padding code block. Thus, it can be avoided that the pad processing module in the FlexE shim at the receiving end cannot identify the third padding code block due to the error codes of the code block identifiers and / or check identifiers in the third padding code block, and the fault tolerance of the pad processing module for searching for the third padding code block is improved. In addition, the pad processing module in the FlexE shim at the receiving end only needs to identify the code block identifiers and / or check identifiers in the third padding code block to identify the third padding code block, and may not need to identify the complete content of the third padding code block. In other words, the pad processing module only needs to detect the correctness of the code block identifiers and / or check identifiers in the third padding code block to achieve the effect of identifying the third padding code block. Therefore, the process of the pad processing module searching for the third padding code block can be simplified. By setting the third padding code block to include code block identifiers in the embodiments of the present application, the dependency relationship between the padding code blocks is reduced. Even if some padding code blocks are incorrect, it does not affect the pad processing module searching for the padding sequence in the first data stream.

[0251] S2203. Determine that the padding sequence is found when multiple padding code blocks continuously found in the first data stream meet the preset conditions, where the preset conditions include: the number of the multiple padding code blocks is greater than a preset threshold and the number of the multiple padding code blocks is less than or equal to n.

[0252] During the process that the pad processing module in the FlexE shim at the receiving end searches for padding code blocks in the first data stream, the pad processing module determines whether the number of multiple consecutive padding code blocks found in the first data stream is greater than a preset threshold and less than or equal to n. When the pad processing module determines that the number of the multiple consecutive padding code blocks found is greater than the preset threshold and less than or equal to n, the pad processing module determines that the multiple padding code blocks meet the preset conditions, and further the pad processing module determines that a padding sequence is found. When the pad processing module determines that the number of the multiple padding code blocks is not greater than the preset threshold, the pad processing module determines that the multiple padding code blocks do not meet the preset conditions, and the pad processing module continues to search for padding code blocks in the first data stream until the multiple consecutive padding code blocks found meet the preset conditions. Optionally, the multiple padding code blocks continuously found by the pad processing module in the first data stream include the first padding code block continuously found by the pad processing module in the first data stream and the padding code blocks found in n-1 code blocks after the first first padding code block.

[0253] In an optional embodiment, the pad processing module performs at least one search process on the first data stream to search for a padding sequence in the first data stream. In each search process, the pad processing module searches for the first padding code block in the first data stream. After the pad processing module finds the first first padding code block in the first data stream, the pad processing module searches for padding code blocks in n-1 code blocks after the first first padding code block. And, the pad processing module determines whether the number of padding code blocks found in the n code blocks (including the first first padding code block and the n-1 code blocks) is greater than a preset threshold. When the pad processing module determines that the number of padding code blocks found in the n code blocks is greater than the preset threshold, the pad processing module determines that the multiple consecutive padding code blocks found meet the preset conditions, and further the pad processing module determines that a padding sequence is found, the pad processing module determines that the current search process is successful, and the pad processing module ends the search process. When the pad processing module determines that the number of padding code blocks found in the n code blocks is not greater than the preset threshold, the pad processing module determines that the multiple consecutive padding code blocks found do not meet the preset conditions, the pad processing module determines that the current search process fails, and the pad processing module performs the next search process. Optionally, in the first search process, the pad processing module starts searching for the first padding code block from the starting position of the first data stream. In each subsequent search process, the pad processing module starts searching for the first padding code block from the end position of the previous search process (specifically, the next code block of the n code blocks detected in the previous search process), and the embodiments of the present application do not limit this.

[0254] It should be noted that the above preset threshold can be flexibly set according to the situation, and the embodiments of the present application do not limit the specific value of the preset threshold. The embodiments of the present application take the preset condition for finding the filling sequence as an example that the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n. In some embodiments, the preset condition for finding the filling sequence includes: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. How to specifically set this preset condition can be related to the preset threshold. In one example, when n is 8 and the preset threshold is 6, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 8 and the preset threshold is 7, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 16 and the preset threshold is 13, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 16 and the preset threshold is 14, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In yet another example, when n is 32 and the preset threshold is 28, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 32 and the preset threshold is 29, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In still another example, when n is 64 and the preset threshold is 60, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 64 and the preset threshold is 61, the preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. It can be seen that whether the preset condition includes the situation where the number of multiple filling code blocks continuously found is equal to the preset threshold depends on the setting of the preset threshold, and the range covered by the preset condition can be flexibly set according to the preset threshold.

[0255] After the pad processing module in the FlexE shim at the receiving end finds the stuffing sequence in the first data stream, it can delete the stuffing sequence in the first data stream. Optionally, the pad processing module deletes the stuffing sequence in the first data stream according to the first stuffing sequence found in the first data stream and the period at which the stuffing sequence appears in the first data stream. In one embodiment, there is a stuffing sequence every w code blocks in the first data stream. The pad processing module first deletes the first stuffing sequence found in the first data stream, and then the pad processing module deletes n code blocks every w code blocks (the pad processing module considers these n code blocks to be n stuffing code blocks, that is, the stuffing sequence).

[0256] In Figure 22 In the embodiment shown, after the pad processing module in the FlexE shim at the receiving end deletes the stuffing sequence in the first data stream, the pad processing module sends the data stream after deleting the stuffing sequence (for example, the data stream after deleting the stuffing sequence is the initial data stream described in S1001) to the corresponding FlexE instance, so that the FlexE instance processes the initial data stream. The initial data stream can be restored to the FlexE client data stream after passing through the FlexE instance, the time slot allocation scheduler, and the idle addition and deletion module in sequence. The FlexE shim at the receiving end uploads the FlexE client data stream to the MAC layer for processing.

[0257] In summary, in the data processing method provided by the embodiment of the present application, since the first data stream includes a periodically appearing stuffing sequence, and the stuffing sequence includes consecutive n stuffing code blocks, where n is an integer greater than or equal to 4, the embodiment of the present application provides a method for FlexE that can insert more stuffing code blocks in the data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6T E PHY interfaces, and can adapt to the evolution of Ethernet standards. When the number of consecutive stuffing code blocks found by the pad processing module in the FlexE shim at the receiving end is greater than the preset threshold and less than or equal to n, it is determined that the stuffing sequence is found, without the number of consecutive stuffing code blocks found must be equal to n, that is, without all the stuffing code blocks in the stuffing sequence being detected correctly. Therefore, the embodiment of the present application provides a method for finding the stuffing sequence in a soft decision manner. The process of the pad processing module in the FlexE shim at the receiving end finding the stuffing sequence is relatively relaxed, the fault tolerance of finding the stuffing sequence is good, and the probability of successfully finding the stuffing sequence can be maintained without deterioration.

[0258] Please refer to Figure 24, which shows a flowchart of yet another data processing method provided by an embodiment of the present application. This data processing method is applied to FlexE. This data processing method is executed by the FlexE shim in the sending end, specifically by the pad processing module in the FlexE shim. Optionally, the FlexE shim in the sending end includes multiple pad processing modules, and this data processing method is executed by any one of the multiple pad processing modules. For example, Figure 24 The illustrated data processing method is performed by Figure 9 any one of the pad processing modules in the FlexE shim in the illustrated sending end. Refer to Figure 24 , this data processing method includes the following steps S2401 to S2402.

[0259] S2401. Receive an initial data stream, which is obtained by interleaving multiple data streams sent to multiple FlexE instances.

[0260] In the FlexE shim of the sending end, the interleaving module can send a data stream to the pad processing module, and the pad processing module receives the data stream sent by the interleaving module. For the convenience of distinction in this embodiment, the data stream sent by the interleaving module to the pad processing module is referred to as the initial data stream. Among them, the initial data stream is obtained by the interleaving module interleaving multiple data streams sent to the interleaving module by multiple FlexE instances.

[0261] S2402. Periodically insert a padding sequence into the initial data stream to obtain a first data stream. The first data stream includes the periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 16.

[0262] For the implementation process of S2402, please refer to the implementation process of S1002. For the description of the first data stream in this embodiment, please refer to Figure 10 the illustrated embodiment, and details are not described here. It should be noted that, different from Figure 10 the illustrated embodiment, in this embodiment, n is an integer greater than or equal to 16.

[0263] In this embodiment, after the pad processing module of the sending end obtains the first data stream, the pad processing module sends the first data stream to the physical layer of the sending end. After the physical layer performs related physical layer processing on the first data stream (such as inserting an AM code block into the first data stream), the processed data stream is sent to the receiving end through the PHY interface of the sending end.

[0264] In summary, in the data processing method provided by the embodiment of the present application, the pad processing module in the FlexE shim of the sending end periodically inserts a padding sequence into the initial data stream to obtain a first data stream. The padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 16. It can be seen that the embodiment of the present application provides a method for inserting more padding code blocks into the data stream for FlexE, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0265] Please refer to Figure 25 , which shows a flowchart of another data processing method provided by the embodiment of the present application. This data processing method is applied to FlexE. This data processing method is executed by the pad processing module in the FlexE shim of the receiving end. Optionally, the FlexE shim of the receiving end includes multiple pad processing modules, and this data processing method is executed by any one of the multiple pad processing modules. By way of example, Figure 25 The data processing method shown is executed by Figure 9 Any one of the pad processing modules in the FlexE shim of the receiving end shown. Refer to Figure 25 , this data processing method includes the following steps S2501 to S2503.

[0266] S2501. Obtain a first data stream. The first data stream is obtained by periodically inserting a padding sequence into the initial data stream. The initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances. The first data stream includes the periodically occurring padding sequence. The padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 16.

[0267] Optionally, in the FlexE shim of the receiving end, the pad processing module receives the first data stream sent by the physical layer. The first data stream is the data stream after the physical layer performs related physical layer processing (such as deleting AM code blocks) on the data stream received by the PHY interface of the receiving end. Moreover, the first data stream is the data stream obtained by the pad processing module in the FlexE shim of the sending end periodically inserting a padding sequence into the initial data stream. The initial data stream is obtained by the interleaving module in the FlexE shim of the sending end interleaving multiple data streams sent by multiple FlexE instances in the FlexE shim. It should be noted that Figure 25 The first data stream in the embodiment shown in Figure 24 is the same data stream as the first data stream in the embodiment shown in Figure 25 However, the first data stream in the embodiment shown inFigure 24 There may be error codes in the first data stream in the illustrated embodiment. Figure 25 For the description of the first data stream in the illustrated embodiment, please refer to Figure 10 the illustrated embodiment, which will not be elaborated here. Different from Figure 10 the illustrated embodiment, in Figure 25 the illustrated embodiment, n is an integer greater than or equal to 16.

[0268] S2502. Search for padding code blocks in the first data stream to find a padding sequence.

[0269] S2503. Determine that a padding sequence is found when multiple continuously found padding code blocks in the first data stream meet a preset condition, where the preset condition includes: the number of the multiple padding code blocks is greater than a preset threshold and the number of the multiple padding code blocks is less than or equal to n.

[0270] The implementation processes of S2502 to S2503 can refer to the implementation processes of S2202 to S2203, which will not be elaborated here.

[0271] It should be noted that the value of the preset threshold in S2503 is different from the value of the preset threshold in S2203, and the preset threshold in S2503 is generally greater than the preset threshold in S2203. Similarly to S2203, the preset threshold in S2503 can be flexibly set according to the situation, and the specific value of this preset threshold is not limited in the embodiments of the present application. In addition, the embodiments of the present application take the preset condition for finding the filling sequence as an example that the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n. In some embodiments, the preset condition for finding the filling sequence includes: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. How to specifically set this preset condition can be related to this preset threshold. In one example, when n is 16 and the preset threshold is 13, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 16 and the preset threshold is 14, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 32 and the preset threshold is 28, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 32 and the preset threshold is 29, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In yet another example, when n is 64 and the preset threshold is 60, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 64 and the preset threshold is 61, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In still another example, when n is 128 and the preset threshold is 120, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than the preset threshold and less than or equal to n; when n is 128 and the preset threshold is 121, this preset condition can be: the number of multiple filling code blocks continuously found in the first data stream is greater than or equal to the preset threshold and less than or equal to n. It can be seen that whether this preset condition includes the situation where the number of multiple filling code blocks continuously found is equal to the preset threshold depends on the setting of this preset threshold, and the range of this preset condition can be flexibly set according to this preset threshold.

[0272] In this embodiment, after the pad processing module in the FlexE shim at the receiving end finds the stuffing sequence in the first data stream, the pad processing module deletes the stuffing sequence in the first data stream. The pad processing module sends the data stream after deleting the stuffing sequence (for example, the data stream after deleting the stuffing sequence is the initial data stream described in S2201) to the corresponding deinterleaving module in the receiving end. The deinterleaving module deinterleaves the initial data stream to obtain multiple data streams. The deinterleaving module sends the multiple data streams to multiple FlexE instances in the receiving end one by one, so that the multiple FlexE instances process the multiple data streams. The initial data stream can be restored to the FlexE client data stream after passing through the deinterleaving module, FlexE instances, time slot allocation scheduler, and idle addition / removal module in sequence. The FlexE shim at the receiving end uploads the FlexE client data stream to the MAC layer for processing.

[0273] In summary, for the data processing method provided in the embodiment of the present application, since the first data stream includes a periodically occurring stuffing sequence, and the stuffing sequence includes consecutive n stuffing code blocks, where n is an integer greater than or equal to 16, the embodiment of the present application provides a method for FlexE that can insert more stuffing code blocks in the data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6T E PHY interfaces, and can adapt to the evolution of Ethernet standards. When the number of multiple consecutive stuffing code blocks found by the pad processing module in the FlexE shim at the receiving end is greater than a preset threshold and less than or equal to n, it is determined that the stuffing sequence is found, without the number of multiple consecutive stuffing code blocks found must be equal to n, that is, without all the stuffing code blocks in the stuffing sequence being detected correctly. Therefore, the embodiment of the present application provides a method for finding the stuffing sequence in a soft decision manner. The process of the pad processing module in the FlexE shim at the receiving end to find the stuffing sequence is relatively loose, the fault tolerance ability of finding the stuffing sequence is good, and the probability of successfully finding the stuffing sequence can be maintained without deterioration.

[0274] The above is the introduction of the method embodiment of the present application. Next, the device embodiment of the present application is introduced. The device of the present application can be used to execute the method of the present application. For details not disclosed in the device embodiment of the present application, please refer to the method embodiment.

[0275] Please refer to Figure 26 which shows a schematic diagram of a data processing device 600 provided in the embodiment of the present application. The data processing device 600 is applied to FlexE. For example, the data processing device 600 is the FlexE shim in the transmitting end, specifically, it can be the pad processing module in the FlexE shim. The data processing device 600 is used to execute asFigure 10 and Figure 24 the method provided by the embodiments shown. As Figure 26 shown, the data processing apparatus 600 includes a transceiver unit 610 and a processing unit 620. The transceiver unit 610 is configured to perform the transceiver operations in the method embodiments shown in Figure 10 and Figure 24 and the processing unit 620 is configured to perform operations other than the transceiver operations in the method embodiments shown in Figure 10 and Figure 24 In one implementation: The transceiver unit 610 is configured to receive an initial data stream sent by a FlexE instance; the processing unit 620 is configured to periodically insert a padding sequence into the initial data stream to obtain a first data stream, the first data stream includes the periodically occurring padding sequence, the padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 4.

[0276] In another implementation: The transceiver unit 610 is configured to receive an initial data stream, which is obtained by interleaving multiple data streams sent by multiple FlexE instances; the processing unit 620 is configured to periodically insert a padding sequence into the initial data stream to obtain a first data stream, the first data stream includes the periodically occurring padding sequence, the padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 16.

[0277] Optionally, in the above two implementations, the n padding code blocks include x first padding code blocks and y second padding code blocks. The first padding code block is a control code block that is globally unique in the first data stream, and the second padding code block is an error code block. x is a positive integer, and y is a positive integer.

[0278] Optionally, in the above two implementations, the x first padding code blocks and the y second padding code blocks satisfy any one of the following:

[0279] x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0280] x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0281] n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or,

[0282] When n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one of the first padding code blocks and one of the second padding code blocks. In each of the code block groups, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or,

[0283] The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks. The y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks. The x1 first padding code blocks, the y second padding code blocks, and the x2 first padding code blocks are consecutive, x1 + x2 = x, and both x1 and x2 are positive integers.

[0284] Optionally, in the above two implementation manners, the n padding code blocks further include z third padding code blocks, where z is a positive integer; the y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks, and the z third padding code blocks are consecutive; or, the z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive.

[0285] Optionally, in the above two implementation manners, the third padding code block is a data code block.

[0286] Optionally, in the above two implementation manners, the third padding code block includes at least one code block identifier.

[0287] Optionally, in the above two implementation manners, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

[0288] Optionally, in the above two implementation manners, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd.

[0289] In summary, for the technical solution provided in the embodiment of the present application, the padding sequence periodically inserted by the data processing device (i.e., FlexE shim in the sending end) in the initial data stream includes n consecutive padding code blocks, where n is an integer greater than or equal to 4, or n is an integer greater than or equal to 16. It can be seen that the embodiment of the present application can insert more padding code blocks into the data stream for FlexE, and can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0290] Please refer to Figure 27 , which shows a schematic diagram of another data processing device 700 provided by an embodiment of the present application. The data processing device 700 is applied to FlexE. For example, the data processing device 700 is a FlexE shim in the receiving end, and specifically may be a pad processing module in the FlexE shim. The data processing device 700 is used to execute the methods provided by the embodiments as shown in Figure 22 and Figure 25 . As shown in Figure 27 , the data processing device 700 includes a transceiver unit 710 and a processing unit 720. The transceiver unit 710 is used to execute the transceiver operations in the method embodiments as shown in Figure 22 and Figure 25 , and the processing unit 720 is used to execute operations other than the transceiver operations in the method embodiments as shown in Figure 22 and Figure 25 .

[0291] In one implementation: The transceiver unit 710 is used to obtain a first data stream. The first data stream is one of the multiplexed data streams obtained by deinterleaving, and the first data stream includes a periodically occurring padding sequence. The padding sequence includes n consecutive padding code blocks, and n is an integer greater than or equal to 4. The processing unit 720 is used to search for the padding code blocks in the first data stream to search for the padding sequence. And, it is used to determine that the padding sequence is found when a plurality of consecutively found padding code blocks in the first data stream meet a preset condition. The preset condition includes: the number of the plurality of padding code blocks is greater than a preset threshold and the number of the plurality of padding code blocks is less than or equal to n.

[0292] In another implementation: The transceiver unit 710 is used to obtain a first data stream. The first data stream is obtained by periodically inserting a padding sequence into an initial data stream. The initial data stream is obtained by interleaving the multiplexed data streams sent by multiple FlexE instances. The first data stream includes the periodically occurring padding sequence. The padding sequence includes n consecutive padding code blocks, and n is an integer greater than or equal to 16. The processing unit 720 is used to search for the padding code blocks in the first data stream to search for the padding sequence. And, it is used to determine that the padding sequence is found when a plurality of consecutively found padding code blocks in the first data stream meet a preset condition. The preset condition includes: the number of the plurality of padding code blocks is greater than a preset threshold and the number of the plurality of padding code blocks is less than or equal to n.

[0293] Optionally, in the above two implementations, the n padding code blocks include x first padding code blocks and y second padding code blocks. The first padding code block is a control code block that is globally unique in the first data stream, and the second padding code block is an error code block. x is a positive integer, and y is a positive integer.

[0294] Optionally, in the above two implementation manners, the x first padding code blocks and the y second padding code blocks satisfy any one of the following:

[0295] x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or,

[0296] n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or,

[0297] n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group includes a first padding code block and a second padding code block, in each code block group, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or,

[0298] The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks, the y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks, the x1 first padding code blocks, the y second padding code blocks and the x2 first padding code blocks are consecutive, x1 + x2 = x, and both x1 and x2 are positive integers.

[0299] Optionally, in the above two implementation manners, the n padding code blocks further include z third padding code blocks, where z is a positive integer; the y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks and the z third padding code blocks are consecutive; or, the z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks and the y second padding code blocks are consecutive.

[0300] Optionally, in the above two implementation manners, the third padding code block is a data code block.

[0301] Optionally, in the above two implementation manners, the third padding code block includes at least one code block identifier.

[0302] Optionally, in the above two implementation manners, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

[0303] Optionally, in the above two implementation manners, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0304] Optionally, in the above two implementation manners, the n padding code blocks include x first padding code blocks, where the first padding code blocks are control code blocks that are globally unique in the first data stream, x is a positive integer, and the processing unit 720 is configured to: find the first padding code blocks in the first data stream; and find the padding sequence in the first data stream based on the first padding code blocks found in the first data stream.

[0305] Optionally, in the above two implementation manners, the processing unit 720 is configured to: determine n - 1 code blocks after the first first padding code block found in the first data stream, where the n - 1 code blocks are consecutive, and the n - 1 code blocks are consecutive with the first first padding code block; and detect the n - 1 code blocks to find padding code blocks in the n - 1 code blocks.

[0306] Optionally, in the above two implementation manners, the processing unit 720 is configured to: map the first first padding code block and the n - 1 code blocks to a code block bitmap; and detect the n - 1 code blocks based on the code block bitmap to find padding code blocks in the n - 1 code blocks.

[0307] Optionally, in the above two implementation manners, the n padding code blocks include third padding code blocks, where the third padding code blocks include at least one code block identifier, and the processing unit 720 is configured to map the third padding code blocks to the code block bitmap based on the code block identifiers in the third padding code blocks.

[0308] Optionally, in the above two implementation manners, the third padding code blocks further include at least one check identifier, and the processing unit 720 is configured to: verify the correctness of the at least one code block identifier based on the at least one check identifier; and map the third padding code blocks to the code block bitmap based on the correct code block identifiers in the at least one code block identifier.

[0309] In summary, for the technical solution provided in the embodiment of the present application, since the first data stream includes a periodically occurring padding sequence, the padding sequence includes consecutive n padding code blocks, where n is an integer greater than or equal to 4, or n is an integer greater than or equal to 16. Therefore, the present application can insert more padding code blocks into the data stream for FlexE, and can be applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6T E PHY interfaces, and can adapt to the evolution of Ethernet standards. When the number of consecutive padding code blocks found by the data processing device (i.e., the FlexE shim at the receiving end) in the first data stream is greater than a preset threshold and less than or equal to n, the padding sequence is determined to be found, without the number of consecutive padding code blocks found necessarily being equal to n, that is, without all the padding code blocks in the padding sequence being detected correctly. Therefore, the process of finding the padding sequence is relatively relaxed, the fault tolerance of finding the padding sequence is good, and the probability of successfully finding the padding sequence can be maintained without deterioration.

[0310] The data processing device provided in the embodiment of the present application can also be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The above PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The data processing method provided in the above method embodiment can also be implemented by software. When the data processing method provided in the above method embodiment is implemented by software, each module in the data processing device can also be a software module.

[0311] The embodiment of the present application provides a data processing device, which is applied to FlexE. The data processing device can be the sending end or a functional component in the sending end, and the data processing device can also be the receiving end or a functional component in the receiving end. The data processing device includes a memory and a processor. The memory is used to store a computer program. The processor is used to execute the computer program stored in the memory so that the data processing device executes all or part of the steps of the data processing method provided in the above method embodiment.

[0312] In one embodiment, please refer to Figure 28, which shows a schematic diagram of another data processing device 800 provided by an embodiment of the present application. The data processing device 800 may be a sending end or a functional component in the sending end, and the data processing device 800 may also be a receiving end or a functional component in the receiving end. The data processing device 800 can implement Figure 10 , Figure 22 , Figure 24 or Figure 25 shown in the method embodiments. The data processing device 800 includes a main control board 810, an interface board 830, and an interface board 840. In the case of multiple interface boards, a switching network board ( Figure 28 not shown in the figure) is also included, and the switching network board is used to complete data exchange between interface boards (the interface board is also called a line card or a service board).

[0313] The main control board 810 is used to complete functions such as system management, device maintenance, and protocol processing. The interface board 830 and the interface board 840 are used to provide various service interfaces and implement service forwarding. These service interfaces are, for example, POS interfaces, GE PHY interfaces, TEPHY interfaces, asynchronous transfer mode (ATM) interfaces, etc. There are mainly three types of functional units on the main control board 810: a system management control unit, a system clock unit, and a system maintenance unit. The main control board 810, the interface board 830, and the interface board 840 are interconnected through a system bus and a system backplane. The interface board 830 includes one or more processors 831. The processor 831 is used to control and manage the interface board 830 and communicate with the central processor 812 on the main control board 810. The memory 832 on the interface board 830 is used to store forwarding table entries. The interface board 830 includes one or more network interfaces 833 for realizing transceiver. The main control board 810 also includes a memory 814, and the memory 814 is used to store system management information, protocols, etc., and the embodiments of the present application do not limit this.

[0314] As Figure 28 shown, in this embodiment, multiple interface boards are included, and a distributed forwarding mechanism is adopted. In this mechanism, the operations on the interface board 840 are basically similar to those of the interface board 830. For example, the interface board 840 includes one or more network interfaces 843 for realizing transceiver, the interface board 840 includes a memory 842 for storing forwarding table entries, and the interface board 840 includes a processor 841 for controlling and managing the interface board 840 and communicating with the central processor 812 on the main control board 810.

[0315] Figure 28The processor 831 in the interface board 830 and / or the processor 841 in the interface board 840 can be special-purpose hardware or chips, such as network processors or application-specific integrated circuits, to implement the above functions. This implementation method is usually referred to as the method of using special-purpose hardware or chips for processing on the forwarding plane. In another embodiment, the processor 831 in the interface board 830 and / or the processor 841 in the interface board 840 can also use a general-purpose processor, such as a general central processing unit (CPU).

[0316] There may be one or more main control boards. When there are multiple main control boards, it may include an active main control board and a standby main control board. There may be one or more interface boards. The stronger the data processing ability of the device (such as the sending end, receiving end, etc.), the more interface boards are provided. In the case of multiple interface boards, these multiple interface boards can communicate through one or more switching network boards. When there are multiple switching network boards, they can jointly achieve load sharing and redundant backup. In a centralized forwarding architecture, the device may not require a switching network board, and the interface board undertakes the processing function of the service data of the entire system. In a distributed forwarding architecture, the device includes multiple interface boards, and data exchange between multiple interface boards can be achieved through a switching network board, providing a large-capacity data exchange and processing ability. Therefore, the data access and processing ability of the device with a distributed architecture is greater than that of the device with a centralized architecture. Which architecture to specifically adopt depends on the networking deployment scenario and is not limited here.

[0317] In an alternative embodiment, the memory 832 and / or the memory 842 is a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disks or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 832 can exist independently and be connected to the processor 831 through a communication bus, or can also be integrated with the processor 831. The memory 842 can exist independently and be connected to the processor 841 through a communication bus, or can also be integrated with the processor 841.

[0318] The memory 832 is used to store program codes (i.e., computer programs) and is controlled by the processor 831 for execution to perform some or all of the steps of the data processing method provided in the above embodiments. The processor 831 is used to execute the program codes stored in the memory 832. The program codes may include one or more software units. These one or more software units may be the functional units provided in the above Figure 26 or Figure 27 functional units provided in the illustrated embodiments. The memory 842 may also be used to store program codes and is controlled by the processor 841 for execution to perform some or all of the steps of the data processing method provided in the above embodiments. Similarly, the memory 814 may also be used to store program codes and is controlled by the central processing unit 812 for execution to perform some or all of the steps of the data processing method provided in the above embodiments.

[0319] Optionally, the network interfaces 833 and 843 are devices such as transceivers for communicating with other devices or networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0320] In another embodiment, please refer to Figure 29 which shows a schematic diagram of another data processing device 900 provided in the embodiments of the present application. The data processing device 900 may be a sending end or a functional component in the sending end, and the data processing device 900 may also be a receiving end or a functional component in the receiving end. The data processing device 900 may implement Figure 10 , Figure 22 , Figure 24 or Figure 25 method embodiments.

[0321] As Figure 29 shown, the data processing device 900 includes a processor 902, a memory 904, a communication interface 906, and a bus 908. The processor 902, the memory 904, and the communication interface 906 are communicatively connected through the bus 908. Figure 29 The connection manner between the processor 902, the memory 904, and the communication interface 906 shown is merely exemplary. In the implementation process, the processor 902, the memory 904, and the communication interface 906 may also be connected by a connection manner other than the bus 908, and the embodiments of the present application do not limit this.

[0322] Among them, the memory 904 is used to store the computer program 9042, and the computer program 9042 may include instructions and data. The memory 904 may be various types of storage media, such as RAM, ROM, non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical memory, and registers, etc.

[0323] Among them, the processor 902 may be a general-purpose processor or a special-purpose processor. A general-purpose processor is a processor that executes specific steps and / or operations by reading and executing a computer program (such as the computer program 9042) stored in a memory (such as the memory 904), and the general-purpose processor may use the data stored in the memory (such as the memory 904) during the execution of the above steps and / or operations. The stored computer program can be executed to implement the related functions of the foregoing processing unit 620, and the general-purpose processor may be a CPU. A special-purpose processor is a processor specifically designed to execute specific steps and / or operations, and the special-purpose processor may be a digital signal processor (DSP), ASIC, or FPGA, etc. The processor 902 may also be a combination of multiple processors, such as a multi-core processor. The processor 902 includes at least one circuit to execute all or part of the steps of the foregoing method embodiments.

[0324] Among them, the communication interface 906 includes interfaces such as input / output (I / O) interfaces, physical interfaces, and logical interfaces for implementing the interconnection of devices inside the data processing device 900, and interfaces for implementing the interconnection of the data processing device 900 with other devices. The physical interface may be a GE PHY interface, a TE PHY interface, which is used to implement the interconnection of the data processing device 900 with other devices. The logical interface is an interface inside the data processing device 900, which is used to implement the interconnection of devices inside the data processing device 900. The communication interface 906 can be used for the data processing device 900 to communicate with other devices, and the communication interface 906 can implement the related functions of the foregoing transceiver units 610, 710. The communication interface 906 may also include a transceiver for transceiver, and the transceiver can also implement the related functions of the transceiver units 610, 710.

[0325] Among them, the bus 908 is any type of communication bus used to implement the interconnection of the processor 902, the memory 904, and the communication interface 906. The bus 908 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 908 can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 29 it is only represented by a thick line in Figure 29 , but it does not mean that there is only one bus or one type of bus.

[0326] The above-mentioned devices can be respectively arranged on independent chips, or at least partially or entirely arranged on the same chip. Whether to independently arrange each device on different chips or to integrate and arrange them on one or more chips often depends on the needs of product design. The embodiments of the present application do not limit the specific implementation forms of the above-mentioned devices.

[0327] Figure 29 The data processing device 900 shown is only exemplary. During the implementation process, the data processing device 900 may further include other components, which will not be listed one by one herein. Figure 29 The data processing device 900 shown inserts a padding sequence into the data stream or deletes the padding sequence in the data stream by executing all or part of the steps of the data processing method provided in the above-mentioned embodiments.

[0328] Based on the same inventive concept, the embodiments of the present application provide a communication system, which includes a sending end and a receiving end. The sending end includes the data processing device as shown in Figure 26 , Figure 28 or Figure 29 . The receiving end includes the data processing device as shown in Figure 27 , Figure 28 or Figure 29 . For example, the communication system is as shown in Figures 7 to 9 any one of them.

[0329] Based on the same inventive concept, the embodiments of the present application provide a computer-readable storage medium, in which a computer program is stored. When the computer program is executed (for example, executed by a data processing device, a FlexE shim, a pad processing module in the FlexE shim, one or more processors, etc.), all or part of the steps of the method provided in the above-mentioned method embodiments are realized.

[0330] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes a program or code. When the program or code is executed (for example, executed by a data processing device, a FlexE shim, a pad processing module in the FlexE shim, one or more processors, etc.), all or part of the steps of the method provided in the above method embodiment are implemented.

[0331] Based on the same inventive concept, an embodiment of the present application provides a chip, which includes a programmable logic circuit and / or program instructions. When the chip runs, it is used to implement all or part of the steps of the method provided in the above method embodiment.

[0332] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a readable storage medium of the computer, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a server, or a data center to another website, a computer, a server, or a data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access, or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium (such as a solid-state drive), etc.

[0333] It should be understood that the term "at least one" in the present application refers to one or more, and "a plurality" refers to two or more. In the present application, unless otherwise specified, the symbol " / " generally means "or". For example, A / B can represent A or B. The term "and / or" in the present application is only a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, for the convenience of clear description, the present application uses terms such as "first", "second", "third", etc. to distinguish the same items or similar items with basically the same functions and roles. Those skilled in the art can understand that the terms "first", "second", "third", etc. do not limit the quantity and execution order.

[0334] The method embodiments, device embodiments, and other different types of embodiments provided in the embodiments of the present application can all refer to each other. The sequence of operations in the method embodiments can be appropriately adjusted, and the operations can also be increased or decreased according to the situation. Any person skilled in the art in the technical field disclosed in the present application can easily think of a changed method within the scope of the technology disclosed in the present application, and it should be covered by the protection scope of the present application. Therefore, it will not be elaborated here.

[0335] In the corresponding embodiments provided in the present application, it should be understood that the disclosed devices and the like can be implemented in other constitutive manners. For example, the device embodiments described above are only illustrative. For example, the division of modules and / or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules, units, or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices, modules, or units can be in an electrical or other form. The modules and / or units described as separate components can be physically separated or not. The components described as modules and / or units can be physical modules and / or physical units or not, and they can be located in one place or distributed to multiple devices. Some or all of the modules and / or units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0336] As described above, it is only an exemplary embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art in the technical field disclosed in the present application can easily think of various equivalent modifications or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized in that, applied to Flexible Ethernet (FlexE), the method includes: receiving an initial data stream sent by a FlexE instance; periodically inserting a padding sequence into the initial data stream to obtain a first data stream, the first data stream including the periodically occurring padding sequence, the padding sequence including consecutive n padding code blocks, where n is an integer greater than or equal to 4.

2. A data processing method, characterized in that, applied to Flexible Ethernet (FlexE), the method includes: receiving an initial data stream, the initial data stream being obtained by interleaving multiple data streams sent by multiple FlexE instances; periodically inserting a padding sequence into the initial data stream to obtain a first data stream, the first data stream including the periodically occurring padding sequence, the padding sequence including consecutive n padding code blocks, where n is an integer greater than or equal to 16.

3. The method according to claim 1 or 2, characterized in that, the n padding code blocks include x first padding code blocks and y second padding code blocks, the first padding code blocks being control code blocks that are globally unique in the first data stream, the second padding code blocks being error code blocks, x being a positive integer, and y being a positive integer.

4. The method according to claim 3, characterized in that, the x first padding code blocks and the y second padding code blocks satisfy any one of the following: x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or, n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or, n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group including one first padding code block and one second padding code block, in each code block group, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or, the x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks, the y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks, the x1 first padding code blocks, the y second padding code blocks, and the x2 first padding code blocks are consecutive, x1 + x2 = x, and both x1 and x2 are positive integers.

5. The method according to claim 3, characterized in that, the n padding code blocks further include z third padding code blocks, z being a positive integer; the y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks, and the z third padding code blocks are consecutive; or, The z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks are consecutive.

6. The method according to claim 5, wherein, the third padding code block is a data code block.

7. The method according to claim 5 or 6, wherein, the third padding code block includes at least one code block identifier.

8. The method according to claim 7, wherein, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

9. The method according to claim 8, wherein, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is odd.

10. A data processing method, wherein, applied to Flexible Ethernet (FlexE), the method includes: obtaining a first data stream, where the first data stream is one of multiple data streams obtained by deinterleaving, the first data stream includes a periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 4; searching for padding code blocks in the first data stream to search for the padding sequence; determining that the padding sequence is found when multiple consecutively found padding code blocks in the first data stream meet a preset condition, where the preset condition includes: the number of the multiple padding code blocks is greater than a preset threshold and the number of the multiple padding code blocks is less than or equal to n.

11. A data processing method, wherein, applied to Flexible Ethernet (FlexE), the method includes: obtaining a first data stream, where the first data stream is obtained by periodically inserting a padding sequence into an initial data stream, the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances, the first data stream includes the periodically occurring padding sequence, and the padding sequence includes consecutive n padding code blocks, and n is an integer greater than or equal to 16; searching for padding code blocks in the first data stream to search for the padding sequence; determining that the padding sequence is found when multiple consecutively found padding code blocks in the first data stream meet a preset condition, where the preset condition includes: the number of the multiple padding code blocks is greater than a preset threshold and the number of the multiple padding code blocks is less than or equal to n.

12. The method according to claim 10 or 11, wherein, the n padding code blocks include x first padding code blocks and y second padding code blocks, the first padding code block is a control code block that is globally unique in the first data stream, the second padding code block is an error code block, x is a positive integer, and y is a positive integer.

13. The method according to claim 12, wherein, the x first padding code blocks and the y second padding code blocks satisfy any one of the following: x = 1, y = n - 1, the y second padding code blocks are located after the first padding code block, and the y second padding code blocks are consecutive with the first padding code block; or, n is an even number, x = y = n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are consecutive with the x first padding code blocks; or, n is an even number, x = y = n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one of the first padding code blocks and one of the second padding code blocks, in each of the code block groups, the second padding code block is located after the first padding code block and is consecutive with the first padding code block, and the padding code blocks in the n / 2 code block groups are consecutive; or, The x first padding code blocks include x1 first padding code blocks and x2 first padding code blocks, the y second padding code blocks are located between the x1 first padding code blocks and the x2 first padding code blocks, the x1 first padding code blocks, the y second padding code blocks and the x2 first padding code blocks are consecutive, x1 + x2 = x, and both x1 and x2 are positive integers.

14. The method according to claim 12, wherein, the n padding code blocks further include z third padding code blocks, and z is a positive integer; the y second padding code blocks are located after the x first padding code blocks and before the z third padding code blocks, and the x first padding code blocks, the y second padding code blocks and the z third padding code blocks are consecutive; or, the z third padding code blocks are located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks and the y second padding code blocks are consecutive.

15. The method according to claim 14, wherein, the third padding code block is a data code block.

16. The method according to claim 14 or 15, wherein, the third padding code block includes at least one code block identifier.

17. The method according to claim 16, wherein, the third padding code block further includes at least one check identifier, and the at least one check identifier is used to check the correctness of the at least one code block identifier.

18. The method according to claim 17, wherein, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

19. The method according to any one of claims 10 to 18, wherein, the n padding code blocks include x first padding code blocks, the first padding code block is a control code block that is globally unique in the first data stream, x is a positive integer, finding the padding code blocks in the first data stream to find the padding sequence includes: finding the first padding code block in the first data stream; Search for the padding sequence in the first data stream based on the first padding code block found in the first data stream.

20. The method according to claim 19, wherein, the searching for the padding sequence in the first data stream based on the first padding code block found in the first data stream includes: determine n - 1 code blocks after the first found first padding code block in the first data stream, the n - 1 code blocks are consecutive, and the n - 1 code blocks are consecutive with the first found first padding code block; detect the n - 1 code blocks to search for padding code blocks in the n - 1 code blocks, wherein the multiple continuously found padding code blocks in the first data stream include the first found first padding code block and the padding code blocks found in the n - 1 code blocks.

21. A data processing device, wherein, applied to Flexible Ethernet (FlexE), the device includes: a transceiver unit for performing the transceiver operations in the method according to any one of claims 1 to 9; a processing unit for performing operations other than the transceiver operations in the method according to any one of claims 1 to 9.

22. A data processing device, wherein, applied to Flexible Ethernet (FlexE), the device includes: a transceiver unit for performing the transceiver operations in the method according to any one of claims 10 to 20; a processing unit for performing operations other than the transceiver operations in the method according to any one of claims 10 to 20.

23. A data processing device, wherein, comprises a memory and a processor; the memory is used for storing a computer program; the processor is used for executing the computer program stored in the memory so that the data processing device executes the method according to any one of claims 1 to 20.

24. A communication system, wherein, comprises a sending end and a receiving end, the sending end includes the data processing device according to claim 21 or 23, and the receiving end includes the data processing device according to claim 22 or 23.

25. A computer-readable storage medium, wherein, a computer program is stored in the computer-readable storage medium, and when the computer program is executed, it implements the method according to any one of claims 1 to 20.

26. A computer program product, wherein, the computer program product includes a program or code, and when the program or code is executed, it implements the method according to any one of claims 1 to 20.

27. A chip, wherein, when the chip runs, it implements the method according to any one of claims 1 to 20.

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