Signal demodulation circuit, method and device suitable for TYPEB protocol of PICC card, and medium

Abstract

The embodiment of the invention relates to a signal demodulation circuit, method and device suitable for a PICC card TYPEB protocol and a medium, the circuit comprises an NRZ demodulation module and a protocol analysis module, the NRZ demodulation module is used for determining a rising edge and a falling edge of a received analog-to-digital conversion signal according to a preset rising and falling edge threshold value, and according to the rising edge and the falling edge of an SOF stage, the protocol analysis module is used for analyzing the received analog-to-digital conversion signal according to the rising edge and the falling edge of the SOF stage. Generating an SOF estimation signal according to an edge overturning principle and sending the SOF estimation signal to a protocol analysis module; the protocol analysis module searches whether an SOF signal meeting an SOF length threshold exists in the SOF estimation signals or not based on the preset SOF length threshold, and feeds back a frame header search completion mark to the NRZ demodulation module when the SOF signal is searched; and the NRZ demodulation module is also used for generating a data signal according to a rising edge and a falling edge of a data stage and an effective edge overturning principle after receiving the frame header search completion mark, and sending the data signal to the protocol analysis module. By adopting the technical scheme, the PICC card can correctly find the SOF signal from the noise of different phases.

Description

Technical Field

[0001] The present disclosure relates to the field of contactless communication technology, and in particular to a signal demodulation circuit, method, device and medium applicable to a PICC card TYPEB protocol. Background Art

[0002] With the development of the Internet of Things (IoT), more and more industries are attaching RFID (Radio Frequency Identification) tags to various items, such as access cards, ID cards, car keys, and bank cards, to form identification systems. This has led to increased demands for contactless communication, which requires both accurate communication and improved efficiency. Due to the unique nature of contactless communication, the communication process is susceptible to interference from the external environment, resulting in varying degrees of noise interference in the transmitted signal. Therefore, eliminating noise from the signal and improving communication resistance have become pressing challenges. Summary of the Invention

[0003] In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a signal demodulation circuit, method, device and medium applicable to the PICC card TYPEB protocol.

[0004] In a first aspect, an embodiment of the present disclosure provides a signal demodulation circuit applicable to the PICC card TYPEB protocol, including an NRZ demodulation module and a protocol analysis module;

[0005] The NRZ demodulation module is used to determine the rising edge and falling edge of the received analog-to-digital conversion signal according to the preset rising and falling edge thresholds, and generate an SOF estimation signal according to the rising and falling edges of the SOF phase according to the edge flip principle and send it to the protocol analysis module;

[0006] The protocol analysis module is configured to, after receiving the SOF estimation signal, search the SOF estimation signal based on a preset SOF length threshold to determine whether there is a SOF signal that meets the SOF length threshold, and when the SOF signal is found, feed back a frame header search completion flag to the NRZ demodulation module;

[0007] The NRZ demodulation module is further configured to generate a data signal according to the rising and falling edges of the data phase and the principle of flipping when encountering a valid edge after receiving the frame header search completion flag, and send the data signal to the protocol analysis module.

[0008] In a second aspect, an embodiment of the present disclosure provides a signal demodulation method applicable to a PICC card TYPEB protocol, which is applied to an NRZ demodulation module of a signal demodulation circuit applicable to a PICC card TYPEB protocol as described in the first aspect, the method comprising:

[0009] Determine the rising edge and falling edge of the received analog-to-digital conversion signal according to a preset rising and falling edge threshold;

[0010] According to the rising edge and falling edge of the SOF phase, the SOF estimation signal is generated according to the edge flip principle;

[0011] The SOF estimation signal is sent to the protocol analysis module of the signal demodulation circuit applicable to the PICC card TYPEB protocol, and the protocol analysis module searches the SOF estimation signal for a SOF signal that meets the SOF length threshold based on a preset SOF length threshold, and feeds back a frame header search completion flag to the NRZ demodulation module when the SOF signal is found;

[0012] After receiving the frame header search completion flag, a data signal is generated according to the rising edge and falling edge of the data phase and the effective edge flip principle and sent to the protocol analysis module.

[0013] In a third aspect, an embodiment of the present disclosure provides a signal demodulation method applicable to the PICC card TYPEB protocol, which is applied to the protocol analysis module of the signal demodulation circuit applicable to the PICC card TYPEB protocol as described in the first aspect, the method comprising:

[0014] Receiving the SOF estimation signal sent by the NRZ demodulation module of the signal demodulation circuit applicable to the PICC card TYPEB protocol, the SOF estimation signal is generated by the NRZ demodulation module according to the preset rising and falling edge thresholds, determining the rising and falling edges of the received analog-to-digital conversion signal, and generating the SOF estimation signal according to the edge flip principle based on the rising and falling edges of the SOF phase;

[0015] Searching, based on a preset SOF length threshold, whether there is a SOF signal meeting the SOF length threshold in the SOF estimation signal;

[0016] In response to searching for the SOF signal, a frame header search completion flag is fed back to the NRZ demodulation module, so that after receiving the frame header search completion flag, the NRZ demodulation module generates a data signal according to the rising edge and falling edge of the data phase and the principle of flipping on the valid edge, and sends it to the protocol analysis module.

[0017] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; the processor for reading the executable instructions from the memory and executing the executable instructions to implement the signal demodulation method applicable to the PICC card TYPEB protocol as described in the second aspect or the third aspect.

[0018] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to implement the signal demodulation method applicable to the PICC card TYPEB protocol as described in the second aspect or the third aspect.

[0019] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0020] The present invention provides a signal demodulation scheme for the PICC card TYPEB protocol. The NRZ demodulation module determines the rising and falling edges of the received analog-to-digital conversion signal based on a preset rising and falling edge threshold, and generates an SOF estimation signal based on the rising and falling edges of the SOF phase according to the edge flip principle and sends it to the protocol analysis module. After receiving the SOF estimation signal, the protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold to see whether there is an SOF signal that meets the SOF length threshold. When the SOF signal is found, it feeds back a frame header search completion flag to the NRZ demodulation module. After receiving the frame header search completion flag, the NRZ demodulation module generates a data signal based on the rising and falling edges of the data phase according to the effective edge flip principle and sends it to the protocol analysis module. The scheme of the present invention is adopted. By adjusting the SOF flip point strategy in the NRZ demodulation module and combining it with the SOF search strategy of the protocol analysis module, the PICC card can correctly find the SOF signal from noise of different phases, effectively eliminating the influence of noise at different positions, thereby effectively identifying the SOF signal, and then correctly receiving subsequent communication data, thereby improving communication efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0022] FIG1( a ) shows a schematic diagram of the existing PICC TYPEB NRZ decoding logic;

[0023] FIG1( b ) shows a schematic diagram of decoding a PICC TYPEB NRZ signal interfered with by a single noise using existing decoding logic;

[0024] FIG1(c) shows a schematic diagram of decoding a PICC TYPEB NRZ signal interfered with by multiple noises using existing decoding logic;

[0025] Figure 2 A schematic diagram showing a comparison between an existing demodulation strategy and an improved demodulation strategy provided by the present disclosure is shown;

[0026] Figure 3 A schematic structural diagram of a signal demodulation circuit applicable to PICC card TYPEB protocol according to an exemplary embodiment of the present disclosure is shown;

[0027] Figure 4 A schematic diagram of a receiving state machine of a protocol analysis module according to an exemplary embodiment of the present disclosure is shown;

[0028] Figure 5 A schematic diagram showing the effect of using the signal demodulation circuit of the present disclosure to analyze a single noise waveform according to an exemplary embodiment of the present disclosure is shown;

[0029] Figure 6 A schematic diagram showing the effect of using the signal demodulation circuit of the present disclosure to deal with multi-noise analysis waveforms according to an exemplary embodiment of the present disclosure is shown;

[0030] Figure 7 A flow chart of a signal demodulation method applicable to the PICC card TYPEB protocol provided by an exemplary embodiment of the present disclosure;

[0031] Figure 8 The present invention provides a flowchart of a signal demodulation method applicable to the PICC card TYPEB protocol provided by another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0033] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0034] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0035] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0036] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0037] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0038] Before explaining the specific embodiments of the present disclosure, the Chinese names or English abbreviations that may be involved in the present disclosure are explained as follows:

[0039] PICC: Proximity Card, NFC inductive IC card;

[0040] TYPEB: a standard protocol for contactless IC cards, a protocol type specified by the ISO / IEC14443 protocol that supports near-field identification, the ISO14443 TYPEB protocol;

[0041] SOF: Frame synchronization header information specified in the ISO / IEC14443 TYPEB protocol, indicating the start of a frame. The SOF signal has the shape of the low bit of 10ETU (10 or 11ETU) and the high bit of 2ETU (2 or 3ETU). Subsequent frame information can only be obtained normally if the SOF shape is correct.

[0042] ETU: Elementary Time Unit, basic time unit. One ETU is equivalent to the time required to transmit one data bit.

[0043] EOF: Indicates the end of the frame. For details, please refer to the definitions in ISO / IEC14443-1, 2, and 3.

[0044] IDLE: idle state;

[0045] DATA: The data part in the frame format, carrying valid communication content information;

[0046] NRZ: Non-Return Zero Code, high level is 1, low level is 0; PICC TYPEB protocol uses NRZ encoding;

[0047] RAM: Random Access Memory, which is the internal memory that directly exchanges data with the CPU;

[0048] Valid edge: The current edge change must be in the opposite direction of the previous edge change to be considered a valid edge. To determine whether a rising edge is valid, it is necessary to determine whether the current edge is a rising edge and the previous edge change is a falling edge. To determine whether a falling edge is valid, it is necessary to determine whether the current edge is a falling edge and the previous edge change is a rising edge. It contains polarity protection features;

[0049] ADC: refers to the analog-to-digital conversion signal obtained by quantizing the received field information by the analog receiver circuit;

[0050] fall_eg: valid falling edge flag in ADC data;

[0051] rise_eg: valid rising edge flag in ADC data;

[0052] rxd: The signal generated by the NRZ demodulation module according to the demodulation strategy in accordance with the ISO / IEC14443 TYPEB protocol requirements;

[0053] SOFL: represents the low level part of the SOF signal;

[0054] SOFH: Indicates the high level part of the SOF signal.

[0055] Currently, in related technologies, PICC TYPEB NRZ decoding follows the polarity judgment principle, that is, the level is flipped only when a valid edge is encountered. Figure 1(a) shows a schematic diagram of the existing PICC TYPEB NRZ decoding logic. In Figure 1(a), adc represents the analog-to-digital conversion signal received by the NRZ demodulation module, fall_eg represents the valid falling edge flag in the ADC data, rise_eg represents the valid rising edge flag in the ADC data, and rxd represents the signal with data information generated by the NRZ demodulation module after parsing the ADC data according to the polarity judgment principle. Each state in format is a frame parsing state that meets the requirements of the TYPEB protocol. The generation logic of the rxd signal shown in Figure 1(a) is as follows: (1) The default idle state of the rxd signal is a high level; (2) If the valid fall_eg signal is high (with polarity judgment), the rxd signal is pulled low; (3) If the valid rise_eg signal is high (with polarity judgment), the rxd signal is pulled high.

[0056] In a noise-free environment, existing NRZ decoding based on polarity determination can accurately identify SOF signals and data signals. However, due to the complex environment of contactless communication, the communication process is easily affected by external interference, which can be fed back into the ADC data and form noise. Figure 1(b) shows a schematic diagram of decoding a PICC TYPE B NRZ signal with single noise interference using existing decoding logic. Figure 1(c) shows a schematic diagram of decoding a PICC TYPE B NRZ signal with multiple noise interference using existing decoding logic. The "analyze state" represents the state analysis result of the protocol analysis module parsing the RXD signal. As shown in Figure 1(b), before the card reader sends the SOF, there is downward noise that interferes with the card reception. The effect of existing decoding based on polarity determination is shown in the RXD signal in Figure 1(b). It can be seen that the RXD signal has a SOFL pattern of more than 11 ETUs, causing the protocol analysis module to identify the SOFL length as abnormal, thus failing to correctly identify the SOF signal and effectively receiving the frame information. The module can only wait for the card reader to retransmit and then receive, which greatly reduces communication efficiency. As shown in Figure 1(c), there are multiple noises with different phases before the card machine sends SOF (two noise segments are used as an example in the figure). The effect of existing decoding based on the polarity judgment principle is shown in the rxd signal in Figure 1(c). The rxd signal has a very short SOFL code pattern, which causes the protocol analysis module to identify the SOFL length abnormality, and thus cannot identify the correct SOF signal. It is impossible to effectively receive the frame information and can only wait for the card machine to resend and then receive, which greatly affects the communication efficiency.

[0057] As can be seen, the existing NRZ decoding strategy relies on valid edge change judgments. For example, judging a rising edge as valid requires that the current ADC data is a rising edge and the previous one was a falling edge. Only then can the current rising edge be considered a valid rising edge. This includes polarity protection. The negative impact of polarity protection is that if there is noise in the SOF phase, the frame header cannot be found and the frame information is missed, thus affecting communication, preventing correct data reception and reducing communication efficiency. However, as can be seen from the dotted boxes of the RXD signal in Figures 1(b) and 1(c), the RXD signal actually contains the correct SOF signal code pattern. It is just that the protocol analysis module, affected by the previous noise, causes an error, resulting in the inability to recognize valid information.

[0058] In view of the above problems, the present disclosure provides an improved signal demodulation circuit suitable for PICC card TYPEB protocol, such as Figure 2 As shown, this solution improves the existing strategy of decoding based on the polarity judgment principle. In the NRZ demodulation module, the decoding work is divided into two parts. The two parts use different flipping principles to deal with different phase noises, while ensuring that SOF and valid data are not lost. One part is to search for SOF signals. In the SOF stage, the edge flip principle is used for decoding, that is, the judgment of the edge polarity is ignored, and the level is flipped when there is an edge, and the protocol analysis module is used to identify the SOF signal; the other part is to receive data. In the data decoding stage, the effective edge flip principle (also known as the polarity judgment principle) is followed, thereby effectively filtering out the noise of the same edge and ensuring the noise resistance of the data part. Using the solution disclosed in this disclosure, the SOF signal can still be accurately identified when there is different phase noise, and then the frame format can be correctly parsed to obtain the communication content. It can not only ensure the identification of valid SOF under noise interference, but also effectively filter out the in-phase edge noise in the data stage, reduce the bit error rate, and improve the noise resistance performance of the PICC TYPEB protocol. The disclosed solution is applicable to NRZ data with a baud rate of 106k / 212k / 424k / 848k / 1.7M as specified in the ISO / IEC14443 TYPEB protocol.

[0059] The signal demodulation circuit, method, device and medium applicable to the PICC card TYPEB protocol provided by the present disclosure are explained in detail below with reference to the accompanying drawings.

[0060] Figure 3 FIG. 1 shows a schematic structural diagram of a signal demodulation circuit applicable to a PICC card TYPEB protocol according to an exemplary embodiment of the present disclosure. Figure 3 As shown, the signal demodulation circuit applicable to the PICC card TYPEB protocol includes an NRZ demodulation module 110 and a protocol analysis module 120 , and may further include an analog receiver circuit 130 and a RAM 140 .

[0061] The analog receiver circuit 130 is configured to quantize the received field information into an analog-to-digital conversion signal and transmit the analog-to-digital conversion signal to the NRZ demodulation module 110. The NRZ demodulation module 110 is configured to determine the rising and falling edges of the received analog-to-digital conversion signal based on preset rising and falling edge thresholds. Based on the rising and falling edges of the SOF phase, the NRZ demodulation module 110 generates an SOF estimation signal according to the edge flipping principle and transmits the signal to the protocol analysis module 120. Upon receiving the SOF estimation signal, the protocol analysis module 120 searches the SOF estimation signal based on a preset SOF length threshold for an SOF signal that meets the SOF length threshold. Upon finding an SOF signal, the protocol analysis module 120 transmits a frame header search completion flag to the NRZ demodulation module 110. Once the protocol analysis module 120 finds the correct frame header signal (SOF signal), it can parse the corresponding frame information. Furthermore, upon receiving the frame header search completion flag, the NRZ demodulation module 110 generates a data signal based on the rising and falling edges of the data phase according to the valid edge flipping principle and transmits the signal to the protocol analysis module 120. After the protocol analysis module 120 completes the analysis of the received data signal, it stores the data in the corresponding RAM 140 .

[0062] The edge flip principle does not require edge polarity determination; it flips when there is a rising or falling edge. For example, if the first edge is a falling edge, when the second edge is encountered, regardless of whether it is a rising edge or a falling edge, it flips to a rising edge when generating the SOF estimation signal. The valid edge flip principle requires edge polarity determination. The current edge change must be in the opposite direction of the previous edge change to be considered a valid edge. Flipping is performed only when generating the data signal.

[0063] In addition, the protocol analysis module 120 also generates an interrupt signal so that the software can read the valid information and perform corresponding operations to complete the information interaction with the TYPEB of the card machine, and then complete related applications such as identity authentication.

[0064] The protocol analysis module 120 analyzes the protocol frame according to the level of the signal output by the NRZ demodulation module 110. Figure 4 The following is a schematic diagram of a receiving state machine of a protocol analysis module according to an exemplary embodiment of the present disclosure, wherein the meaning of each state machine is as follows:

[0065] IDLE: Idle state. When it starts receiving signals, it enters the WAIT_SOF state.

[0066] WAIT_SOF: Currently in the receiving state, waiting for the SOF signal. When the falling edge of the SOF estimation signal is received, it enters the RX_SOFL state;

[0067] RX_SOFL: In the RX_SOFL state, the low-level length of the SOF estimated signal is calculated. If the low-level length of the SOF estimated signal meets the SOFL requirement (that is, it is consistent with the SOF low-level length threshold), it indicates that the correct SOFL has been received, and the state machine enters the RX_SOFH state; if the low-level length does not meet the SOFL requirement, it enters the WAIT_SOF state.

[0068] RX_SOFH: In the RX_SOFH state, the high-level length of the SOF estimation signal is calculated. If the high-level length of the SOF estimation signal meets the SOFH requirements (that is, it is consistent with the SOF high-level length threshold) when the SOF estimation signal is a rising edge, it indicates that the correct SOFH signal is received and the state machine enters the RX_DATA state; if the high-level length does not meet the SOFH requirements, it enters the WAIT_SOF state.

[0069] RX_DATA: In the RX_DATA state, data is received according to the frame format, and after the data is completed, it enters the RX_EOF state;

[0070] RX_EOF: In the RX_EOF state, the EOF signal is received according to the frame format to complete the reception.

[0071] based on Figure 4 The receiving state machine design shown in the figure, in an optional embodiment of the present disclosure, the SOF length threshold includes a SOF low-level length threshold and a SOF high-level length threshold, wherein the SOF low-level length threshold can be set to 10ETU, for example, and the SOF high-level length threshold can be set to 2ETU, for example. In this embodiment, the protocol analysis module 120 is also used to: enter a waiting state (denoted as WAIT_SOF) to wait for receiving the SOF estimation signal, and when the falling edge of the SOF estimation signal is received, enter a SOF low-level receiving state (denoted as RX_SOFL); in the SOF low-level receiving state, count the low-level length between the current falling edge and the adjacent rising edge in the SOF estimation signal, and when the low-level length is consistent with the SOF low-level length threshold, enter a SOF high-level receiving state (denoted as RX_SOFH); in the SOF high-level receiving state, count the SOF F estimates the high-level length between the adjacent rising edge and the next falling edge in the signal, and when the high-level length is consistent with the SOF high-level length threshold, determines that there is a SOF signal that meets the SOF length threshold in the SOF estimation signal, and enters the data receiving state (recorded as RX_DATA); in the data receiving state, receives the data signal sent by the NRZ demodulation module according to the frame format of the TYPEB protocol, and enters the end state (recorded as RX_EOF) after the data reception is completed; in the end state, receives the EOF signal sent by the NRZ demodulation module according to the frame format to complete the reception.

[0072] Furthermore, in an optional embodiment of the present disclosure, the protocol analysis module 120 is further configured to: if the low-level length is inconsistent with the SOF low-level length threshold, enter a waiting state and perform a level flip on the signal following the adjacent rising edge; in the waiting state, upon receiving the falling edge of the flipped signal, enter the SOF low-level receiving state to count the low-level length. The low-level length thus counted is again compared with the SOF low-level length threshold, and, based on the comparison result, enter either the SOF high-level receiving state or the waiting state. The above process is repeated until the correct SOF signal is found.

[0073] In an optional embodiment of the present disclosure, the protocol analysis module 120 is further configured to: enter a waiting state if the high-level length does not coincide with the SOF high-level length threshold, and after entering the waiting state, enter an SOF low-level receiving state upon receiving a falling edge. The above process is repeated until the correct SOF signal is found.

[0074] Figure 5 FIG. 1 shows a schematic diagram showing the effect of using the signal demodulation circuit of the present disclosure to deal with a single noise analysis waveform according to an exemplary embodiment of the present disclosure. Figure 5 As shown, the RXD signal output by the NRZ demodulation module using the existing polarity judgment principle for decoding contains a low level with a level length of 15ETU, which does not meet the requirement of the SOF low level length of 10ETU, and is therefore incorrect. However, using the signal demodulation circuit disclosed in the present invention, the SOF estimation signal output by the NRZ demodulation module according to the edge flip principle (regardless of polarity) is as follows Figure 5 Combined with the receiving state machine logic of the protocol analysis module provided by the present disclosure, the protocol analysis module corrects the level of the rxdSearch_sof signal according to the rxdSearch_sof signal and the internal state machine jump situation, and searches for the SOF shape that meets the SOF low level length threshold and SOF high level length threshold in real time, as shown in FIG. Figure 5 As shown in the rxd rectify signal in the figure, after the state machine jumps back from the SOFL state to the WAIT_SOF state, the logic circuit corrects the rxd Search_sof signal, changing the high level to a low level. The state machine then enters the SOFL state to perform a low-level length check. This process continues until a valid SOF signal is identified. The dashed box in the rxd rectify signal represents the correct SOF signal found after level correction. After identifying a valid SOF signal, data reception and processing proceed.

[0075] Figure 6FIG. 1 shows a schematic diagram showing the effect of using the signal demodulation circuit of the present disclosure to deal with multi-noise analysis waveforms according to an exemplary embodiment of the present disclosure. Figure 6 As shown, the RXD signal output by the NRZ demodulation module using the existing polarity judgment principle for decoding contains a low level with a level length less than 10ETU, which is incorrect. However, using the signal demodulation circuit disclosed in the present invention, the SOF estimation signal output by the NRZ demodulation module according to the edge flip principle (regardless of polarity) is as follows Figure 6 Combined with the receiving state machine logic of the protocol analysis module provided by the present disclosure, the protocol analysis module corrects the level of the rxd Search_sof signal according to the rxd Search_sof signal and the internal state machine jump situation, and searches for the SOF shape of the legal length in real time, such as Figure 6 As shown in the figure, after the state machine jumps back from the SOFL state to the WAIT_SOF state, the logic circuit corrects the rxd Search_sof signal, changing the high level to a low level. The state machine then enters the SOFL state to perform a low-level length check. However, the low-level length still does not meet the SOH low-level length threshold. The state machine jumps back from the SOFL state to the WAIT_SOF state again. After receiving a low level, the state machine enters the SOFL state to perform a low-level length check. Real-time detection is performed until an SOF signal of legal length is identified. The dashed box in the rxd rectify signal represents the correct SOF signal found after level correction. After identifying a valid SOF signal, data reception and processing proceed.

[0076] It can be seen that the protocol parsing module provided by the present disclosure will correct the received signal according to the state machine jump situation, and use the state machine and level flipping to allow the parsing circuit to search for legal SOF signals at all times, instead of simply looking for 10ETU low frequency + 2ETU high level. It can also search for 10ETU high level and 2ETU low level signals. After finding such a shape, the signal is flipped to make a level correction, and then enter the state of frame data parsing, so that the correct SOF signal can be identified from waveforms of different shapes, and then data reception processing can be performed. By improving the demodulation strategy of the NRZ demodulation module and combining it with the SOF search logic of the protocol analysis module, the present disclosure can effectively filter out noise interference in the SOF stage, identify valid SOF signals, enhance the robustness of signal reception, and improve communication efficiency.

[0077] The signal demodulation circuit for the PICC card TYPEB protocol provided by the embodiments of the present disclosure includes an NRZ demodulation module and a protocol analysis module. The NRZ demodulation module determines the rising and falling edges of a received analog-to-digital conversion signal based on preset rising and falling edge thresholds, and generates an SOF estimation signal based on the rising and falling edges of the SOF phase and in accordance with the edge flip principle, and sends the signal to the protocol analysis module. After receiving the SOF estimation signal, the protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold to determine whether an SOF signal meeting the SOF length threshold exists, and when the SOF signal is found, feeds back a frame header search completion flag to the NRZ demodulation module. After receiving the frame header search completion flag, the NRZ demodulation module generates a data signal based on the rising and falling edges of the data phase and in accordance with the valid edge flip principle, and sends the signal to the protocol analysis module. By adopting the solution disclosed in the present invention, by adjusting the SOF flip point strategy in the NRZ demodulation module and combining it with the SOF search strategy of the protocol analysis module, the PICC card can correctly find the SOF signal from the noise of different phases, effectively eliminate the influence of noise at different positions, thereby effectively identifying the SOF signal, and then correctly receiving subsequent communication data, thereby improving communication efficiency.

[0078] Figure 7 This is a flow chart of a signal demodulation method applicable to the PICC card TYPEB protocol provided by an exemplary embodiment of the present disclosure. The method can be applied to the NRZ demodulation module of the signal demodulation circuit applicable to the PICC card TYPEB protocol described in the aforementioned embodiment.

[0079] like Figure 7 As shown, the signal demodulation method applicable to the PICC card TYPEB protocol may include the following steps:

[0080] Step 201: Determine the rising edge and falling edge of the received analog-to-digital conversion signal according to preset rising and falling edge thresholds.

[0081] The rising and falling edge thresholds can be preset. For example, a voltage lower than 0.3 volts can be set as a falling edge, and a voltage higher than 1.2 volts can be set as a rising edge.

[0082] In this embodiment, after receiving the analog-to-digital conversion signal, the NRZ demodulation module can identify the rising edge and the falling edge in the analog-to-digital conversion signal according to the rising and falling edge thresholds.

[0083] Step 202 : Generate a SOF estimation signal according to the rising edge and falling edge of the SOF phase and the edge flip principle.

[0084] Among them, the edge flip principle means that there is no need to judge the polarity of the edge, and it flips when there is a rising edge or a falling edge. For example, if the first edge is a falling edge, when encountering the second edge, no matter whether the second edge is a rising edge or a falling edge, it will flip to a rising edge when generating the SOF estimation signal.

[0085] Step 203: The SOF estimation signal is sent to a protocol analysis module of a signal demodulation circuit applicable to the PICC card TYPEB protocol. The protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold to see whether there is an SOF signal that meets the SOF length threshold. When an SOF signal is found, a frame header search completion flag is fed back to the NRZ demodulation module.

[0086] In this embodiment, the NRZ demodulation module sends the generated SOF estimation signal to the protocol analysis module. After receiving the SOF estimation signal, the protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold to see if there is a SOF signal that meets the SOF length threshold. Specifically, after receiving begins, the module first enters a waiting state to wait for the SOF estimation signal. When a falling edge of the SOF estimation signal is received, the module enters a SOF low-level receiving state. In the SOF low-level receiving state, the module counts the low-level length between the current falling edge and the adjacent rising edge of the SOF estimation signal and compares the low-level length with the SOF low-level length threshold to see if it is consistent. If the low-level length is inconsistent with the SOF low-level length threshold, the module re-enters the waiting state and flips the signal level after the adjacent rising edge. In the waiting state, when a falling edge of the flipped signal is received, the module enters a SOF low-level receiving state to count the low-level length. If the low-level length is consistent with the SOF low-level length threshold, the module enters a SOF high-level receiving state. In the SOF high-level receiving state, the high-level length between the adjacent rising edge and the next falling edge (i.e., the next edge adjacent to the adjacent rising edge) in the SOF estimation signal is counted, and the high-level length is compared with the SOF high-level length threshold to see if it is consistent. If the high-level length does not match the SOF high-level length threshold, the system re-enters the waiting state and enters the SOF low-level receiving state when a falling edge is received. If the high-level length matches the SOF high-level length threshold, it is determined that the SOF estimation signal contains a SOF signal that meets the SOF length threshold, and then a frame header search completion flag is fed back to the NRZ demodulation module.

[0087] Step 204: After receiving the frame header search completion flag, generate a data signal according to the rising edge and falling edge of the data phase and the principle of flipping upon encountering a valid edge, and send the data signal to the protocol analysis module.

[0088] In this embodiment, after receiving the frame header search completion flag fed back by the protocol analysis module, the NRZ demodulation module generates a data signal according to the rising and falling edges of the data phase and the principle of flipping upon encountering a valid edge, and sends it to the protocol analysis module.

[0089] Among them, the principle of flipping when encountering a valid edge requires judging the polarity of the edge. The current edge change must be opposite to the direction of the previous edge change to be considered a valid edge, and flipping is only performed when generating a data signal.

[0090] The present invention provides a signal demodulation method for the PICC card TYPEB protocol. The NRZ demodulation module determines the rising and falling edges of the received analog-to-digital conversion signal based on a preset rising and falling edge threshold. Based on the rising and falling edges of the SOF phase, an SOF estimation signal is generated according to the edge flip principle. The SOF estimation signal is sent to the protocol analysis module. The protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold to determine whether there is an SOF signal that meets the SOF length threshold. When an SOF signal is found, a frame header search completion flag is fed back to the NRZ demodulation module. After receiving the frame header search completion flag, a data signal is generated according to the rising and falling edges of the data phase according to the valid edge flip principle and sent to the protocol analysis module. The scheme of the present invention can effectively distinguish noise, correctly identify SOF and valid information under noise interference, and then parse the correct communication data, reduce the situation where the card machine retransmits due to bit errors caused by noise, and increase the communication interaction time, and effectively improve the efficiency of TYPEB communication.

[0091] Figure 8 This is a flow chart of a signal demodulation method applicable to the PICC card TYPEB protocol provided by another exemplary embodiment of the present disclosure. The method can be applied to the protocol analysis module of the signal demodulation circuit applicable to the PICC card TYPEB protocol described in the aforementioned embodiment.

[0092] like Figure 8 As shown, the signal demodulation method applicable to the PICC card TYPEB protocol may include the following steps:

[0093] Step 301: Receive an SOF estimation signal sent by an NRZ demodulation module of a signal demodulation circuit applicable to the PICC card TYPEB protocol. The SOF estimation signal is generated by the NRZ demodulation module based on the rising and falling edges of the received analog-to-digital conversion signal according to a preset rising and falling edge threshold, and according to the rising and falling edges of the SOF phase, according to the edge flip principle.

[0094] It should be noted that, in this embodiment, the detailed description of how the NRZ demodulation module generates the SOF estimation signal can be found in the relevant description of the aforementioned embodiment, which will not be repeated here.

[0095] Step 302: Search the SOF estimation signal based on a preset SOF length threshold to see whether there is an SOF signal that meets the SOF length threshold.

[0096] The SOF length threshold includes a SOF low level length threshold and a SOF high level length threshold.

[0097] When the protocol analysis module searches for a SOF signal that meets the SOF length threshold in the SOF estimation signal, it can first enter a waiting state to wait for receiving the SOF estimation signal. When the falling edge of the SOF estimation signal is received, it enters a SOF low-level receiving state. In the SOF low-level receiving state, the low-level length between the current falling edge and the adjacent rising edge in the SOF estimation signal is counted. When the low-level length is inconsistent with the SOF low-level length threshold, the waiting state is re-entered, and the signal after the adjacent rising edge is level-flipped. In the waiting state, when the falling edge of the flipped signal is received, the SOF low-level receiving state is entered to count the low-level length. When the low-level length is consistent with the SOF low-level length threshold, the SOF high-level receiving state is entered. In the SOF high-level receiving state, the high-level length between the adjacent rising edge to the next falling edge in the SOF estimation signal is counted, and when the high-level length is consistent with the SOF high-level length threshold, it is determined that there is a SOF signal that meets the SOF length threshold in the SOF estimation signal; when the high-level length is inconsistent with the SOF high-level length threshold, the waiting state is re-entered, and when a falling edge is received, the SOF low-level receiving state is entered to count the low-level length.

[0098] In step 303, in response to searching for the SOF signal, a frame header search completion flag is fed back to the NRZ demodulation module, so that after receiving the frame header search completion flag, the NRZ demodulation module generates a data signal according to the rising and falling edges of the data phase and the principle of flipping on a valid edge, and sends it to the protocol analysis module.

[0099] In this embodiment, when the protocol analysis module searches for a SOF signal that meets the SOF level length threshold from the SOF estimation signal, it feeds back a frame header search completion flag to the NRZ demodulation module. After receiving the frame header search completion flag, the NRZ demodulation module generates a data signal according to the principle of flipping when encountering a valid edge and sends it to the protocol analysis module.

[0100] Furthermore, after determining that a SOF signal that meets the SOF level length threshold is searched from the SOF estimation signal, the protocol analysis module enters a data receiving state, receives the data signal sent by the NRZ demodulation module according to the frame format of the TYPEB protocol in the data receiving state, and enters an end state after the data reception is completed; in the end state, the EOF signal sent by the NRZ demodulation module is received according to the frame format to complete the reception.

[0101] The present invention provides a signal demodulation method for the PICC card TYPEB protocol. The NRZ demodulation module determines the rising and falling edges of the received analog-to-digital conversion signal based on a preset rising and falling edge threshold. Based on the rising and falling edges of the SOF phase, an SOF estimation signal is generated according to the edge flip principle. The SOF estimation signal is sent to the protocol analysis module. The protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold to determine whether there is an SOF signal that meets the SOF length threshold. When an SOF signal is found, a frame header search completion flag is fed back to the NRZ demodulation module. After receiving the frame header search completion flag, a data signal is generated according to the rising and falling edges of the data phase according to the valid edge flip principle and sent to the protocol analysis module. The scheme of the present invention can effectively distinguish noise, correctly identify SOF and valid information under noise interference, and then parse the correct communication data, reduce the situation where the card machine retransmits due to bit errors caused by noise, and increase the communication interaction time, and effectively improve the efficiency of TYPEB communication.

[0102] The embodiments of the present disclosure further provide a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, the signal demodulation method applicable to the PICC card TYPEB protocol provided in any embodiment of the present disclosure is implemented.

[0103] According to one or more embodiments of the present disclosure, the present disclosure provides an electronic device, including:

[0104] processor;

[0105] a memory for storing instructions executable by the processor;

[0106] The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the signal demodulation method applicable to the PICC card TYPEB protocol as provided in any embodiment of the present disclosure.

[0107] According to one or more embodiments of the present disclosure, the present disclosure provides a computer-readable storage medium storing a computer program for implementing a signal demodulation method applicable to the PICC card TYPEB protocol as provided in any embodiment of the present disclosure.

[0108] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0109] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0111] The units involved in the embodiments described in this disclosure may be implemented in software or hardware, wherein the name of a unit does not necessarily limit the unit itself.

[0112] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0113] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0114] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also includes other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned disclosed concepts. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

[0115] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details have been included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0116] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A signal demodulation circuit suitable for PICC card TYPEB protocol, characterized in that: Including NRZ demodulation module and protocol analysis module; The NRZ demodulation module is used to determine the rising edge and falling edge of the received analog-to-digital conversion signal according to the preset rising and falling edge thresholds, and generate a SOF estimation signal according to the rising edge and falling edge of the SOF stage according to the edge flip principle and send it to the protocol analysis module; The protocol analysis module is used for searching whether there is a SOF signal that meets the SOF length threshold in the SOF estimation signal after receiving the SOF estimation signal, and feeding back a frame header search completion flag to the NRZ demodulation module when the SOF signal is found; The NRZ demodulation module is also used to generate a data signal and send it to the protocol analysis module according to the rising edge and falling edge of the data phase and the principle of flipping when encountering a valid edge after receiving the frame header search completion mark.

2. The signal demodulation circuit applicable to PICC card TYPEB protocol according to claim 1, characterized in that: The SOF length threshold includes a SOF low level length threshold and a SOF high level length threshold; The protocol analysis module is also used for: Entering a waiting state to wait for receiving a SOF estimation signal, and when receiving a falling edge of the SOF estimation signal, entering a SOF low level receiving state; In the SOF low-level receiving state, counting the low-level length between the current falling edge and the adjacent rising edge in the SOF estimation signal, and entering the SOF high-level receiving state when the low-level length is consistent with the SOF low-level length threshold; In the SOF high-level receiving state, counting the high-level lengths between the adjacent rising edges to the next falling edges in the SOF estimation signal, and when the high-level lengths are consistent with the SOF high-level length threshold, determining that there is a SOF signal that meets the SOF length threshold in the SOF estimation signal, and entering a data receiving state; In the data receiving state, the data signal sent by the NRZ demodulation module is received according to the frame format of the TYPEB protocol, and the end state is entered after the data reception is completed; In the end state, the EOF signal sent by the NRZ demodulation module is received according to the frame format to complete the reception.

3. The signal demodulation circuit applicable to PICC card TYPEB protocol according to claim 2, characterized in that: The protocol analysis module is also used for: When the low level length is inconsistent with the SOF low level length threshold, the waiting state is entered, and the level of the signal after the adjacent rising edge is flipped; In the waiting state, when the falling edge of the flipped signal is received, the SOF low level receiving state is entered to count the low level length.

4. The signal demodulation circuit applicable to PICC card TYPEB protocol according to claim 2 or 3, characterized in that: The protocol analysis module is also used for: When the high level length is not consistent with the SOF high level length threshold, the waiting state is entered, and when a falling edge is received, the SOF low level receiving state is entered.

5. A signal demodulation method applicable to PICC card TYPEB protocol, characterized in that: The NRZ demodulation module applied to the signal demodulation circuit applicable to the PICC card TYPEB protocol as claimed in any one of claims 1 to 4, the method comprising: Determine the rising edge and falling edge of the received analog-to-digital conversion signal according to a preset rising and falling edge threshold; According to the rising edge and falling edge of the SOF phase, a SOF estimation signal is generated according to the edge flip principle; The SOF estimation signal is sent to the protocol analysis module of the signal demodulation circuit applicable to the PICC card TYPEB protocol, and the protocol analysis module searches the SOF estimation signal based on a preset SOF length threshold whether there is a SOF signal that meets the SOF length threshold, and feeds back a frame header search completion flag to the NRZ demodulation module when the SOF signal is searched; After receiving the frame header search completion flag, a data signal is generated according to the rising edge and falling edge of the data phase and the effective edge flip principle, and sent to the protocol analysis module.

6. A signal demodulation method applicable to PICC card TYPEB protocol, characterized in that: The method is applied to the protocol analysis module of the signal demodulation circuit applicable to the PICC card TYPEB protocol as claimed in any one of claims 1 to 4, and comprises: Receive the SOF estimation signal sent by the NRZ demodulation module of the signal demodulation circuit applicable to the PICC card TYPEB protocol, the SOF estimation signal is generated by the NRZ demodulation module according to the preset rising and falling edge thresholds to determine the rising and falling edges of the received analog-to-digital conversion signal, and according to the rising and falling edges of the SOF stage, according to the edge flip principle; Based on a preset SOF length threshold, searching whether there is a SOF signal satisfying the SOF length threshold in the SOF estimation signal; In response to searching for the SOF signal, a frame header search completion flag is fed back to the NRZ demodulation module, so that after receiving the frame header search completion flag, the NRZ demodulation module generates a data signal according to the rising and falling edges of the data phase and the principle of flipping when encountering a valid edge, and sends it to the protocol analysis module.

7. The method according to claim 6, characterized in that The SOF length threshold includes a SOF low level length threshold and a SOF high level length threshold; The searching, based on a preset SOF length threshold, whether there is a SOF signal satisfying the SOF length threshold in the SOF estimation signal comprises: Entering a waiting state to wait for receiving a SOF estimation signal, and when receiving a falling edge of the SOF estimation signal, entering a SOF low level receiving state; In the SOF low-level receiving state, counting the low-level length between the current falling edge and the adjacent rising edge in the SOF estimation signal, and entering the SOF high-level receiving state when the low-level length is consistent with the SOF low-level length threshold; In the SOF high level receiving state, the high level length between the adjacent rising edge to the next falling edge in the SOF estimation signal is counted, and when the high level length is consistent with the SOF high level length threshold, it is determined that there is a SOF signal that meets the SOF length threshold in the SOF estimation signal.

8. The method according to claim 7, characterized in that The method further comprises: When the low level length is inconsistent with the SOF low level length threshold, the waiting state is entered, and the level of the signal after the adjacent rising edge is flipped; In the waiting state, when the falling edge of the flipped signal is received, the SOF low level receiving state is entered to count the low level length.

9. The method according to claim 7, characterized in that: The method further comprises: When the high level length is not consistent with the SOF high level length threshold, the waiting state is entered, and when a falling edge is received, the SOF low level receiving state is entered.

10. The method according to any one of claims 7 to 9, characterized in that: After determining that there is a SOF signal satisfying the SOF length threshold in the SOF estimation signal, the method further includes: Enter data receiving state; In the data receiving state, the data signal sent by the NRZ demodulation module is received according to the frame format of the TYPEB protocol, and the end state is entered after the data reception is completed; In the end state, the EOF signal sent by the NRZ demodulation module is received according to the frame format to complete the reception.

11. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the signal demodulation method applicable to the PICC card TYPEB protocol as described in any one of claims 5 to 10.

12. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program is used to implement the signal demodulation method applicable to the PICC card TYPEB protocol as described in any one of claims 5 to 10 above.

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