Protocol decoding and triggering method based on envelope detection, digital oscilloscope and medium

Abstract

The invention provides a protocol decoding and triggering method based on envelope detection, a digital oscilloscope and a medium, relates to the technical field of digital signal processing, and is used for solving the problems of speed, accuracy and cost in a protocol decoding and triggering process. The method is applied to the digital oscilloscope. The digital oscilloscope comprises a hardware circuit and upper computer software; the method comprises the following steps: a hardware circuit performs envelope detection on a collected original signal to obtain an effective data packet; the upper computer software performs level conversion on the effective data packet according to a preset level threshold value to obtain a binary data packet; the upper computer software searches protocol frame headers of the binarized data packets according to frame header characteristics of different protocols; and the upper computer software performs protocol decoding and protocol triggering on the binarized data packet by taking a protocol frame header as a starting point. According to the method, based on hardware pre-triggering of envelope detection, analysis on invalid data packets can be reduced, the protocol decoding and triggering efficiency and accuracy are improved, and extra hardware cost is not needed.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and provides a protocol decoding and triggering method based on envelope detection, a digital oscilloscope and a medium. Background Art

[0002] As the development of various industries is becoming more and more digital, intelligent, networked and energy-saving, especially the rapid development of the intelligent driving industry, the communication requirements between electronic devices are getting higher and higher, and a variety of bus protocols have emerged, including I2C, CAN, LIN, Flexray, USB, PCIe and other protocols. As the types and complexity of bus protocols increase, the bus analysis requirements for electronic measurement equipment such as oscilloscopes also increase. In addition, for high-speed serial protocols such as USB and PCIe, the real-time and consistency of decoding and triggering need to be considered.

[0003] There are two main processing methods for various measurement and analysis instruments. One is to implement protocol decoding and triggering through analog comparators and programmable hardware. This pure hardware processing method is fast, but due to the limitations of hardware circuits, it is difficult to flexibly adjust parameters and deal with complex protocol formats, resulting in low accuracy of protocol decoding and triggering. The other is to implement protocol decoding at the software layer and protocol triggering at the hardware layer, which not only requires additional hardware costs, but may also lead to inconsistent decoding and triggering results. Summary of the invention

[0004] The present application provides a protocol decoding and triggering method based on envelope detection, a digital oscilloscope and a medium, which are used to solve the speed, accuracy and cost problems in the protocol decoding and triggering process.

[0005] In a first aspect, a protocol decoding and triggering method based on envelope detection is provided, which is applied to a digital oscilloscope; the digital oscilloscope includes a hardware circuit and a host computer software; the method includes:

[0006] The hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet;

[0007] The host computer software performs level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet;

[0008] The host computer software searches for the protocol frame header of the binary data packet according to the frame header features of different protocols;

[0009] The upper computer software takes the protocol frame header as a starting point and performs protocol decoding and protocol triggering on the binary data packet.

[0010] Optionally, before the hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet, the method further includes:

[0011] The host computer software obtains the edge parameters and level thresholds preset by the user, and maps the level thresholds to binary bit values ​​at a fixed resolution through quantization;

[0012] The hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet, including:

[0013] The hardware circuit detects the valid edge of the original signal according to the edge parameter and the binary bit value to obtain a valid data packet.

[0014] Optionally, the calculation formula of the binary bit value is as follows:

[0015]

[0016] Among them, vol is the level threshold, scale is the vertical scale of the digital oscilloscope, offset is the vertical bias of the digital oscilloscope, adcBits is the bit width of the digital oscilloscope, and bitval is the binary bit value.

[0017] Optionally, the host computer software performs level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet, including:

[0018] The host computer software converts the floating point level values ​​in the valid data packet that are greater than or equal to the level threshold into a logic value of 1, and converts the floating point level values ​​in the valid data packet that are less than the level threshold into a logic value of 0.

[0019] Optionally, the host computer software takes the protocol frame header as a starting point to perform protocol decoding and protocol triggering on the binary data packet, including:

[0020] The host computer software performs protocol decoding on the binary data packet with the protocol frame header as the starting point to obtain a decoded data packet; the decoded data packet includes field types, data values, start time and end time of multiple fields;

[0021] The host computer software determines the trigger time of the decoding data packet according to the trigger condition input by the user.

[0022] Optionally, the host computer software performs protocol decoding on the binary data packet with the protocol frame header as the starting point to obtain a decoded data packet, including:

[0023] The upper computer software takes the protocol frame header as a starting point, performs data sampling, extraction and separation of protocol information on the binary data packet through a protocol state machine, and obtains a decoded data packet.

[0024] Optionally, before the host computer software uses the protocol frame header as a starting point to perform data sampling, protocol information extraction and separation on the binary data packet through a protocol state machine to obtain a decoded data packet, the method further includes:

[0025] The host computer software generates a protocol state machine according to the protocol frame format of the original signal; the protocol state machine includes an error state for handling any error situation.

[0026] Optionally, the host computer software determines the trigger time of the decoding data packet according to the trigger condition input by the user, including:

[0027] The host computer software determines the target field in the decoded data packet according to the trigger condition input by the user; and determines the end time of the target field as the trigger time of the decoded data packet.

[0028] In a second aspect, a digital oscilloscope based on the protocol decoding and triggering method based on envelope detection according to any one of the first aspects is provided, wherein the digital oscilloscope comprises a hardware circuit and a host computer software;

[0029] The hardware circuit is used to perform envelope detection on the collected original signal to obtain a valid data packet;

[0030] The host computer software is used to perform level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet;

[0031] The host computer software is also used to search for the protocol frame header of the binary data packet according to the frame header features of different protocols;

[0032] The host computer software is also used to perform protocol decoding and protocol triggering on the binary data packet with the protocol frame header as the starting point.

[0033] In a third aspect, the present application provides a computer-readable storage medium having a computer program file stored thereon, and a processor executes the computer program file to implement the protocol decoding and triggering method based on envelope detection described in the first aspect.

[0034] Compared with the prior art, the beneficial effects of the embodiments of the present application are as follows:

[0035] The embodiment of the present application provides a protocol decoding and triggering method based on envelope detection, which is applied to a digital oscilloscope; the digital oscilloscope includes a hardware circuit and a host computer software; the method includes: the hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet; the host computer software performs level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet; the host computer software searches for the protocol frame header of the binary data packet according to the frame header features of different protocols; the host computer software takes the protocol frame header as the starting point, and performs protocol decoding and protocol triggering on the binary data packet.

[0036] In the embodiment of the present application, envelope detection is realized by hardware circuit, valid data packets are screened out, and transmitted to the host computer software, and protocol decoding and triggering are performed by the host computer software, which can avoid software analysis of invalid data packets, save the time of software analysis, thereby improving the efficiency of protocol decoding and triggering. Compared with envelope detection by software, the present application performs envelope detection by hardware circuit, which is faster, and the hardware circuit can use the edge trigger circuit widely used by digital oscilloscopes, and the cost of the hardware circuit will not be increased additionally. And analysis is done at the software layer, which has great flexibility, can be triggered at any position, and can also accurately analyze complex protocols, improve the accuracy of protocol decoding and triggering. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of the structure of a digital oscilloscope provided in an embodiment of the present application;

[0039] Figure 2 A schematic diagram of a flow chart of a protocol decoding and triggering method based on envelope detection provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the flow of envelope detection provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of an invalid data packet and a valid data packet provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of an I2C protocol frame header provided in an embodiment of the present application, wherein the characteristic of the I2C protocol frame header is that when the clock line maintains a high level, the data line changes from a high level to a low level.

[0043] Figure 6 A schematic diagram of a CAN protocol frame header provided in an embodiment of the present application;

[0044] Figure 7 A schematic diagram of a LIN protocol frame header provided in an embodiment of the present application;

[0045] Figure 8 A schematic diagram of a Flexray protocol frame header provided in an embodiment of the present application;

[0046] Fig. 9 A schematic diagram of a USB protocol frame header provided in an embodiment of the present application;

[0047] Fig.10 A schematic diagram of a PCIe protocol frame header provided in an embodiment of the present application;

[0048] Fig.11 A schematic diagram of the CAN protocol frame format provided in an embodiment of the present application;

[0049] Fig.12 A schematic diagram of a setting interface for CAN decoding parameters provided in an embodiment of the present application;

[0050] Fig.13 A schematic diagram of a setting interface for CAN trigger conditions provided in an embodiment of the present application;

[0051] Fig.14 A schematic diagram of the CAN protocol triggering and decoding results provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0053] In order to solve the speed, accuracy and cost problems in the protocol decoding and triggering process, an embodiment of the present application provides a protocol decoding and triggering method based on envelope detection, which is applied to a digital oscilloscope.

[0054] Please refer to Figure 1, is a schematic diagram of the structure of a digital oscilloscope provided in an embodiment of the present application. The digital oscilloscope includes a hardware circuit and a host computer software, and the hardware circuit and the host computer software can communicate with each other.

[0055] Based on the digital oscilloscope of the aforementioned embodiment, Figure 2 The protocol decoding and triggering method based on envelope detection is introduced in the following figure.

[0056] S201, the hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet.

[0057] In a possible embodiment, before executing S201, the method further includes: the host computer software obtains the edge parameter and level threshold preset by the user, and maps the level threshold to a binary bit value at a fixed resolution through quantization.

[0058] The step of S201 includes: the hardware circuit detects the valid edge of the original signal according to the edge parameter and the binary bit value to obtain a valid data packet.

[0059] Please refer to Figure 3 , which is a flow chart of envelope detection provided by an embodiment of the present application. First, the host computer software can set edge parameters and level thresholds, then map the level thresholds to binary bit values ​​at a fixed resolution through quantization, and then send the edge parameters and binary bit values ​​to the hardware circuit, and finally, the hardware circuit detects valid edges according to the edge parameters and binary bit values, filters out valid data packets from the original signal, and uploads them to the host computer software.

[0060] In the specific implementation process, users can set edge parameters and level thresholds in the host computer. The edge parameters are related to the specific format of the protocol. For high-level valid protocol signals, such as CAN, LIN, USB, etc., the edge parameters can be set to the rising edge. For low-level valid protocol signals, such as I2C, Flexray, etc., the edge parameters can be set to the falling edge. The level threshold is determined by the level of the signal. For example, the idle low level of the protocol signal is -1V, and the valid high level is 1V. The value range of the level threshold is (-1,1). In order to avoid the influence of noise, the level threshold is usually set to the middle value, that is, 0V.

[0061] After mapping the level threshold to a binary bit value at a fixed resolution through quantization, the host computer software sends the edge parameter and binary bit value to the hardware circuit, and the hardware circuit detects the valid edge based on the edge parameter and binary bit value. For example, if the edge parameter is a rising edge and the level threshold is 0V, then when the original signal exceeds 0V, it means that a valid edge is detected, and the data segment with a valid signal is screened out, that is, a valid data packet, such as Figure 4 As shown, Figure 4A schematic diagram of an invalid data packet and a valid data packet provided in an embodiment of the present application. After the hardware circuit filters out the valid data packet from the original signal, the valid data packet is transmitted to the host computer software for analysis.

[0062] In the embodiment of the present application, edge detection can effectively reduce the impact of crosstalk on data packet decoding, help to accurately identify the beginning and end of the data packet, and improve the accuracy of valid data packet extraction by accurately capturing the valid signal edge, thereby preventing irrelevant signals from affecting the data decoding process.

[0063] In a possible embodiment, the calculation formula of the binary bit value is as follows:

[0064]

[0065] Among them, vol is the level threshold, scale is the vertical scale of the digital oscilloscope, offset is the vertical offset of the digital oscilloscope, adcBits is the bit width of the digital oscilloscope, and bitval is the binary bit value.

[0066] Quantization is the process of mapping the continuous level of an analog signal to a finite number of discrete values. The vertical scale of a digital oscilloscope refers to the time interval at which the digital oscilloscope samples the analog signal. The vertical offset of a digital oscilloscope refers to a constant voltage offset applied in the vertical direction when the digital oscilloscope measures the signal, so that the display position of the signal is offset to a specific position on the oscilloscope screen. The bit width of a digital oscilloscope refers to the number of binary bits that can represent the amplitude of each sampling point when the digital oscilloscope samples the input analog signal.

[0067] In an embodiment of the present application, the digital oscilloscope accurately quantizes the level threshold of the analog signal according to the vertical scale, vertical offset and bit width settings during sampling, thereby generating a corresponding binary bit value.

[0068] S202 , the upper computer software performs level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet.

[0069] In a possible embodiment, the host computer software converts the floating point level values ​​in the valid data packet that are greater than or equal to the level threshold into a logic value of 1, and converts the floating point level values ​​in the valid data packet that are less than the level threshold into a logic value of 0.

[0070] For example, the specific conversion formula is as follows:

[0071]

[0072] Wherein, x represents the floating-point level value in the valid data packet, threshold represents the level threshold, and f(x) represents the logic value in the binary data packet.

[0073] S203 , the host computer software searches for the protocol frame header of the binary data packet according to the frame header features of different protocols.

[0074] In the specific implementation process, the frame headers of different protocols have different characteristics. The upper computer software can search for the protocol frame header according to the frame header characteristics of different protocols. After searching for the protocol frame header, the start time is recorded. For fixed-rate protocols, the time of the next sampling point can be determined according to the start time.

[0075] Please refer to Figure 5 , which is a schematic diagram of an I2C protocol frame header provided in an embodiment of the present application. The characteristic of the I2C protocol frame header is that when the clock line maintains a high level, the data line changes from a high level to a low level.

[0076] Please refer to Figure 6 , is a schematic diagram of a CAN protocol frame header provided in an embodiment of the present application, and the characteristic of the CAN protocol frame header is: rising edge.

[0077] Please refer to Figure 7 , is a schematic diagram of a LIN protocol frame header provided in an embodiment of the present application, and the characteristics of the LIN protocol frame header are: a low-level segment of no less than 13 bits.

[0078] Please refer to Figure 8 , is a schematic diagram of a Flexray protocol frame header provided in an embodiment of the present application, and the characteristic of the Flexray protocol frame header is: falling edge.

[0079] Please refer to Fig. 9 , is a schematic diagram of a USB protocol frame header provided in an embodiment of the present application. The characteristics of the USB protocol frame header are: the USB+ level state is 10101011, and the USB- level state is 01010100.

[0080] Please refer to Fig.10 , is a schematic diagram of a PCIe protocol frame header provided in an embodiment of the present application. The characteristics of the PCIe protocol frame header are: COMMA code, the level state is 1100000101 or 0011111010.

[0081] S204, the upper computer software takes the protocol frame header as the starting point, and performs protocol decoding and protocol triggering on the binary data packet.

[0082] In a possible embodiment, the host computer software uses the protocol frame header as the starting point to perform protocol decoding on the binary data packet to obtain a decoded data packet; the decoded data packet includes field types, data values, start time and end time of multiple fields; the host computer software determines the trigger time of the decoded data packet based on the trigger conditions input by the user.

[0083] In the specific implementation process, the upper computer software includes a protocol decoding module and a protocol triggering module, and the protocol decoding module can be used to perform protocol decoding on the binary data packet to obtain a decoded data packet. The protocol triggering module can directly obtain the decoded data packet from the protocol decoding module and perform protocol triggering on the decoded data packet based on the triggering conditions input by the user.

[0084] The decoded data packet consists of multiple protocol frames, each of which includes multiple fields, each of which includes field types, data values, start time and end time of multiple fields. The field types include frame header, ID, data, checksum, frame tail and other types. The start time is the time of the first sampling point of the field, and the end time is the time of the last sampling point of the field. The data value is calculated according to the byte order of the protocol. Since the big endian sequence stores the high-order byte of the data at the low address and the low-order byte at the high address, if it is a big endian sequence, the value of the first sampling point is the highest bit, and the value of the last sampling point is the lowest bit.

[0085] For example, the decoded data packet of the CAN protocol is shown in Table 1.

[0086] Table 1

[0087]

[0088] In an embodiment of the present application, protocol triggering is performed directly based on decoded data packets, which can avoid repeated decoding, improve the triggering speed, and ensure the consistency of the decoding result and the triggering result. Since the triggering condition is based on the decoded data packet, the software can more accurately determine the triggering time, reduce false triggering or missed triggering, and optimize the efficiency of real-time response.

[0089] In a possible embodiment, the upper computer software uses the protocol frame header as a starting point to perform protocol decoding on the binary data packet, and the steps of obtaining the decoded data packet include:

[0090] The upper computer software takes the protocol frame header as the starting point, and uses the protocol state machine to perform data sampling, extract and separate the protocol information of the binary data packet to obtain the decoded data packet.

[0091] In the specific implementation process, after obtaining the binary data packet, the protocol decoding module takes the protocol frame header as the starting point, processes the subsequent protocol frame part through the protocol state machine, traverses the binary data packet, and completes data sampling, extraction and separation of protocol information.

[0092] In the data sampling process, for fixed-rate protocol frames, the protocol decoding module can divide the sampling rate by the signal rate to obtain the number of sampling points for each bit. For example, if the sampling rate is 100MSas and the data rate is 5Mbps, then the number of sampling points for each bit is 100MSas / 5Mbps=20Sa. If the sampling point is not specified, the value of each bit is based on the point in the middle of these 20 points.

[0093] During the extraction and separation of protocol information, the protocol decoding module can parse each frame of data according to the format and specifications of the protocol data stream, divide it into field types such as frame header, ID, data, check, frame tail, etc., output the field type, data value, start time and end time of each part of the protocol frame, and finally obtain the decoded data packet.

[0094] In the embodiment of the present application, the state machine gradually parses the binary data packet based on the state transition mode, and the gradual decoding from the frame header to the frame tail can effectively avoid unnecessary resource consumption. If the protocol changes (such as the addition of new fields, the adjustment of the data format), the expansion of the state machine is relatively simple, and only the parsing and processing logic of the new field needs to be added to the state of the corresponding state machine without changing the entire decoding framework, which improves the scalability and adaptability of the protocol parsing system.

[0095] In a possible embodiment, before the host computer software uses the protocol frame header as the starting point and performs data sampling, protocol information extraction and separation on the binary data packet through the protocol state machine to obtain the decoded data packet, the method further includes:

[0096] The upper computer software generates a protocol state machine according to the protocol frame format of the original signal; the protocol state machine includes an error state; the error state is a state used to handle any error situation.

[0097] In the specific implementation process, the protocol decoding module of the host computer software can generate different protocol state machines according to different protocol frame formats. First, the protocol frame format of the original signal is analyzed to identify the frame header, frame tail, field, flag bit, checksum and other information. This information will serve as the design basis of the state machine. Then, according to the protocol frame format, a protocol state machine is designed to simulate the process of protocol parsing. The parsing process of each protocol field can be regarded as a state or a transition condition in the protocol state machine. Among them, the state machine nodes represent the various stages of the protocol (such as frame header parsing, data field parsing, frame tail check, etc.). The state transition condition represents the relationship and dependency between the fields in the protocol (such as specific flag bits, data length, check, etc.).

[0098] For example: a CAN data frame consists of a start bit, an arbitration field, a control field, a data field, a (cyclic redundancy check) field, an acknowledgment (ACK) field, and a frame tail. The corresponding protocol state machine includes an idle state, an arbitration state, a control state, a data state, a CRC state, an ACK state, a frame tail state, and an error state. The error state is intended to deal with errors or half-frames in the protocol frame format.

[0099] In the idle state, the state machine waits for the start signal on the bus. After detecting that the bus is idle, it enters the arbitration state to start transmission. In the arbitration state, the state machine monitors the ID field (arbitration domain) and decides whether to continue sending based on the priority of the bit. The state machine will enter the control state from the arbitration state to parse information such as the data length field (DLC) in the control domain. In the data state, the state machine parses the data field byte by byte to receive and process the data. If the data field does not meet expectations or the data is incomplete, it enters the error state. In the CRC state, the state machine calculates the CRC and compares it with the received CRC value. If the CRC check fails, the state machine jumps to the error state. In the ACK state, the state machine monitors the correctness of the ACK signal. If the ACK signal is not received, it means that the data transmission has failed and enters the error state. In the end of frame state, the state machine ensures the integrity and correct end of the data frame, and then returns to the idle state and waits for the next data transmission. If it is a half frame, it enters the error state. The error state is a state used to handle any error situation.

[0100] In an embodiment of the present application, different protocol state machines can be generated according to different protocol formats and applied to the decoding of binary data packets. This method can not only automate the protocol decoding process and improve data decoding efficiency, but also has flexibility and can adapt to different protocols and communication standards.

[0101] In a possible embodiment, the host computer software determines the trigger time of decoding the data packet according to the trigger condition input by the user, including:

[0102] The upper computer software determines the target field in the decoded data packet according to the trigger condition input by the user; and determines the end time of the target field as the trigger time of the decoded data packet.

[0103] During the specific implementation process, the user can input the trigger conditions. According to different protocol specifications, the protocol trigger can be triggered at the frame header, ID, data, checksum, frame tail, etc.

[0104] If the host computer software determines that the trigger condition input by the user is a preset field type, the target field corresponding to the preset field type in the decoded data packet is determined. For example: if the user sets the trigger condition of the CAN protocol to the start bit, the protocol trigger module of the host computer software will search for a field with a field type of the start bit in the decoded data packet, and determine the end time of the field as the trigger time of the decoded data packet.

[0105] If the host computer software determines that the trigger condition input by the user is the data type and the preset data value, the target field corresponding to the data type and the preset data value in the decoded data packet is determined. For example: the user sets the trigger condition of the CAN protocol as the data type, and the triggered data value is 0x33, then the protocol trigger module of the host computer software will search for a field with the field type as the data type and the data value as 0x33 in the decoded data packet, and determine the end time of the 0x33 field as the trigger time of the decoded data packet.

[0106] In the embodiment of the present application, users can define trigger conditions in the host computer software according to actual needs, which can provide them with more flexible configuration options, so that they can make adjustments according to specific scenarios when using the software to meet personalized needs. By using the end time of the target field as the trigger point, users can very accurately control when to trigger a specific event or operation, which is very important for real-time data processing and high-precision control systems.

[0107] The following describes in detail the technical effects of the protocol decoding and triggering method based on envelope detection provided in the embodiment of the present application in combination with actual engineering tests.

[0108] The CAN standard waveform is transmitted through the arbitrary waveform generator. The protocol frame format is as follows Fig.11 As shown, the CAN protocol has differential signals: CANH and CANL. This test uses the CANH signal, with a high level as recessive "1" and a low level as dominant "0". The baud rate is 1Mbps. The waveform is collected by a digital oscilloscope, and the protocol decoding and triggering method based on envelope detection proposed in this application is used for online analysis.

[0109] Please refer to Fig.12 , which is a schematic diagram of the setting interface of the CAN decoding parameters provided in an embodiment of the present application, the setting type is the standard CAN type, the data source is channel 1, the threshold is 0V, the baud rate is 1Mbps, the sampling point is 80%, and the signal type is a high-level signal line.

[0110] Please refer to Fig.13 , is a schematic diagram of the setting interface of the CAN trigger condition provided in the embodiment of the present application, the trigger condition is set to frame data, and the specified value is 0x33. If triggered correctly, the trigger time will be at the last sampling point position of 0x33 in the data part.

[0111] Please refer to Fig.14 , which is a schematic diagram of the CAN protocol decoding and triggering results provided in the embodiment of the present application. The value of each field of the protocol frame in the decoding result is drawn below the waveform, where 0x112 is the frame ID, 0x0~0x77 is the frame data part, 0x592D is the CRC, and 0x7F is the frame tail. The range of each field is from the position of the first sampling point to the position of the last sampling point. At the same time, there are corresponding decoding results in the table, one row represents a complete frame, and one column represents a field of the frame. The position marked with a small triangle in the rectangular box is the trigger time, corresponding to the last sampling point position of 0x33.

[0112] In summary, the embodiment of the present application provides a protocol decoding and triggering method based on envelope detection, which is effective for decoding and triggering of bus protocols. Hardware pre-triggering based on envelope detection can reduce the analysis of invalid data packets and improve the speed and accuracy of protocol decoding. Software-based protocol decoding and triggering can process protocol frames more flexibly, cope with complex and high-speed protocols, and implement protocol triggering based on protocol decoding results, reduce the amount of calculation, and ensure that the decoding and triggering results are consistent. Using the general hardware circuit structure of a digital oscilloscope, additional hardware costs can be avoided.

[0113] Based on the same inventive concept, the embodiment of the present application also provides a digital oscilloscope based on a protocol decoding and triggering method of envelope detection, the digital oscilloscope comprising a hardware circuit and a host computer software;

[0114] The hardware circuit is used to perform envelope detection on the collected original signal to obtain a valid data packet;

[0115] The upper computer software is used to perform level conversion on the valid data packet according to the preset level threshold to obtain a binary data packet;

[0116] The host computer software is also used to search for the protocol frame header of the binary data packet according to the frame header features of different protocols;

[0117] The host computer software is also used to perform protocol decoding and protocol triggering on the binary data packets starting from the protocol frame header.

[0118] It should be noted that each module in the protocol decoding and triggering device based on envelope detection in this embodiment corresponds one-to-one to each step in the protocol decoding and triggering method based on envelope detection in the aforementioned embodiment. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned protocol decoding and triggering method based on envelope detection, which will not be repeated here.

[0119] In addition, in one embodiment, the present application also provides a computer storage medium, on which a computer program file is stored, and when the computer program file is executed by a processor, the aforementioned protocol decoding and triggering method based on envelope detection is implemented.

[0120] In some embodiments, the computer readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or various devices including one or any combination of the above memories. The computer may be various computing devices including intelligent terminals and servers.

[0121] In some embodiments, executable instructions may be in the form of program files, software, software modules, scripts or codes, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as stand-alone program files or as modules, components, subroutines or other units suitable for use in a computing environment.

[0122] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other program files or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program file in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutine files, or code portions).

[0123] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0124] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0125] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0126] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for a multimedia terminal device to execute the methods described in each embodiment of the present application.

[0127] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A protocol decoding and triggering method based on envelope detection, characterized in that: Applied in a digital oscilloscope; the digital oscilloscope includes a hardware circuit and a host computer software; the method includes: The hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet; The host computer software performs level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet; The host computer software searches for the protocol frame header of the binary data packet according to the frame header features of different protocols; The upper computer software takes the protocol frame header as a starting point and performs protocol decoding and protocol triggering on the binary data packet.

2. The protocol decoding and triggering method based on envelope detection as claimed in claim 1, characterized in that: Before the hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet, the method further includes: The host computer software obtains the edge parameters and level thresholds preset by the user, and maps the level thresholds to binary bit values ​​at a fixed resolution through quantization; The hardware circuit performs envelope detection on the collected original signal to obtain a valid data packet, including: The hardware circuit detects the valid edge of the original signal according to the edge parameter and the binary bit value to obtain a valid data packet.

3. The protocol decoding and triggering method based on envelope detection as claimed in claim 2, characterized in that: The calculation formula of the binary bit value is as follows: Among them, vol is the level threshold, scale is the vertical scale of the digital oscilloscope, offset is the vertical bias of the digital oscilloscope, adcBits is the bit width of the digital oscilloscope, and bitval is the binary bit value.

4. The protocol decoding and triggering method based on envelope detection as claimed in claim 1, characterized in that: The host computer software performs level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet, including: The host computer software converts the floating point level values ​​in the valid data packet that are greater than or equal to the level threshold into a logic value of 1, and converts the floating point level values ​​in the valid data packet that are less than the level threshold into a logic value of 0.

5. The protocol decoding and triggering method based on envelope detection as claimed in claim 1, characterized in that: The host computer software takes the protocol frame header as a starting point, performs protocol decoding and protocol triggering on the binary data packet, including: The host computer software performs protocol decoding on the binary data packet with the protocol frame header as the starting point to obtain a decoded data packet; the decoded data packet includes field types, data values, start time and end time of multiple fields; The host computer software determines the trigger time of the decoding data packet according to the trigger condition input by the user.

6. The protocol decoding and triggering method based on envelope detection as claimed in claim 5, characterized in that: The host computer software uses the protocol frame header as a starting point to perform protocol decoding on the binary data packet to obtain a decoded data packet, including: The upper computer software takes the protocol frame header as a starting point, performs data sampling, protocol information extraction and separation on the binary data packet through a protocol state machine, and obtains a decoded data packet.

7. The protocol decoding and triggering method based on envelope detection as claimed in claim 6, characterized in that: Before the host computer software uses the protocol frame header as a starting point to extract and separate the binary data packet, extract and separate the protocol information through the protocol state machine to obtain the decoded data packet, the method further includes: The host computer software generates a protocol state machine according to the protocol frame format of the original signal; the protocol state machine includes an error state for handling any error situation.

8. The protocol decoding and triggering method based on envelope detection as claimed in claim 5, characterized in that: The host computer software determines the trigger time of the decoded data packet according to the trigger condition input by the user, including: The host computer software determines the target field in the decoded data packet according to the trigger condition input by the user; and determines the end time of the target field as the trigger time of the decoded data packet.

9. A digital oscilloscope based on the protocol decoding and triggering method based on envelope detection as claimed in any one of claims 1 to 8, characterized in that: The digital oscilloscope includes a hardware circuit and a host computer software; The hardware circuit is used to perform envelope detection on the collected original signal to obtain a valid data packet; The host computer software is used to perform level conversion on the valid data packet according to a preset level threshold to obtain a binary data packet; The host computer software is also used to search for the protocol frame header of the binary data packet according to the frame header features of different protocols; The host computer software is also used to perform protocol decoding and protocol triggering on the binary data packet with the protocol frame header as the starting point.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program file, and the processor executes the computer program file to implement the protocol decoding and triggering method based on envelope detection as described in any one of claims 1 to 8.

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