Enhanced QOI encoder realized based on FPGA

Abstract

The invention relates to the field of image lossless coding, and provides an enhanced QOI encoder realized based on an FPGA. The design is based on an enhanced QOI encoding strategy, and the encoder consists of an input bit width conversion module, a JPEG-LS predictor, an enhanced QOI encoding unit, an encoding group FIFO module, a compact bit width conversion module and a keep signal specification module, and has the characteristics of higher throughput rate, good time sequence performance and lower hardware resource consumption. A core component JPEG-LS predictor and an enhanced QOI coding unit adopt pipeline design, and two pixels can be coded in each clock period; coding of images with any resolution ratio is supported (only the image width is required to be an even number); 64-bit AXI Stream bus interfaces are adopted for input pixel streams and output coded data streams, and coded data output does not carry null bytes, so that DMA (direct memory access) transmission is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of lossless image coding, and specifically designs an enhanced QOI encoder based on FPGA. The encoder is based on an enhanced QOI coding strategy and aims to improve the efficiency and throughput of QOI image coding through a programmable hardware circuit. Background Art

[0002] With the rapid development of digital image technology, image coding technology has become an important part of the field of digital image processing. As an emerging image lossless coding algorithm, QOI (Quite OK Image) has shown great potential in the field of image storage and transmission due to its simplicity, efficiency, and fast encoding and decoding speed. However, the existing QOI coding implementation mainly relies on the software platform, and its performance is limited by the computing power and memory bandwidth of general-purpose processors. Therefore, exploring the hardware implementation of QOI coding strategy is of great significance to improving the speed and efficiency of image coding. Summary of the invention

[0003] The present invention proposes a hardware implementation method of a QOI image coding strategy. The coding strategy comes from the patent "An Improved QOI Image Coding Strategy", which is called an enhanced QOI coding strategy in the present invention. The enhanced QOI encoder implemented based on FPGA converts the image pixel stream (RGB888, 24-bit true color, pixels contain three colors of red, green and blue, each color is represented by 8 bits) into an enhanced QOI coded data stream. Both the pixel stream and the coded data stream comply with the AXI Stream bus interface protocol, and the bus data bit width is 64 bits. The enhanced QOI encoder is mainly composed of input bit width conversion, JPEG-LS predictor, enhanced QOI coding unit, coding group FIFO, compact bit width conversion and keep signal specification module. Its hardware architecture is as follows Figure 1 shown.

[0004] The input bit width conversion module converts the input pixel stream from 64 bits to 48 bits to achieve parallel input of two pixels.

[0005] Both the JPEG-LS predictor and the enhanced QOI coding unit are pipelined to encode two pixels per clock cycle.

[0006] The predictor calculates the predicted values ​​of two pixels according to the rules, and inputs them together with the original pixel values ​​into the enhanced QOI encoding unit for enhanced QOI encoding, and outputs a 9-byte coding group, which has a maximum of 9 valid bytes.

[0007] The code group FIFO acts as a buffer for code group data.

[0008] The function of the compact bit width conversion module is to generate two 8-byte outputs from a 9-byte fully valid 9-byte code group.

[0009] The keep signal specification module compacts the AXIS encoded data stream and removes null bytes. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 To enhance the hardware architecture of the QOI encoder;

[0011] Figure 2 This is an example of bit width conversion of the input pixel stream (the image resolution is 24*24);

[0012] Figure 3 is the JPEG-LS prediction rule;

[0013] Figure 4 The composition of the 9-byte code group output by the enhanced QOI code unit;

[0014] Figure 5 Two possible cases of 9-byte code groups are shown;

[0015] Figure 6 This is a preliminary shaping diagram of a 9-byte code group;

[0016] Figure 7 Schematic diagram of a 16-byte ring register buffer. DETAILED DESCRIPTION

[0017] To further illustrate the design points and advantages of the enhanced QOI encoder, Figure 1 The encoder architecture shown in the figure introduces the functions and design ideas of each sub-module one by one.

[0018] The encoder consists of input bit width conversion, JPEG-LS predictor, enhanced QOI coding unit, coding group FIFO, compact bit width conversion and keep signal specification.

[0019] Input bit width conversion converts the data bit width of the input pixel stream from 64 bits to 48 bits. Taking an image with a resolution of 24×24 as an example, the bit width conversion of the input pixel stream is as follows: Figure 2 As shown, there are a total of 216 data transmissions on the input AXIS bus, and there are no empty bytes in the data. When the image width × height is divisible by 8, it can be ensured that all the transmissions on the input AXIS are valid bytes.

[0020] After the bit width is converted to 48 bits (2 pixels in parallel), the transmission becomes 288 records. The input bit width conversion can be implemented by using a state machine to control the ready signal of the input AXIS. Every 2 64-bit data inputs are converted into 3 48-bit data outputs.

[0021] The predictor processes 2 pixels at a time and performs the following Figure 3 The simple nonlinear prediction shown generates predicted values ​​for the corresponding positions.

[0022] The predicted value at position x is determined based on the values ​​of the surrounding pixels. When pixels a, b, and c do not exist, that is, x is located in the upper left corner of the image, the first pixel of the image is being encoded, and the predicted value x is {0, 0, 0}; when pixels b and c do not exist, X is located in the first row of the image, and the predicted value x is the value of pixel a; when a and c do not exist, x is located in the first column of the image, and the predicted value x is the value of pixel b. In general, if c is greater than or equal to the maximum value of a and b, the predicted value x takes the minimum value of a and b; if c is less than or equal to the minimum value of a and b, the predicted value x takes the maximum value of a and b; if neither of the first two conditions is met, the predicted value x is equal to a+bc.

[0023] The predictor is a fully pipelined data flow processing unit with a total of 3 pipeline stages, outputting the original pixel value and predicted value of 2 pixels, a total of 96 bits. In order to avoid the situation where 2 pixels span 2 rows, the width of the input image is limited to an even number to simplify the design.

[0024] The enhanced QOI coding unit performs enhanced QOI coding according to the pixels and their predicted values ​​to generate a coding group. The enhanced QOI coding unit is also a fully pipelined data flow processing unit with a total of 8 pipeline stages, encoding 2 pixels each time, the first 6 stages complete the coding, and the last 2 stages reshape the coding group.

[0025] The enhanced QOI encoding strategy provides 7 encoding strategies, which are QOI_RUN, QOI_INDEX, QOI_DIFF1, QOI_DIFF2, QOI_LUMA, QOI_DIFF3 and QOI_RGB in order of priority from high to low. The corresponding encoding byte lengths also increase in sequence. QOI_RUN, QOI_INDEX and QOI_DIFF1 are the shortest, requiring only 1 byte, and QOI_RGB is the longest, requiring 4 bytes.

[0026] During the encoding process, all six encoding strategies except QOI_RGB will be judged. Since the enhanced QOI encoding unit encodes two pixels in parallel, the correlation between the two encoded pixels must also be considered. The judgment process is orderly distributed in the first five pipelines. The two pixels involved in the encoding each have a 6-bit encoding flag. If they meet a certain encoding strategy, the corresponding encoding flag is marked. Finally, the final encoding is completed in the sixth pipeline according to the priority of the encoding flag (the priority of the encoding strategy) to generate a 9-byte encoding group.

[0027] The composition of the 9-byte code group is as follows Figure 4 As shown, it consists of two pixel coding groups plus a leading RUN code. There may be empty bytes in the coding group. The 9-byte coding group carries a 9-bit keep signal. 0 in the keep signal indicates that the corresponding position of the coding group is an empty byte. Figure 5 (a) and Figure 5 (b) Two possible cases of a 9-byte code group are given.

[0028] The 7th and 8th pipelines of the enhanced QOI coding unit implement the initial shaping of the coding group. Figure 5 The shaping process of the coding group shown in (a) is as follows Figure 6 As shown, Figure 5 (b) shows that the code group has been shaped, and the final 9-byte code group byte data is right-aligned. In addition, the code group data has a 4-bit user signal to indicate the effective length of the code group.

[0029] The compact bit width conversion converts the 72-bit code group output to 64 bits (64 bits is the data bit width commonly used for DMA, Direct Memory Access, direct memory access) to prepare for the subsequent keep signal normalization. This bit width conversion is only valid for the preceding RUN code, and the two pixel codes are both QOI_RGB coded code groups. At this time, the effective byte number is 9 bytes. The compact bit width conversion module divides it into two 8-byte and outputs it in 2clks. Code groups of other lengths are directly truncated into 8 bytes for transmission. The probability of the effective byte number of the code group being 9 bytes is relatively small, which is a special case. This simple processing method can simplify the hardware design, and the throughput loss caused by it is almost negligible.

[0030] Both the JPEG-LS predictor and the enhanced QOI coding unit are pipelined and use common data interfaces (data signals and valid signals). Figure 1As shown in the figure (the small rectangle represents the AXIS bus interface), the compact bit width conversion will block the input when processing the coding group with a valid byte number of 9 bytes, affecting the previous pipeline prediction and encoding. Therefore, a coding group FIFO is added before the compact bit width conversion for buffering. When the compact bit width conversion module is blocked, the FIFO caches the coding group data. When the accumulated data volume reaches the set threshold, s_ready will be lowered. At this time, the data input to the JPEG-LS predictor is blocked and the pipeline is paused. The threshold is set reasonably to ensure that the coding group FIFO does not overflow when caching the coding group data.

[0031] After the enhanced QOI coding unit's initial shaping and compact bit width transformation, the AXIS data stream still has a large number of empty bytes. Most DMAs do not allow empty bytes to appear in the AXIS data stream. Therefore, it is necessary to use the keep signal normalization module to integrate the sparse encoded data and remove the empty bytes.

[0032] The keep signal normalization module uses a 16-byte ring register buffer divided into two domains to splice sparse coded data, such as Figure 7 As shown, the write domain pointer points to the domain where the write byte pointer is located, and the read pointer points to another domain. Each time 8 bytes of data are input, the valid bytes are written into the ring register in sequence, and the write byte pointer is updated. If the updated write pointer crosses the domain boundary, the read and write domain pointers are swapped. At this time, the domain pointed to by the read domain pointer (a total of 8 bytes of data) can be read out.

[0033] The board was put into logic synthesis, and the FPGA device model was selected as Xilinx xc7z020clg400-2. The clock period was set to 6ns (that is, the clock frequency was 167MHz), the clock uncertainty was set to 10% of the clock period, and the setup time margin of the worst path was 0.549ns. Therefore, the encoder met the target clock frequency of 167MHz.

[0034] In terms of resource consumption, this design uses 439 Slices (configurable logic units inside FPGA, consisting of lookup tables LUTs, flip-flops FFs, multiplexers Mux, and carry chains) and 2.5 BRAMs (36kb).

[0035] The paper "High-throughput architecture for b oThe JPEG-LS lossless coding algorithm with 2 degrees of parallelism is implemented on FPGA. The FPGA model used in the design is XILINX Virtex6-75t, and the resource consumption is Slice: 8.3K, BRAM (36kb): 7. In comparison, the enhanced QOI encoder proposed in the present invention has advantages in resource consumption.

Claims

1. An enhanced QOI encoder based on FPGA, characterized in that: The encoder converts the image pixel stream (RGB888) into an enhanced QOI encoded data stream. Both the pixel stream and the encoded data stream comply with the AXI Stream bus interface protocol, and the bus data bit width is 64 bits. The encoder is mainly composed of input bit width conversion, JPEG-L predictor, enhanced QOI encoding unit, encoding group FIFO, compact bit width conversion and keep signal specification module.

2. The JPEG-LS predictor according to claim 1, characterized in that Two pixels are processed each time, nonlinear prediction is performed and prediction values ​​of corresponding positions are generated, and the JPEG-LS predictor is a fully-pipeline data flow processing unit with three pipeline stages.

3. The enhanced QOI coding unit according to claim 1, characterized in that: Two pixels are processed each time, and enhanced QOI coding is performed according to the pixels and their predicted values ​​to generate a right-aligned coding group, and the coding unit is a full-pipeline data flow processing unit with 8 pipeline stages.

4. The coding group FIFO according to claim 1, characterized in that: The coding group data is buffered before the compact bit width conversion. When the accumulated data volume reaches the set threshold, the data input to the JPEG-LS predictor will be blocked to pause the pipeline and ensure that the coding group FIFO will not overflow when caching the coding group data.

5. The keep signal normalization module according to claim 1, characterized in that: A 16-byte ring register buffer divided into two domains is used to splice sparse coded data. When the updated write byte pointer crosses the domain boundary, the read and write domain pointers are swapped. At this time, the domain pointed to by the read domain pointer (a total of 8 bytes of data) can be read out.

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