Downlink fault detection method and device, access network equipment and medium

Abstract

The invention discloses a downlink fault detection method and device, access network equipment and a medium, and relates to the field of wireless communication. According to the specific implementation scheme, when it is monitored that a downlink of a target cell breaks down, test parameters of the target cell under a current wireless frame are read from a storage module in a processing chip of a BBU; determining scheduling parameters and cell parameters according to the test parameters; the scheduling parameters and the cell parameters are serially input into a bit-level processing module, a symbol-level processing module, a compression module and a CA switching module in the processing chip; and determining the fault reason of the downlink according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module. Therefore, the processing chip of the BBU is subjected to module division, and when the downlink between the BBU and the AAU has a fault, each module in the processing chip is tested based on the test parameters, so that the fault reason of the downlink can be accurately positioned according to the actual output of each module.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a downlink fault detection method, device, access network equipment and medium. Background Art

[0002] In wireless communication systems (such as LTE (Long Term Evolution) communication systems and NR (New Radio) communication systems), the simple structure can be divided into two major subsystems: BBU (Building Baseband Unit) and AAU (Active Antenna Unit). When a downlink failure occurs between the BBU and AAU, it is very important to locate the cause of the failure, repair the downlink failure according to the cause of the failure, improve the stability of the downlink, and improve the reliability and effectiveness of data transmission. Summary of the invention

[0003] The present application provides a downlink fault detection method, apparatus, access network equipment and medium.

[0004] According to one aspect of the present application, a downlink fault detection method is provided, comprising: when a downlink fault is detected in a target cell, reading test parameters of the target cell in the current wireless frame from a storage module in a processing chip of an indoor baseband processing unit BBU; wherein the downlink includes a communication link between the BBU and an active antenna unit AAU corresponding to the target cell; determining scheduling parameters and cell parameters according to the test parameters; serially inputting the scheduling parameters and cell parameters into a bit-level processing module, a symbol-level processing module, a compression module and a carrier antenna CA switching module in the processing chip; and determining the cause of the downlink fault according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0005] As a possible implementation manner, determining the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module includes: obtaining a first actual output of the CA switching module, and determining whether a processing chip fails according to the first actual output; if the processing chip fails, obtaining a second actual output of a target processing module; wherein the target processing module includes a bit-level processing module and / or a symbol-level processing module; and determining the cause of the failure of the processing chip in the downlink according to the second actual output.

[0006] As a possible implementation manner, determining whether the processing chip fails according to the first actual output includes: querying the first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by simulating the CA switching module according to the test parameters; when the first standard output does not match the first actual output, determining that the processing chip fails; when the first standard output matches the first actual output, determining that the processing chip does not fail.

[0007] As a possible implementation method, determining the cause of the failure of the processing chip in the downlink according to the second actual output includes: obtaining the second actual output of the symbol-level processing module in the processing chip; querying the second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; and when the second actual output of the symbol-level processing module matches the second standard output, determining that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0008] As a possible implementation method, determining the cause of the failure of the processing chip in the downlink based on the second actual output also includes: when the second actual output of the symbol-level processing module does not match the second standard output, obtaining the second actual output of the bit-level processing module; querying the third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by simulating the bit-level processing module according to the test parameters; when the second actual output of the bit-level processing module matches the third standard output, determining that the cause of the failure of the processing chip in the downlink is that the symbol-level processing module has a failure.

[0009] As a possible implementation method, determining the cause of failure of the processing chip in the downlink based on the second actual output also includes: when the second actual output of the bit-level processing module does not match the third standard output, determining that the cause of failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0010] As a possible implementation method, determining the cause of the downlink failure based on the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module also includes: if the processing chip does not fail, determining that the cause of the downlink failure is a failure in layer 2 in the BBU or a failure in the AAU.

[0011] As a possible implementation method, a storage module is used to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in a current wireless frame, and the current wireless frame includes M subframes, where M is a positive integer; when a downlink failure of the target cell is monitored, the test parameters of the target cell in the current wireless frame are read from the storage module in the processing chip in the indoor baseband processing unit BBU corresponding to the target cell, including: when a downlink failure in the target cell is monitored, performing a first reading process M times on the storage module; using the data read by the i-th first reading process as the sub-test parameter of the i-th subframe; wherein i is a positive integer not greater than M; and determining the test parameter based on the sub-test parameters of the M subframes.

[0012] As a possible implementation method, when a downlink failure is detected in the target cell, a first reading process is performed M times on the storage module, including: determining a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; for the i-th first reading process, determining a target storage address from each candidate storage address; wherein the target storage address is used to store the sub-test parameters of the i-th subframe; according to the target data volume and the total data volume stored in the target storage address, performing a second reading process N times on the storage module; wherein the target data volume is used to indicate the data volume read in a single time; N is determined according to the ratio of the total volume to the target data volume; and using the data read by the N second reading processes as the data read by the i-th first reading process.

[0013] As a possible implementation method, the first second reading process includes: determining the base address for starting to read in the first second reading process according to the first storage address among each target storage address; starting from the base address read in the first second reading process, reading the target data amount of data, and using it as the data read in the first second reading process; determining the base address for starting to read in the second second reading process according to the end address at which the first second reading process ends reading; the non-first second reading process includes: starting from the base address read in this second reading process, reading the target data amount of data, and using it as the data read in this second reading process; determining the base address for starting to read in the next second reading process according to the end address at which the second reading process ends reading.

[0014] As a possible implementation method, scheduling parameters and cell parameters are determined according to test parameters, including: storing the data read by each second reading process in a cache module in the processing chip in sequence; reading scheduling parameters from the first storage area in the cache module; and reading cell parameters from the second storage area in the cache module.

[0015] As a possible implementation method, the data read by each second reading process is sequentially stored in a cache module in the processing chip, including: for any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to the cell from the data read by any second reading process; according to the first output format of the PCIE interface in the processing chip, format conversion is performed on the first sub-parameter to obtain a first sub-parameter of the first output format; wherein the first output format is determined according to the data format of the actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; according to the second output format of the PCIE interface in the processing chip, format conversion is performed on the second sub-parameter to obtain a second sub-parameter of the second output format; wherein the second output format is determined according to the data format of the actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; the first sub-parameter of the first output format is cached in the first storage area, and the second sub-parameter of the second output format is cached in the second storage area.

[0016] As a possible implementation, when a downlink failure of the target cell is detected, the method further includes: disconnecting the communication link between the PCIE interface and the bit-level processing module; and establishing a communication link between the storage unit and the bit-level processing module.

[0017] As a possible implementation, the processing chip is a field programmable gate array FPGA, and the storage module is a double data rate synchronous dynamic random access memory DDR SDRAM.

[0018] According to another aspect of the present application, an access network device is provided, including:

[0019] Memory, transceiver, processor:

[0020] A memory for storing computer programs; a transceiver for transmitting and receiving data under the control of a processor; a processor for reading the computer program in the memory and performing the following operations: when a downlink failure of a target cell is detected, reading the test parameters of the target cell in the current wireless frame from a storage module in a processing chip of a BBU; wherein the downlink includes a communication link between the BBU and an AAU corresponding to the target cell; determining scheduling parameters and cell parameters according to the test parameters; serially inputting the scheduling parameters and cell parameters into a bit-level processing module, a symbol-level processing module, a compression module and a CA switching module in the processing chip; and determining the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0021] As a possible implementation manner, the processor determines the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module, specifically: obtaining the first actual output of the CA switching module, and determining whether the processing chip fails according to the first actual output; if the processing chip fails, obtaining the second actual output of the target processing module; wherein the target processing module includes a bit-level processing module and / or a symbol-level processing module; and determining the cause of the failure of the processing chip in the downlink according to the second actual output.

[0022] As a possible implementation manner, the processor executes to determine whether the processing chip fails based on the first actual output, specifically: querying the first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by simulating the CA switching module according to the test parameters; when the first standard output does not match the first actual output, determining that the processing chip fails; when the first standard output matches the first actual output, determining that the processing chip does not fail.

[0023] As a possible implementation method, the processor executes to determine the cause of the failure of the processing chip in the downlink according to the second actual output, specifically: obtaining the second actual output of the symbol-level processing module in the processing chip; querying the second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; when the second actual output of the symbol-level processing module matches the second standard output, determining that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0024] As a possible implementation method, the processor executes to determine the cause of the failure of the processing chip in the downlink based on the second actual output, specifically: when the second actual output of the symbol-level processing module does not match the second standard output, obtain the second actual output of the bit-level processing module; query the third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by simulating the bit-level processing module according to the test parameters; when the second actual output of the bit-level processing module matches the third standard output, determine that the cause of the failure of the processing chip in the downlink is that the symbol-level processing module has a failure.

[0025] As a possible implementation method, the processor determines the cause of the failure of the processing chip in the downlink based on the second actual output, specifically: when the second actual output of the bit-level processing module does not match the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0026] As a possible implementation method, the processor determines the cause of the downlink failure based on the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module. Specifically, if the processing chip does not fail, it is determined that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

[0027] As a possible implementation method, the storage module is used to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in a current wireless frame, and the current wireless frame includes M subframes, where M is a positive integer; when the processor monitors that a downlink failure occurs in the target cell, the processor reads the test parameters of the target cell in the current wireless frame from the storage module in the processing chip in the indoor baseband processing unit BBU corresponding to the target cell, specifically: when a downlink failure occurs in the target cell, the storage module is executed M times the first reading process; the data read by the i-th first reading process is used as the sub-test parameter of the i-th subframe; wherein i is a positive integer not greater than M; and the test parameter is determined based on the sub-test parameters of the M subframes.

[0028] As a possible implementation method, when the processor monitors that a downlink failure occurs in the target cell, the processor executes a first reading process on the storage module M times, specifically: determining a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; for the i-th first reading process, determining the target storage address from each candidate storage address; wherein the target storage address is used to store the sub-test parameters of the i-th subframe; according to the target data amount and the total data amount stored in the target storage address, executing a second reading process on the storage module N times; wherein the target data amount is used to indicate the amount of data read in a single time; N is determined according to the ratio of the total amount to the target data amount; and the data read by the N second reading processes are used as the data read by the i-th first reading process.

[0029] As a possible implementation method, the processor executes the first second reading process, specifically: according to the first storage address in each target storage address, determine the base address for starting to read in the first second reading process; starting from the base address read in the first second reading process, read the target data amount of data, and use it as the data read in the first second reading process; according to the end address where the first second reading process ends, determine the base address for starting to read in the second second reading process; the processor executes the non-first second reading process, specifically: starting from the base address read in this second reading process, read the target data amount of data, and use it as the data read in this second reading process; according to the end address where the second reading process ends, determine the base address for starting to read in the next second reading process.

[0030] As a possible implementation method, the processor executes to determine the scheduling parameters and cell parameters based on the test parameters, specifically: the data read by each second reading process is stored in the cache module in the processing chip in sequence; the scheduling parameters are read from the first storage area in the cache module; and the cell parameters are read from the second storage area in the cache module.

[0031] As a possible implementation method, the processor executes to store the data read by each second reading process in sequence into a cache module in the processing chip, specifically: for any second reading process, extract a first sub-parameter related to scheduling and a second sub-parameter related to the cell from the data read by any second reading process; according to the first output format of the PCIE interface in the processing chip, the first sub-parameter is format-converted to obtain a first sub-parameter of the first output format; wherein the first output format is determined according to the data format of the actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; according to the second output format of the PCIE interface in the processing chip, the second sub-parameter is format-converted to obtain a second sub-parameter of the second output format; wherein the second output format is determined according to the data format of the actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; the first sub-parameter of the first output format is cached to the first storage area, and the second sub-parameter of the second output format is cached to the second storage area.

[0032] As a possible implementation method, the processor is also used to perform the following operations: when a downlink failure of the target cell is detected, disconnect the communication link between the PCIE interface and the bit-level processing module; and establish a communication link between the storage unit and the bit-level processing module.

[0033] As a possible implementation, the processing chip is a field programmable gate array FPGA, and the storage module is a double data rate synchronous dynamic random access memory DDR SDRAM.

[0034] According to another aspect of the present application, a downlink fault detection device is provided, comprising:

[0035] A reading unit is used to read the test parameters of the target cell in the current radio frame from the storage module in the processing chip of the indoor baseband processing unit BBU when a downlink failure of the target cell is detected; wherein the downlink includes a communication link between the BBU and the active antenna unit AAU corresponding to the target cell;

[0036] A first determining unit, configured to determine a scheduling parameter and a cell parameter according to a test parameter;

[0037] An input unit, used to serially input the scheduling parameters and cell parameters into the bit-level processing module, the symbol-level processing module, the compression module and the carrier antenna CA switching module in the processing chip;

[0038] The second determining unit is used to determine the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0039] As a possible implementation method, the second determination unit is specifically used to: obtain a first actual output of the CA switching module, and determine whether the processing chip fails based on the first actual output; if the processing chip fails, obtain a second actual output of the target processing module; wherein the target processing module includes a bit-level processing module and / or a symbol-level processing module; and determine the cause of the failure of the processing chip in the downlink based on the second actual output.

[0040] As a possible implementation method, the second determination unit is specifically used to: query the first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by simulating the CA switching module according to the test parameters; when the first standard output does not match the first actual output, it is determined that the processing chip has failed; when the first standard output matches the first actual output, it is determined that the processing chip has not failed.

[0041] As a possible implementation method, the second determination unit is specifically used to: obtain a second actual output of the symbol-level processing module in the processing chip; query a second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; and when the second actual output of the symbol-level processing module matches the second standard output, determine that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0042] As a possible implementation method, the second determination unit is also used to: when the second actual output of the symbol-level processing module does not match the second standard output, obtain the second actual output of the bit-level processing module; query the third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by simulating the bit-level processing module according to the test parameters; when the second actual output of the bit-level processing module matches the third standard output, determine that the cause of the failure of the processing chip in the downlink is a failure of the symbol-level processing module.

[0043] As a possible implementation manner, the second determination unit is further used to: when the second actual output of the bit-level processing module does not match the third standard output, determine that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0044] As a possible implementation manner, the second determination unit is further used to: if the processing chip does not fail, determine that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

[0045] As a possible implementation method, the storage module is used to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current wireless frame, and the current wireless frame includes M subframes, where M is a positive integer; the reading unit is specifically used to: when a downlink failure is detected in the target cell, perform M first reading processes on the storage module; use the data read by the i-th first reading process as the sub-test parameters of the i-th subframe; wherein i is a positive integer not greater than M; and determine the test parameters based on the sub-test parameters of the M subframes.

[0046] As a possible implementation method, the reading unit is specifically used to: determine a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; for the i-th first reading process, determine the target storage address from each candidate storage address; wherein the target storage address is used to store the sub-test parameter of the i-th subframe; according to the target data amount and the total data amount stored in the target storage address, perform N second reading processes on the storage module; wherein the target data amount is used to indicate the amount of data read in a single time; N is determined according to the ratio of the total amount to the target data amount; and use the data read by the N second reading processes as the data read by the i-th first reading process.

[0047] As a possible implementation method, the first second reading process includes: determining the base address for starting to read in the first second reading process according to the first storage address among each target storage address; starting from the base address read in the first second reading process, reading the target data amount of data, and using it as the data read in the first second reading process; determining the base address for starting to read in the second second reading process according to the end address at which the first second reading process ends reading; the non-first second reading process includes: starting from the base address read in this second reading process, reading the target data amount of data, and using it as the data read in this second reading process; determining the base address for starting to read in the next second reading process according to the end address at which the second reading process ends reading.

[0048] As a possible implementation method, the first determination unit is specifically used to: store the data read by each second reading process into a cache module in the processing chip in sequence; read the scheduling parameters from the first storage area in the cache module; and read the cell parameters from the second storage area in the cache module.

[0049] As a possible implementation method, the first determination unit is specifically used to: for any second reading process, extract a first sub-parameter related to scheduling and a second sub-parameter related to the cell from the data read in any second reading process; according to the first output format of the PCIE interface in the processing chip, format convert the first sub-parameter to obtain the first sub-parameter of the first output format; wherein the first output format is determined according to the data format of the actual scheduling parameters sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameters are sent by layer 2 in the BBU to the processing chip; according to the second output format of the PCIE interface in the processing chip, format convert the second sub-parameter to obtain the second sub-parameter of the second output format; wherein the second output format is determined according to the data format of the actual cell parameters sent by the PCIE interface to the bit-level processing module, and the actual cell parameters are sent by layer 2 to the processing chip; cache the first sub-parameter of the first output format to the first storage area, and cache the second sub-parameter of the second output format to the second storage area.

[0050] As a possible implementation, the device further includes:

[0051] A disconnection unit, used to disconnect the communication link between the PCIE interface and the bit-level processing module when a downlink failure of the target cell is detected;

[0052] An establishing unit is used to establish a communication link between the storage unit and the bit-level processing module.

[0053] As a possible implementation, the processing chip is a field programmable gate array FPGA, and the storage module is a double data rate synchronous dynamic random access memory DDR SDRAM.

[0054] According to another aspect of the present application, a processor-readable storage medium is provided, characterized in that the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the downlink fault detection method of the above embodiment.

[0055] According to another aspect of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the downlink fault detection method of the above embodiment of the present application is implemented.

[0056] The downlink fault detection method, device, access network equipment and medium provided in the embodiments of the present application can realize the module division of the processing chip of the BBU. When a downlink fault occurs between the BBU and the AAU, each module in the processing chip is tested based on the test parameters, so that the cause of the downlink fault can be accurately located according to the actual output of each module, and the downlink fault can be repaired according to the cause of the fault, so as to improve the stability of the downlink and improve the reliability and effectiveness of data transmission.

[0057] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present application.

[0059] Figure 1 It is a schematic diagram of the architecture of using optical ports to capture time domain data in related technologies;

[0060] Figure 2 A schematic diagram of a flow chart of a downlink fault detection method provided in an embodiment of the present application;

[0061] Figure 3 A flowchart of another downlink fault detection method provided in an embodiment of the present application;

[0062] Figure 4 A flowchart of another downlink fault detection method provided in an embodiment of the present application;

[0063] Figure 5 A flowchart of another downlink fault detection method provided in an embodiment of the present application;

[0064] Figure 6 A schematic diagram of the implementation principle of the closed-loop debugging link provided in the embodiment of the present application for pile driving and troubleshooting;

[0065] Figure 7 A detailed schematic diagram of the processing flow of the bit-level processing module provided in an embodiment of the present application;

[0066] Figure 8 A detailed schematic diagram of the processing flow of the symbol-level processing module provided in an embodiment of the present application;

[0067] Fig. 9 A schematic diagram of the software implementation flow of the closed-loop piling data troubleshooting provided in the embodiment of the present application;

[0068] Fig.10 A schematic diagram of the structure of the piling module provided in the embodiment of the present application;

[0069] Fig.11 A schematic diagram of the implementation flow of piling control for three cells provided in an embodiment of the present application;

[0070] Fig.12 A schematic diagram of the implementation flow of a single subframe reading DDR provided in an embodiment of the present application;

[0071] Fig.13 A schematic diagram of the structure of an access network device provided in an embodiment of the present application;

[0072] Fig.14 A schematic diagram of the structure of a downlink fault detection device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] In the embodiments of the present application, the term "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0074] In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.

[0075] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0076] In wireless communication systems, when developing new functions or in commercial field operation and maintenance scenarios, the following two problems may occur:

[0077] First, how to efficiently and completely verify the correctness of the downlink between the BBU and AAU during the development of new functions;

[0078] Second, in the field operation and maintenance scenario, various faults often occur in the downlink between the BBU and the AAU. When a downlink fault occurs, how to efficiently locate the cause of the fault to determine whether the fault is attributed to the BBU or the AAU, and when the fault is attributed to the BBU, how to determine whether the fault is caused by the processing chip in the BBU (such as FPGA (Field Programmable Gate Array)). If the fault is not caused by the processing chip, how to efficiently and quickly confirm that the problem is not caused by the module inside the processing chip.

[0079] Currently, it is possible to increase the scheduling parameters of L2 (Layer 2) in the BBU to the processing chip, and perform a fault test on the downlink based on the scheduling parameters.

[0080] Although this solution can largely distinguish between problems between the processing chip and L2, it cannot rule out problems between the processing chip and AAU. Furthermore, if the solution determines that the fault is caused by the processing chip, there is no way to determine which node inside the processing chip introduced the problem.

[0081] In the related art, the downlink between the BBU and the AAU is mainly tested through the following two solutions:

[0082] The first one is the traditional debugging solution: from the entrance of the PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface of the processing chip to the exit of the downlink service link level (that is, the entrance of the optical port of the processing chip), the ILA (integrated logic analyzer) is inserted into the processing chip according to the nodes, and the data signals, address signals, write enable and other related signals that need to be debugged and observed are placed in the ILA core. Then, an emulator is used outside the board to connect to the JTAG (Joint Test Action Group) debugging interface of the processing chip. The other end of the emulator is connected to the computer to locate the cause of the fault through real-time online capture.

[0083] However, this solution is limited by the hardware environment and can only be carried out in the laboratory, and cannot be used in the field. In addition, the method of adding ila core requires the storage resources of the processing chip, and it is necessary to add different ila to recompile the new version many times, which makes the fault diagnosis efficiency low. At the same time, the visible data length is short, and comprehensive information cannot be grasped.

[0084] The second solution is to use the optical port data capture function to locate the cause of the fault based on the 80ms (millisecond) time domain data captured from the optical port of the processing chip.

[0085] However, the time domain data in this solution needs to be used in conjunction with parameters. Since it is currently impossible to extract the corresponding parameter information while acquiring the time domain data, it is only possible to see from the optical port whether the time domain data is non-zero, which has no substantial guiding significance.

[0086] As an example, taking FPGA as the processing chip, the architecture diagram of using optical port to capture time domain data can be as follows: Figure 1 As shown, CA is the abbreviation of Carry Antenna, and DDR is the abbreviation of DDR (Double Data Rate) SRAM (Synchronous Dynamic Random Access Memory).

[0087] In summary, the first solution has at least the following disadvantages: increasing the ila version, increasing resources, and a long version cycle (6-7 hours at a time). The length of viewable data is relatively short, and the amount of information is incomplete, resulting in low fault diagnosis efficiency; it can only meet laboratory use and cannot be used in the field.

[0088] The second solution mentioned above has at least the following disadvantages: there is no parameter analysis, and the time domain data can only be used to determine whether it is non-zero, which lacks guiding significance.

[0089] Therefore, in order to solve at least one of the above-mentioned problems, an embodiment of the present application provides a downlink fault detection method, device, access network equipment and medium, wherein the method and device are based on the same application concept. Since the principles of solving the problems by the method and device are similar, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0090] The following describes the downlink fault detection method, apparatus, access network equipment and medium provided by the present application with reference to the accompanying drawings.

[0091] Figure 2 A flowchart of a downlink fault detection method provided in an embodiment of the present application.

[0092] The downlink fault detection method of the embodiment of the present application can be executed by an access network device.

[0093] The access network device may be a base station, wherein the base station may include multiple cells providing services for the terminal device. Depending on the specific application scenario, the base station may also be called an access point, or may be a device in the access network that communicates with the wireless terminal device through one or more sectors on the air interface, or may be other names. The base station may be used to interchange received air frames with Internet Protocol (IP) packets, and serve as a router between the wireless terminal device and the rest of the access network, wherein the rest of the access network may include an Internet Protocol (IP) communication network. The base station may also coordinate the attribute management of the air interface. For example, the base station involved in the embodiments of the present application may be a base station (Base Transceiver Station, BTS) in the Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA), or a base station (NodeB) in Wide-band Code Division Multiple Access (WCDMA), or an evolutionary Node B (eNB or e-NodeB) in the long term evolution (LTE) system, or a 5G base station (gNB) in the 5G network architecture (next generation system), or a home evolved Node B (HeNB), a relay node, a home base station (femto), a pico base station, etc., which is not limited in the embodiments of the present application. In some network structures, the base station may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and the distributed unit may also be arranged geographically separately.

[0094] The terminal device may be a device that provides voice and / or data connectivity to a user, a handheld device with a wireless connection function, or other processing devices connected to a wireless modem. In different systems, the names of the terminal devices may also be different. For example, in a 5G system, the terminal device may be called a user equipment (UE). The wireless terminal device may communicate with one or more core networks (CN) via a radio access network (RAN). The wireless terminal device may be a mobile terminal device, such as a mobile phone (or "cellular" phone) and a computer with a mobile terminal device. For example, it may be a portable, pocket-sized, handheld, computer-built-in or vehicle-mounted mobile device that exchanges language and / or data with a wireless access network. For example, personal communication service (PCS) phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDA) and other devices. The wireless terminal device may also be referred to as a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, an access point, a remote terminal device, an access terminal device, a user terminal device, a user agent, and a user device, but is not limited in the embodiments of the present application.

[0095] like Figure 2 As shown, the downlink fault detection method may include the following steps:

[0096] Step S201, when a downlink failure of a target cell is detected, the test parameters of the target cell in the current radio frame are read from the storage module in the processing chip of the BBU; wherein the downlink includes the communication link between the BBU and the AAU corresponding to the target cell.

[0097] The current radio frame may include multiple subframes. For example, the current radio frame (10 ms (milliseconds)) may include 10 subframes (1 ms).

[0098] In an embodiment of the present application, when a downlink failure is detected between the BBU and AAU of the target cell, the test parameters (or pile driving parameters) of the target cell in the current wireless frame can be read from the storage module in the processing chip of the BBU.

[0099] Step S202: Determine scheduling parameters and cell parameters according to test parameters.

[0100] In the embodiment of the present application, scheduling parameters (used to schedule each terminal device in the target cell) and cell parameters can be determined based on the test parameters.

[0101] Step S203, the scheduling parameters and the cell parameters are serially input into the bit-level processing module, the symbol-level processing module, the compression module and the CA switching module in the processing chip.

[0102] In an embodiment of the present application, the scheduling parameters and cell parameters can be input into the bit-level processing module in the processing chip, and then the actual output of the bit-level processing module can be input into the symbol-level processing module in the processing chip, and then the actual output of the symbol-level processing module can be input into the compression module in the processing chip, and then the actual output of the compression module can be input into the CA switching module.

[0103] Step S204: determining the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0104] In the embodiment of the present application, the cause of the downlink failure can be determined according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0105] It should be noted that each wireless frame can perform fault detection on the downlink of the target cell. In the present application, the test parameters of the target cell under each wireless frame (or one wireless frame) can be read from the storage module, and based on the test parameters, each module in the processing chip can be tested to determine the cause of the downlink fault.

[0106] The downlink fault detection method of the embodiment of the present application is to read the test parameters of the target cell in the current wireless frame from the storage module in the processing chip of the BBU when the downlink fault of the target cell is detected; determine the scheduling parameters and cell parameters according to the test parameters; input the scheduling parameters and cell parameters serially into the bit-level processing module, symbol-level processing module, compression module and CA switching module in the processing chip; determine the cause of the downlink fault according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module. Thus, the processing chip of the BBU is divided into modules, and when the downlink between the BBU and the AAU fails, each module in the processing chip is tested based on the test parameters, so that the cause of the downlink fault can be accurately located according to the actual output of each module, and then the downlink fault can be repaired according to the cause of the fault, so as to improve the stability of the downlink and improve the reliability and effectiveness of data transmission.

[0107] In order to clearly explain how to determine the cause of a downlink failure in any embodiment of the present application, the present application also proposes a downlink failure detection method.

[0108] Figure 3 A flowchart of another downlink fault detection method provided in an embodiment of the present application.

[0109] like Figure 3 As shown, the downlink fault detection method may include the following steps:

[0110] Step S301, when it is detected that a downlink failure occurs in a target cell, a test parameter of the target cell in a current radio frame is read from a storage module in a processing chip of a BBU.

[0111] The downlink includes a communication link between the BBU and the AAU corresponding to the target cell.

[0112] For the explanation of step S301, please refer to the relevant description in any embodiment of the present application, and will not be repeated here.

[0113] In any embodiment of the present application, the processing chip may be an FPGA, and the storage module may be a DDRSDRAM.

[0114] Step S302: Determine scheduling parameters and cell parameters according to test parameters.

[0115] Step S303, the scheduling parameters and the cell parameters are serially input into the bit-level processing module, the symbol-level processing module, the compression module and the CA switching module in the processing chip.

[0116] The explanation of steps S302 to S303 can be found in the relevant description in any embodiment of the present application and will not be repeated here.

[0117] Step S304, obtaining the first actual output of the CA switching module, and determining whether the processing chip fails according to the first actual output, if so, executing steps S305 to S306, if not, executing step S307.

[0118] In an embodiment of the present application, the actual output of the CA switching module (referred to as the first actual output in the present application) can be obtained or extracted, and based on the first actual output, it is determined whether the processing chip fails. If so, steps S305 to S306 are executed; if not, step S307 is executed.

[0119] It should be noted that steps S305 to S306 and step S307 are two parallel implementation methods. In actual application, only one needs to be executed.

[0120] In any embodiment of the present application, a method for determining whether a processing chip fails is, for example:

[0121] 1. Query the standard output corresponding to the CA switching module in the current infinite frame (referred to as the first standard output in this application), wherein the first standard output is obtained by simulating the CA switching module according to the test parameters of the target cell in the current wireless frame.

[0122] 2. Determine whether the first standard output matches the first actual output. If the first standard output matches or is consistent with the first actual output, it can be determined that the processing chip is not faulty.

[0123] 3. If the first standard output does not match or is inconsistent with the first actual output, it can be determined that the processing chip fails.

[0124] As an example, for step S302, the scheduling parameters and cell parameters of multiple subframes in the current wireless frame can be determined respectively according to the test parameters. For step S303, the scheduling parameters and cell parameters of each subframe can be serially input into the bit-level processing module, symbol-level processing module, compression module and CA switching module in the processing chip to obtain the actual output of each module in each subframe.

[0125] At this time, with respect to step S304, the first standard output of the CA switching module may include the standard output of the CA switching module in multiple subframes, and correspondingly, the first actual output may include the actual output of the CA switching module in multiple subframes. In the present application, it may be determined whether the standard output of the CA switching module in each subframe matches the actual output. When the standard output and the actual output of all subframes match, it may be determined that the processing chip has not failed. When the standard output and the actual output of at least one subframe do not match, it may be determined that the processing chip has failed.

[0126] Therefore, whether a processing chip fails can be detected based on the actual output and standard output of the CA switching module in each subframe, thereby improving the accuracy and reliability of the detection result.

[0127] Step S305: obtaining the second actual output of the target processing module.

[0128] In the embodiment of the present application, when it is determined that the processing chip fails, the second actual output of the target processing module can be further obtained or extracted. The target processing module includes a bit-level processing module and / or a symbol-level processing module.

[0129] Step S306: Determine the cause of the failure of the processing chip in the downlink according to the second actual output.

[0130] In the embodiment of the present application, the cause of the failure of the processing chip in the downlink may be determined according to the second actual output of the target processing module.

[0131] Step S307: determine that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

[0132] In the embodiment of the present application, when it is determined that the processing chip has not failed, it can be determined that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

[0133] The downlink fault detection method of the embodiment of the present application can detect which specific module in the processing chip has failed when it is determined that the processing chip in the BBU has failed. When it is determined that the processing chip in the BBU has not failed, it is determined that layer 2 or AAU in the BBU has failed, so that the cause of the downlink fault can be accurately located, and the downlink fault can be repaired according to the cause of the fault to improve the stability of the downlink.

[0134] In order to clearly explain how to determine the cause of a downlink failure in any embodiment of the present application, the present application also proposes a downlink failure detection method.

[0135] Figure 4A flowchart of another downlink fault detection method provided in an embodiment of the present application.

[0136] like Figure 4 As shown, the downlink fault detection method may include the following steps:

[0137] Step S401, when it is detected that a downlink failure occurs in a target cell, a test parameter of the target cell in a current radio frame is read from a storage module in a processing chip of a BBU.

[0138] The downlink includes a communication link between the BBU and the AAU corresponding to the target cell.

[0139] Step S402: Determine scheduling parameters and cell parameters according to test parameters.

[0140] Step S403, the scheduling parameters and the cell parameters are serially input into the bit-level processing module, the symbol-level processing module, the compression module and the CA switching module in the processing chip.

[0141] Step S404: Obtain a first actual output of the CA switching module, and determine whether a processing chip fails according to the first actual output.

[0142] The explanation of steps S401 to S404 can be found in the relevant description in any embodiment of the present application and will not be repeated here.

[0143] Step S405: if the processing chip fails, obtain the second actual output of the symbol-level processing module in the processing chip.

[0144] In an embodiment of the present application, when it is determined that a processing chip fails, the actual output of the symbol-level processing module in the processing chip (referred to as the second actual output in the present application) can be further acquired or extracted.

[0145] Step S406, querying the second standard output corresponding to the symbol-level processing module in the current wireless frame.

[0146] The second standard output is obtained by performing simulation test on the symbol-level processing module according to the test parameters.

[0147] In an embodiment of the present application, the standard output corresponding to the symbol-level processing module in the current wireless frame (referred to as the second standard output in this application) can be queried, wherein the second standard output is obtained by simulating and testing the symbol-level processing module based on the test parameters of the target cell in the current wireless frame.

[0148] Step S407, determining whether the second actual output of the symbol-level processing module matches the second standard output, if so, executing step S408, if not, executing step S409.

[0149] In the embodiment of the present application, it can be determined whether the second actual output of the symbol-level processing module matches or is consistent with the second standard output. If so, step S408 is executed; if not, step S409 is executed.

[0150] It should be noted that step S408 and step S409 are two parallel implementation methods. In actual application, only one needs to be executed.

[0151] As an example, for step S402, the scheduling parameters and cell parameters of multiple subframes in the current wireless frame can be determined respectively according to the test parameters. For step S403, the scheduling parameters and cell parameters of each subframe can be serially input into the bit-level processing module, symbol-level processing module, compression module and CA switching module in the processing chip to obtain the actual output of each module in each subframe.

[0152] At this time, for step S407, the second standard output of the symbol-level processing module may include the standard output of the symbol-level processing module under multiple subframes, and accordingly, the second actual output of the symbol-level processing module may include the actual output of the symbol-level processing module under multiple subframes. In the present application, it can be determined whether the standard output and the actual output of the symbol-level processing module under each subframe match or are consistent. When the standard output and the actual output of all subframes match, it can be determined that the second actual output matches the second standard output. When there is a mismatch between the standard output and the actual output of at least one subframe, it can be determined that the second actual output does not match the second standard output.

[0153] Step S408: determining that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0154] In the embodiment of the present application, when the second actual output of the symbol-level processing module matches the second standard output, it can be determined that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0155] Step S409, obtaining the second actual output of the bit-level processing module, and querying the third standard output corresponding to the bit-level processing module in the current wireless frame.

[0156] The third standard output is obtained by performing a simulation test on the bit-level processing module according to the test parameters.

[0157] In an embodiment of the present application, when the second actual output of the symbol-level processing module does not match the second standard output, the actual output of the bit-level processing module (referred to as the second actual output in the present application) can be further obtained or extracted, and the standard output corresponding to the bit-level processing module in the current wireless frame (referred to as the third standard output in the present application) can also be queried, wherein the third standard output is obtained by simulating and testing the bit-level processing module based on the test parameters of the target cell in the current wireless frame.

[0158] Step S410, determining whether the second actual output of the bit-level processing module matches the third standard output, if so, executing step S411, if not, executing step S412.

[0159] In the embodiment of the present application, it can be determined whether the second actual output of the bit-level processing module matches or is consistent with the third standard output. If so, step S411 is executed; if not, step S412 is executed.

[0160] It should be noted that step S411 and step S412 are two parallel implementation methods. In actual application, only one needs to be executed.

[0161] As an example, for step S402, the scheduling parameters and cell parameters of multiple subframes in the current wireless frame can be determined respectively according to the test parameters. For step S403, the scheduling parameters and cell parameters of each subframe can be serially input into the bit-level processing module, symbol-level processing module, compression module and CA switching module in the processing chip to obtain the actual output of each module in each subframe.

[0162] At this time, for step S410, the third standard output may include the standard output of the bit-level processing module under multiple subframes, and accordingly, the second actual output of the bit-level processing module may include the actual output of the bit-level processing module under multiple subframes. In the present application, it can be determined whether the standard output and the actual output of the bit-level processing module in each subframe match or are consistent. When the standard output and the actual output of all subframes match, it can be determined that the second actual output of the bit-level processing module matches the third standard output. When there is a mismatch between the standard output and the actual output of at least one subframe, it can be determined that the second actual output of the bit-level processing module does not match the third standard output.

[0163] Step S411, determining that the cause of the failure of the processing chip in the downlink is a failure of the symbol-level processing module.

[0164] In the embodiment of the present application, when the second actual output of the bit-level processing module matches the third standard output, it can be determined that the cause of the failure of the processing chip in the downlink is a failure of the symbol-level processing module.

[0165] Step S412: determine that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0166] In the embodiment of the present application, when the second actual output of the bit-level processing module does not match the third standard output, it can be determined that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0167] The downlink fault detection method of the embodiment of the present application can detect which specific module in the processing chip has failed when determining that the processing chip in the BBU has failed, thereby improving the efficiency and effectiveness of fault detection, so that the faulty module can be repaired in a targeted manner to improve the stability of the downlink.

[0168] In order to clearly illustrate any of the above embodiments, the present application also proposes a downlink fault detection method.

[0169] Figure 5 A flowchart of another downlink fault detection method provided in an embodiment of the present application.

[0170] like Figure 5 As shown, the downlink fault detection method may include the following steps:

[0171] Step S501: When a downlink failure of a target cell is detected, a first reading process is performed M times on a storage module in a processing chip of a BBU.

[0172] The downlink includes a communication link between the BBU and the AAU corresponding to the target cell.

[0173] Here, M is the number of subframes included in the current wireless frame, and M is a positive integer, for example, M can be 10.

[0174] The storage module is used to store a parameter file (or stub file) of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current radio frame.

[0175] In the embodiment of the present application, when a downlink failure is detected in the target cell, the first reading process may be performed M times on the storage module in the processing chip of the BBU.

[0176] In any embodiment of the present application, the execution method of each first reading process may be, for example:

[0177] 1. Determine a candidate storage address from various storage addresses of the storage module, wherein the candidate storage address is used to store the parameter file of the target cell.

[0178] In the present application, the storage address of the parameter file of each cell in the storage module is fixed. According to the cell identifier (such as the cell index) of the target cell, the storage addresses for storing the parameter file of the target cell can be determined from the various storage addresses of the storage module and used as candidate storage addresses.

[0179] 2. For the i-th (i is a positive integer not greater than M) first reading process, the target storage address can be determined from each candidate storage address, where the target storage address is used to store the test parameters of the i-th subframe (referred to as sub-test parameters in this application).

[0180] In the present application, the storage address of the test parameters (i.e., sub-test parameters) of each cell in each subframe in the storage module is fixed, and the sub-test parameters for storing the i-th subframe can be determined from various candidate storage addresses based on the cell identifier (such as the cell index) of the target cell and the subframe number of the i-th subframe.

[0181] 3. Perform N second reading processes on the storage module according to the target data volume and the total amount of data stored in the target storage address; wherein the target data volume is used to indicate the amount of data read in a single time; and N is determined based on the ratio of the total amount to the target data volume.

[0182] In the present application, the amount of data read each time (referred to as the target data amount in the present application) can be determined based on the bit width of the storage module, and the second reading process can be performed N times on the storage module based on the target data amount and the total number stored in the target storage address, where N is determined based on the ratio of the total number to the target data amount.

[0183] That is, each second reading process is used to read a target amount of data from a target storage address.

[0184] As an example, for the first second reading process: the first storage address among the target storage addresses can be used as the base address (i.e., the starting address) for the first second reading process to start reading, and starting from the base address read in the first second reading process, the target data volume is read and used as the data read in the first second reading process. In addition, the base address for the second second reading process to start reading can also be determined based on the end address of the first second reading process.

[0185] For the jth (j=2, 3, ..., N-1) second reading process: the target data volume can be read starting from the base address read by the jth second reading process, and used as the data read by the jth second reading process. In addition, the base address for starting reading by the j+1th second reading process can be determined according to the end address of the jth second reading process.

[0186] For the last (ie, Nth) second reading process: starting from the base address read in the Nth second reading process, data of the target data volume may be read and used as the data read in the Nth second reading process.

[0187] 4. The data read in the Nth second reading process is used as the data read in the i-th first reading process.

[0188] In the embodiment of the present application, the data read by the N second reading processes may be used as the data read by the i-th first reading process.

[0189] Step S502: using the data read in the i-th first reading process as the sub-test parameter of the i-th sub-frame.

[0190] In the embodiment of the present application, the data read in the i-th first reading process may be used as the sub-test parameter of the i-th sub-frame.

[0191] Step S503: determine the test parameters according to the sub-test parameters of the M sub-frames.

[0192] In this embodiment of the present application, the sub-test parameters of M subframes may be used as the test parameters of the current wireless frame.

[0193] Step S504: Determine scheduling parameters and cell parameters according to the test parameters.

[0194] The execution process of step S504 can refer to the relevant description in any embodiment of the present application and will not be repeated here.

[0195] In any embodiment of the present application, the scheduling parameters and cell parameters in the current radio frame are determined, for example, as follows:

[0196] 1. The data read in each second reading process is sequentially stored in a cache module in the processing chip.

[0197] As an example, for any second reading process, a first sub-parameter related to scheduling can be extracted from the data read in the second reading process, and the first sub-parameter can be format converted according to the first output format of the PCIE interface in the processing chip to obtain the first sub-parameter of the first output format. After that, the first sub-parameter of the first output format can be cached in the first storage area of ​​the cache module.

[0198] The first output format is determined according to the data format of the actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is the scheduling parameter sent by layer 2 in the BBU to the processing chip.

[0199] Moreover, for any second reading process, a second sub-parameter related to the cell can be extracted from the data read in the second reading process, and the second sub-parameter can be format-converted according to the second output format of the PCIE interface in the processing chip to obtain the second sub-parameter of the second output format, and then the second sub-parameter of the second output format can be cached in the second storage area of ​​the cache module.

[0200] The second output format is determined according to the data format of the actual cell parameters sent by the PCIE interface to the bit-level processing module, and the actual cell parameters are the cell parameters sent by layer 2 to the processing chip.

[0201] 2. Read the scheduling parameters from the first storage area in the cache module.

[0202] 3. Read the cell parameters from the second storage area in the cache module.

[0203] Step S505, the scheduling parameters and the cell parameters are serially input into the bit-level processing module, the symbol-level processing module, the compression module and the CA switching module in the processing chip.

[0204] The execution process of step S505 can refer to the relevant description in any embodiment of the present application and will not be repeated here.

[0205] In any embodiment of the present application, the sub-scheduling parameters of the M subframes can be determined from the scheduling parameters of the current wireless frame, and the sub-cell parameters of the M subframes can be determined from the cell parameters of the current wireless frame. In the present application, the sub-scheduling parameters and sub-cell parameters of each subframe can be serially input into the bit-level processing module, symbol-level processing module, compression module and CA switching module in the processing chip to obtain the actual output of each module in each subframe.

[0206] Step S506: Determine the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0207] The execution process of step S506 can refer to the relevant description in any embodiment of the present application and will not be repeated here.

[0208] In any embodiment of the present application, in order to avoid the situation where layer 2 in the BBU sends cell parameters and scheduling parameters to the processing chip, thereby interfering with the actual detection results, in the present application, when a downlink failure of the target cell is monitored, the communication link between the PCIE interface and the bit-level processing module can be disconnected, and a communication link between the storage unit and the bit-level processing module can be established.

[0209] The downlink fault detection method of the embodiment of the present application can implement multiple reading processes on the storage module in the processing chip of the BBU to effectively obtain the test parameters of the current wireless frame, thereby improving the effectiveness of fault detection.

[0210] In any embodiment of the present application, when a downlink failure occurs between the BBU and the AAU, it can be determined whether the cause of the failure is caused by the processing chip of the BBU. If it is not caused by the processing chip, it can be further determined whether the cause of the failure is caused by the previous level L2 of the processing chip or by the next level AAU. If it is caused by the processing chip, the module can be split on the link node set inside the processing chip to shorten the problem to a specific module. Finally, the cause of the failure or the problem can be located through the simulation vector (recorded as the standard output of the module in this application), so as to achieve the purpose of quickly determining the ownership of the problem and quickly iterating the solution to the problem, thereby improving the efficiency of diagnosing failures or problems.

[0211] Specifically, a piling function can be added to the downlink service level entrance, the PCIE interface in the processing chip that communicates with L2 is disconnected, a vector source is input from the entrance of the downlink service level, the scheduling parameters and the original bit sent by L2 are completely simulated and replaced in terms of the interface and timing content, and parameter distribution, parameter calculation, coding, premodulation, layer mapping, resource mapping, IFFT (Inverse Fast Fourier Transform), CP (Cyclic Prefix), antenna interleaving, compression, CA switching and other downlink service processing links are implemented inside the processing chip. Then, at the exit of the downlink service processing link (i.e., the entrance of the optical port of the processing chip), an operation of extracting 80ms of time domain data is performed.

[0212] Among them, piling corresponds to reading the data of the storage module (such as DDR) in the processing chip (such as FPGA), and extracting data corresponds to storing the data in the storage module. Taking the storage module as DDR4 (a new generation of memory specifications) as an example, the high-speed read and write characteristics of DDR4 can be used. The user side can read and write DDR at the same time, that is, piling while collecting the piling results. The DDR arbitrator completes the reading and writing selection. The storage and writing rates of DDR are lower than the effective read and write bandwidth of DDR. Among them, the high-speed read and write characteristics of DDR can ensure that the reading and writing of DDR will not send conflicts. Therefore, a closed-loop debugging link integrating piling and extracting data can be realized. The extracted data can be compared with the standard output (or called standard vector). According to the comparison results, the correctness of the downlink between the entire BBU and AAU can be judged.

[0213] As an example, the processing chip is FPGA and the storage module is DDR4. The implementation principle of the closed-loop debugging link for pile driving and data troubleshooting can be as follows: Figure 6 As shown, when the actual output of the CA switching module is successfully compared with the standard output, it means that the fault problem does not occur inside the FPGA. Otherwise, it means that the fault problem occurs inside the FPGA. At this time, in order to further narrow the scope of the fault problem, the export data extraction function of the bit-level processing module and the export data extraction function of the symbol-level processing module can be added in the downlink at the same time. The results of piling are collected while piling at different positions. By introducing the data extraction function of multiple nodes (or modules), when the problem occurs inside the FPGA, it can be clearly determined in which node (or module) the problem occurs.

[0214] In order to further reduce the scope of the fault and analyze the cause of the fault, Figure 6 As shown, the time domain data capture structure in the related art (i.e. Figure 1 )compared to, Figure 6 The piling module, selection module and format conversion module have been added. These three newly added core modules and the time domain data extraction function of the original optical port work together to complete the troubleshooting of the entire downlink.

[0215] like Figure 6 As shown, the entrance of the downlink service is the PCIE interface, and the exit is the optical port. These two interfaces are used as the front and back demarcation points of the downlink service-level data link. When a problem occurs in the downlink between the BBU and the AAU, the parameter pile file (referred to as the parameter file in this application) can be written into the DDR4 storage module through the PCIE interface by the driver layer software, and the selected pile parameter (referred to as the debugging parameter in this application) is switched to the "selection module" to input this data effectively. The "pile module" is responsible for reading the debugging parameters in the parameter file from the DDR4 in a loop, and converting the debugging parameters into the same data format as the real parameters issued by the normal PCIE interface to replace the real parameters issued by the PCIE interface. In the internal processing of the downlink service-level module, after the bit (bit) level processing module, the symbol level processing module, the compression module and the CA switching module, at the exit of the CA module, the actual output of the extracted CA module is sent to the soft logic submodule. The soft logic module is responsible for selecting one channel of data from multiple channels, converting the data into a data format that meets the DDR4 entry requirements, and storing it in DDR4. The driver layer software accesses DDR4 through the PCIE interface, reads the data and prints it into a result file, and uses the result file to complete the comparison with the vector result file of the stub. The vector result file of the stub includes the standard output of each module.

[0216] The details of the processing flow of the bit-level processing module can be as follows: Figure 7As shown, the details of the processing flow of the symbol level processing module can be as follows Figure 8 shown.

[0217] Specifically, the software implementation process of closed-loop pile driving troubleshooting can be as follows: Fig. 9 As shown, it mainly includes the following steps:

[0218] When a downlink failure occurs between the BBU and the AAU, first switch the channel through the "select module" (only select the channel for the pile parameter (i.e., test parameter) input, and close the channel for the real parameter input), select the channel for reading the parameter pile file (referred to as the parameter file in this application) from DDR4 as input, input the pile driving enable instruction to enable the "pile driving module", execute the pile driving function, read the parameter file from DDR4 to the entrance of the bit-level processing module for pile driving, and extract the pile driving output data from the exit of the CA switching module at the same time. The output data length can support up to 80ms, i.e., 8 wireless frame lengths. Compare the extracted output data with the standard output (or standard vector) corresponding to the CA switching module. If the vector comparison is successful, it means that the entrance to the exit of the FPGA downlink works normally, and the fault caused by the FPGA is eliminated.

[0219] If the vector comparison is unsuccessful, it means that the problem occurs inside the FPGA (it may be caused by the FPGA or a parameter configuration error). At this time, in order to find out the fault point, switch to extract the export data of the previous node (i.e., the symbol-level processing module) and compare it with the standard output (or standard vector) corresponding to the symbol-level processing module. If the vector comparison is successful, it means that the problem occurs in the compression module and / or CA switching module; if the vector comparison is unsuccessful, it means that the problem occurs in the previous node of the symbol-level processing module (i.e., the bit-level processing module).

[0220] The export data of the bit-level processing module is extracted and compared with the standard output (or standard vector) of the bit-level processing module. If the vector comparison is successful, it means that the problem occurs in the symbol-level processing module. Otherwise, the locking problem occurs in the bit-level processing module.

[0221] For the modules with locking issues, further analysis and positioning are carried out in a targeted manner to find the cause of the failure and modify the code, and then re-iterate the stubbing verification until the problem is solved.

[0222] That is, the above core module is a newly added bit-level piling module, which replaces the PCIE interface of L2 to input the vector source file to the business-level entry. Its core is to read the parameter piling file stored in DDR4 (referred to as parameter file in this application), and convert the data format of the parameter file into the data format of the business-level entry to ensure the invisibility of the business-level code program to the input source of the previous level, that is, the parameters of the invisible input are the real parameters sent by L2, or the piling parameters stored in DDR4 (referred to as test parameters in this application). The structure of the piling module can be as follows: Fig.10 As shown:

[0223] It should be noted that a single board on the access network device side can support N (exemplarily, N can be 3) cell piling, and the piling module can be responsible for the control process of 3 cell piling. For example, the FPGA may include a bit-level processing module, and a bit-level processing module can be connected to three symbol-level processing modules in FAGA, wherein a symbol-level processing module corresponds to a cell, and each symbol-level processing module is connected to a compression module and a CA switching module, and the CA switching module is connected to an optical port. For example, the FPGA may include three optical ports, each optical port is connected to an AAU, wherein each AAU corresponds to a cell, or the FPGA may include only one optical port, and one optical port can be connected to one AAU, and one AAU corresponds to 3 cells.

[0224] Among them, the state machine can be used to control whether the piling of the current cell is completed, when the piling of the next cell is enabled, and how the three cells perform cyclic flow control.

[0225] in, Fig.10 The DDR base address calculation module for reading: The storage address of the test parameters of each cell in each subframe in DDR4 is fixed. The reading of DDR4 adopts the burst operation mode. Therefore, it is necessary to calculate the amount of data read each time according to the bit width of DDR4 (referred to as the target data amount in this application), and calculate the base address for the next read based on the size of the target data amount.

[0226] DDR read data control module: Initiates a burst read request operation for DDR4 according to the interface format and process for reading DDR4.

[0227] DDR read-back data processing module: The clock rates of the DDR4 interface and the PCIE interface may be different, and the bit widths may also be different. The read DDR4 data needs to be cached, cross-clock processed, and bit width converted.

[0228] User parameter interface conversion module: selects the scheduling parameters from the fixed position in the DDR readback data and converts them into the data format of the real scheduling parameters of the PCIE interface.

[0229] Cell parameter interface conversion module: selects cell parameters from fixed positions in the DDR read-back data and converts them into the data format of the real cell parameters of the PCIE interface.

[0230] As an example, the piling control implementation process of three cells can be as follows: Fig.11 As shown, the piling method to be used is determined. A single board supports piling in three cells. In this application, piling can be performed in any one cell, or in three cells at the same time, but each cell will be executed serially.

[0231] Specifically, "triggering piling enable" detects whether there is any cell piling. If so, according to the round-robin mechanism, first determine whether the first cell (recorded as cell 1) is enabled for piling. If cell 1 is not enabled for piling, directly enter the judgment state of the second cell (recorded as cell 2); if cell 1 is enabled for piling, it will be processed according to the single subframe read operation DDR to determine whether piling of one subframe of cell 1 is completed. If completed, enter the judgment state of cell 2; in the judgment state of cell 2, first determine whether cell 2 is enabled for piling. If cell 2 is not enabled for piling, directly enter the judgment state of the third cell (recorded as cell 3). Judgment state; if the piling of cell 2 is enabled, it will be processed according to the single subframe read operation DDR to determine whether the piling of one subframe of cell 2 is completed. If completed, enter the judgment state of cell 3; in the judgment state of cell 3, first determine whether the piling of cell 3 is enabled. If the piling of cell 3 is not enabled, directly return to the judgment state of cell 1 to proceed to the judgment state of the next subframe; if the piling of cell 3 is enabled, it will be processed according to the single subframe read operation DDR to determine whether the piling of one subframe of cell 3 is completed. If completed, enter the judgment state of the first cell to proceed to the judgment state of the next subframe.

[0232] Fig.11 The function of the piling control process module of the three cells is realized. The function of reading a parameter file of a single subframe (referred to as subtest parameter in this disclosure) is realized in the "single subframe read DDR" process. The specific implementation process can be as follows: Fig.12 As shown, it mainly includes the following steps:

[0233] 1. During the implementation process, we must first determine whether the cell piling is enabled. If enabled, in "Calculate 1 read address", we need to determine the initial address (i.e. base address) for reading DDR4 based on the cell index and the current subframe number, and calculate the initial address to be read next time based on the burst length.

[0234] Among them, the parameter file of each subframe of each cell occupies a unique storage space in DDR4.

[0235] 2. After obtaining the initial address for reading DDR4, start reading DDR data in a burst operation in "Read DDR". One burst operation reads data of a fixed length.

[0236] 3. "Receive data" needs to cache the read DDR data.

[0237] 4. "Data format conversion" completes the selection of scheduling parameters, interface conversion, and the selection of cell parameters and interface conversion.

[0238] The length of the parameter file is fixed, and the length of the data read in each burst is also fixed. Therefore, the number of burst reads required for a cell in a subframe is also fixed. For example, the data in the parameter file of a single cell in one subframe requires eight burst transmissions. Each time a burst transmission read is completed, the counter is incremented.

[0239] 5. In "Has a subframe been read?", the counter value is judged. If the cumulative value reaches 8 times, it is considered that the single-cell single-subframe is completed, and the process returns to judge whether the cell is enabled to prepare for the next round of operations.

[0240] 6. If it is determined that the single subframe is not completed, enter the "calculate the read address once" process to calculate the base address for the next read.

[0241] In summary, when a cell's downlink fails, it is possible to effectively determine whether the cause of the fault is caused by the FPGA subsystem. That is, by adding a piling function, the FPGA can be piled at the entrance and data can be collected at the exit. This self-generated and self-collected closed-loop method can verify the correctness of the downlink, so as to achieve the purpose of proving one's innocence and troubleshooting the cause of the fault. In addition, multi-node data collection of the bit-level processing module and the symbol-level processing module is added. When the fault occurs inside the FPGA subsystem, it can be used to determine the location of the faulty node and converge the problem location range. In addition, for the development stage of new functions, the status of the entire downlink can be verified, and the early unit test can be completed efficiently.

[0242] Compared with the existing solutions, the downlink fault detection method provided by the present application has at least the following advantages:

[0243] 1. High efficiency. This method can quickly determine whether the problem is an FPGA problem (i.e., determine whether the fault is caused by the FPGA) through simple operations such as staking, data extraction, and data comparison, so as to achieve the purpose of quickly transferring the fault bug and improve the problem convergence speed;

[0244] 2. It is highly flexible and suitable for any field and laboratory environment. It does not require other auxiliary equipment and has a wide range of application scenarios.

[0245] 3. It is highly versatile and does not require recompiling and positioning versions specifically for specific problems, saving testing time;

[0246] 4. As a maintenance and testing method, it will not destroy the fault scenario, so that occasional problems need to be reproduced.

[0247] The technical solution provided in the embodiment of the present application can be applicable to a variety of systems, especially 5G systems. For example, the applicable system can be a global system of mobile communication (Global System of Mobile communication, referred to as GSM) system, code division multiple access (Code Division Multiple Access, referred to as CDMA) system, wideband code division multiple access (Wideband Code Division Multiple Access, referred to as WCDMA) general packet radio service (General Packet Radio Service, referred to as GPRS) system, long term evolution (long term evolution, referred to as LTE) system, LTE frequency division duplex (Frequency Division Duplex, referred to as FDD) system, LTE time division duplex (time division duplex, referred to as TDD) system, advanced long term evolution (Long Term Evolution Advanced, referred to as LTE-A) system, Universal Mobile Telecommunication System (Universal Mobile Telecommunication System, referred to as UMTS), Worldwide interoperability for Microwave Access (Worldwide interoperability for Microwave Access, referred to as WiMAX) system, 5G new air interface (NewRadio, referred to as NR) system, etc. These various systems include terminals and network equipment. The system may also include a core network part, such as an evolved packet system (EPS), a 5G system (5GS), etc.

[0248] In order to implement the above embodiments, the present application also proposes an access network device.

[0249] Fig.13 A schematic diagram of the structure of an access network device provided in an embodiment of the present application.

[0250] like Fig.13 As shown, the access network device may include: a transceiver 1300 , a processor 1310 , and a memory 1320 .

[0251] Among them, the memory 1320 is used to store computer programs; the transceiver 1300 is used to send and receive data under the control of the processor 1310; the processor 1310 is used to read the computer program in the memory 1320 and perform the following operations: when it is monitored that the downlink of the target cell fails, read the test parameters of the target cell in the current wireless frame from the storage module in the processing chip of the BBU; wherein the downlink includes a communication link between the BBU and the AAU corresponding to the target cell; determine the scheduling parameters and the cell parameters according to the test parameters; input the scheduling parameters and the cell parameters serially into the bit-level processing module, the symbol-level processing module, the compression module and the CA switching module in the processing chip; determine the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0252] The transceiver 1300 is used to receive and send data under the control of the processor 1310 .

[0253] Among them, Fig.13 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1310 and various circuits of memory represented by memory 1320 are linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 1300 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, which transmission medium may include a wireless channel, a wired channel, an optical cable, and other transmission media. The processor 1310 is responsible for managing the bus architecture and general processing, and the memory 1320 may store data used by the processor 1310 when performing operations.

[0254] The processor 1310 may be a CPU, an ASIC, an FPGA or a CPLD, and the processor 1310 may also adopt a multi-core architecture.

[0255] As a possible implementation manner, the processor 1310 determines the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module, specifically: obtaining the first actual output of the CA switching module, and determining whether the processing chip fails according to the first actual output; if the processing chip fails, obtaining the second actual output of the target processing module; wherein the target processing module includes a bit-level processing module and / or a symbol-level processing module; and determining the cause of the failure of the processing chip in the downlink according to the second actual output.

[0256] As a possible implementation manner, the processor 1310 executes to determine whether the processing chip fails according to the first actual output, specifically: query the first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by simulating the CA switching module according to the test parameters; when the first standard output does not match the first actual output, it is determined that the processing chip fails; when the first standard output matches the first actual output, it is determined that the processing chip does not fail.

[0257] As a possible implementation method, the processor 1310 executes to determine the cause of the failure of the processing chip in the downlink according to the second actual output, specifically: obtaining the second actual output of the symbol-level processing module in the processing chip; querying the second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by simulating the symbol-level processing module according to the test parameters; when the second actual output of the symbol-level processing module matches the second standard output, determining that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0258] As a possible implementation method, the processor 1310 executes to determine the cause of the failure of the processing chip in the downlink according to the second actual output, specifically: when the second actual output of the symbol-level processing module does not match the second standard output, obtain the second actual output of the bit-level processing module; query the third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by simulating the bit-level processing module according to the test parameters; when the second actual output of the bit-level processing module matches the third standard output, determine that the cause of the failure of the processing chip in the downlink is that the symbol-level processing module has a failure.

[0259] As a possible implementation method, the processor 1310 determines the cause of the failure of the processing chip in the downlink based on the second actual output, specifically: when the second actual output of the bit-level processing module does not match the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0260] As a possible implementation method, the processor 1310 determines the cause of the downlink failure based on the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module. Specifically, if the processing chip does not fail, it is determined that the cause of the downlink failure is a failure in layer 2 in the BBU or a failure in the AAU.

[0261] As a possible implementation method, the storage module is used to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current wireless frame, and the current wireless frame includes M subframes, where M is a positive integer; when the processor 1310 monitors that a downlink failure of the target cell occurs, the processor 1310 reads the test parameters of the target cell in the current wireless frame from the storage module in the processing chip in the indoor baseband processing unit BBU corresponding to the target cell, specifically: when a downlink failure is monitored in the target cell, the storage module is executed M times the first reading process; the data read by the i-th first reading process is used as the sub-test parameter of the i-th subframe; wherein i is a positive integer not greater than M; and the test parameter is determined according to the sub-test parameters of the M subframes.

[0262] As a possible implementation method, when the processor 1310 monitors that a downlink failure occurs in the target cell, the processor 1310 performs a first reading process on the storage module M times, specifically: determining a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; for the i-th first reading process, determining the target storage address from each candidate storage address; wherein the target storage address is used to store the sub-test parameters of the i-th subframe; performing a second reading process on the storage module N times according to the target data volume and the total data volume stored in the target storage address; wherein the target data volume is used to indicate the amount of data read in a single time; N is determined according to the ratio of the total amount to the target data volume; and using the data read by the N second reading processes as the data read by the i-th first reading process.

[0263] As a possible implementation method, the processor 1310 executes the first second reading process, specifically: according to the first storage address in each target storage address, determine the base address for starting to read in the first second reading process; starting from the base address read in the first second reading process, read the target data amount of data, and use it as the data read in the first second reading process; according to the end address where the first second reading process ends, determine the base address for starting to read in the second second reading process; the processor executes the non-first second reading process, specifically: starting from the base address read in this second reading process, read the target data amount of data, and use it as the data read in this second reading process; according to the end address where the second reading process ends, determine the base address for starting to read in the next second reading process.

[0264] As a possible implementation method, the processor 1310 determines the scheduling parameters and the cell parameters based on the test parameters, specifically: the data read by each second reading process is stored in the cache module in the processing chip in sequence; the scheduling parameters are read from the first storage area in the cache module; and the cell parameters are read from the second storage area in the cache module.

[0265] As a possible implementation method, the processor 1310 executes to store the data read by each second reading process into a cache module in the processing chip in sequence, specifically: for any second reading process, extract the first sub-parameter related to scheduling and the second sub-parameter related to the cell from the data read by any second reading process; according to the first output format of the PCIE interface in the processing chip, the first sub-parameter is format-converted to obtain the first sub-parameter of the first output format; wherein the first output format is determined according to the data format of the actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; according to the second output format of the PCIE interface in the processing chip, the second sub-parameter is format-converted to obtain the second sub-parameter of the second output format; wherein the second output format is determined according to the data format of the actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; the first sub-parameter of the first output format is cached to the first storage area, and the second sub-parameter of the second output format is cached to the second storage area.

[0266] As a possible implementation, the processor 1310 is further used to perform the following operations: when a downlink failure of the target cell is detected, disconnect the communication link between the PCIE interface and the bit-level processing module; and establish a communication link between the storage unit and the bit-level processing module.

[0267] As a possible implementation, the processing chip is FPGA and the storage module is DDR SDRAM.

[0268] It should be noted that the access network device provided in the embodiment of the present application can achieve the above Figures 2 to 5 All the method steps implemented in the method embodiment can achieve the same technical effect, and the parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0269] With the above Figures 2 to 5 Corresponding to the downlink fault detection method provided in the embodiment, the present application also provides a downlink fault detection device. Since the downlink fault detection device provided in the embodiment of the present application is similar to the above-mentioned Figures 2 to 5 The downlink fault detection method provided in the embodiment corresponds to the downlink fault detection method, so the implementation method of the downlink fault detection method is also applicable to the downlink fault detection device provided in the embodiment of the present application, and will not be described in detail in the embodiment of the present application.

[0270] Fig.14 A schematic diagram of the structure of a downlink fault detection device provided in an embodiment of the present application.

[0271] like Fig.14 As shown, the downlink fault detection device 1400 is applied to an access network device and may include: a reading unit 1410 , a first determining unit 1420 , an input unit 1430 and a second determining unit 1440 .

[0272] Among them, the reading unit 1410 is used to read the test parameters of the target cell in the current wireless frame from the storage module in the processing chip of the indoor baseband processing unit BBU when a downlink failure of the target cell is monitored; wherein the downlink includes the communication link between the BBU and the active antenna unit AAU corresponding to the target cell.

[0273] The first determining unit 1420 is configured to determine scheduling parameters and cell parameters according to the test parameters.

[0274] The input unit 1430 is used to serially input the scheduling parameters and cell parameters into the bit-level processing module, symbol-level processing module, compression module and carrier antenna CA switching module in the processing chip.

[0275] The second determining unit 1440 is configured to determine a downlink failure cause according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module.

[0276] As a possible implementation method, the second determination unit 1440 is specifically used to: obtain a first actual output of the CA switching module, and determine whether the processing chip fails based on the first actual output; if the processing chip fails, obtain a second actual output of the target processing module; wherein the target processing module includes a bit-level processing module and / or a symbol-level processing module; and determine the cause of the failure of the processing chip in the downlink based on the second actual output.

[0277] As a possible implementation method, the second determination unit 1440 is specifically used to: query the first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by simulating the CA switching module according to the test parameters; when the first standard output does not match the first actual output, it is determined that the processing chip has failed; when the first standard output matches the first actual output, it is determined that the processing chip has not failed.

[0278] As a possible implementation method, the second determination unit 1440 is specifically used to: obtain the second actual output of the symbol-level processing module in the processing chip; query the second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by simulating the symbol-level processing module according to the test parameters; when the second actual output of the symbol-level processing module matches the second standard output, determine that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

[0279] As a possible implementation method, the second determination unit 1440 is also used to: when the second actual output of the symbol-level processing module does not match the second standard output, obtain the second actual output of the bit-level processing module; query the third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by simulating the bit-level processing module according to the test parameters; when the second actual output of the bit-level processing module matches the third standard output, determine that the cause of the failure of the processing chip in the downlink is a failure of the symbol-level processing module.

[0280] As a possible implementation manner, the second determination unit 1440 is further used to: when the second actual output of the bit-level processing module does not match the third standard output, determine that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

[0281] As a possible implementation manner, the second determining unit 1440 is further configured to: if the processing chip does not fail, determine that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

[0282] As a possible implementation method, the storage module is used to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current wireless frame, and the current wireless frame includes M subframes, where M is a positive integer; the reading unit 1410 is specifically used to: when a downlink failure is detected in the target cell, perform M first reading processes on the storage module; use the data read by the i-th first reading process as the sub-test parameters of the i-th subframe; wherein i is a positive integer not greater than M; and determine the test parameters based on the sub-test parameters of the M subframes.

[0283] As a possible implementation method, the reading unit 1410 is specifically used to: determine a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; for the i-th first reading process, determine the target storage address from each candidate storage address; wherein the target storage address is used to store the sub-test parameter of the i-th subframe; according to the target data amount and the total data amount stored in the target storage address, perform N second reading processes on the storage module; wherein the target data amount is used to indicate the amount of data read in a single time; N is determined according to the ratio of the total amount to the target data amount; and use the data read by the N second reading processes as the data read by the i-th first reading process.

[0284] As a possible implementation method, the first second reading process includes: determining the base address for starting to read in the first second reading process according to the first storage address among each target storage address; starting from the base address read in the first second reading process, reading the target data amount of data, and using it as the data read in the first second reading process; determining the base address for starting to read in the second second reading process according to the end address at which the first second reading process ends reading; the non-first second reading process includes: starting from the base address read in this second reading process, reading the target data amount of data, and using it as the data read in this second reading process; determining the base address for starting to read in the next second reading process according to the end address at which the second reading process ends reading.

[0285] As a possible implementation method, the first determination unit 1420 is specifically used to: store the data read by each second reading process into the cache module in the processing chip in sequence; read the scheduling parameters from the first storage area in the cache module; and read the cell parameters from the second storage area in the cache module.

[0286] As a possible implementation method, the first determination unit 1420 is specifically used to: for any second reading process, extract a first sub-parameter related to scheduling and a second sub-parameter related to the cell from the data read in any second reading process; according to the first output format of the PCIE interface in the processing chip, format convert the first sub-parameter to obtain the first sub-parameter of the first output format; wherein the first output format is determined according to the data format of the actual scheduling parameters sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameters are sent by layer 2 in the BBU to the processing chip; according to the second output format of the PCIE interface in the processing chip, format convert the second sub-parameter to obtain the second sub-parameter of the second output format; wherein the second output format is determined according to the data format of the actual cell parameters sent by the PCIE interface to the bit-level processing module, and the actual cell parameters are sent by layer 2 to the processing chip; cache the first sub-parameter of the first output format to the first storage area, and cache the second sub-parameter of the second output format to the second storage area.

[0287] As a possible implementation manner, the downlink fault detection device 1400 may further include:

[0288] A disconnection unit, used to disconnect the communication link between the PCIE interface and the bit-level processing module when a downlink failure of the target cell is detected;

[0289] An establishing unit is used to establish a communication link between the storage unit and the bit-level processing module.

[0290] As a possible implementation, the processing chip is FPGA and the storage module is DDR SDRAM.

[0291] It should be noted that the downlink fault detection device provided in the embodiment of the present application can achieve the above Figures 2 to 5 All the method steps implemented in the method embodiment can achieve the same technical effect, and the parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0292] It should be noted that each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0293] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program code.

[0294] In order to implement the above embodiments, the present application also proposes a processor-readable storage medium.

[0295] The processor-readable storage medium stores a computer program for causing the processor to execute the present application. Figures 2 to 5 A downlink fault detection method according to any embodiment.

[0296] Among them, the processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CD, DVD, BD, HVD, etc.), and semiconductor storage (such as ROM, EPROM, EEPROM, non-volatile memory (NANDFLASH), solid-state drive (SSD)), etc.

[0297] In order to implement the above embodiments, the present application also proposes a computer program product.

[0298] The computer program product includes a computer program which, when executed by a processor, implements the present application. Figures 2 to 5 A downlink fault detection method according to any embodiment.

[0299] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0300] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer executable instructions. These computer executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0301] These processor executable instructions may also be stored in a processor readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the processor readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0302] These processor-executable instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0303] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A downlink fault detection method, characterized in that: include: When a downlink failure of the target cell is detected, the test parameters of the target cell under the current radio frame are read from a storage module in a processing chip of an indoor baseband processing unit BBU; wherein the downlink includes a communication link between the BBU and an active antenna unit AAU corresponding to the target cell; Determining scheduling parameters and cell parameters according to the test parameters; Inputting the scheduling parameters and the cell parameters in series into a bit-level processing module, a symbol-level processing module, a compression module, and a carrier antenna CA switching module in the processing chip; The cause of the downlink failure is determined according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module.

2. The method according to claim 1, characterized in that The determining the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module comprises: Obtaining a first actual output of the CA switching module, and determining whether the processing chip fails according to the first actual output; If the processing chip fails, a second actual output of a target processing module is obtained; wherein the target processing module includes the bit-level processing module and / or the symbol-level processing module; A fault cause of the processing chip in the downlink is determined according to the second actual output.

3. The method according to claim 2, characterized in that The step of determining whether the processing chip fails according to the first actual output includes: querying a first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by performing a simulation test on the CA switching module according to the test parameters; In the case where the first standard output does not match the first actual output, determining that the processing chip fails; When the first standard output matches the first actual output, it is determined that the processing chip has not failed.

4. The method according to claim 2, characterized in that: The determining, according to the second actual output, a fault cause of the processing chip in the downlink includes: Obtaining a second actual output of the symbol-level processing module in the processing chip; Querying a second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; When the second actual output of the symbol-level processing module matches the second standard output, it is determined that the cause of the failure of the processing chip in the downlink is that the compression module and / or the CA switching module fails.

5. The method according to claim 4, characterized in that The determining, according to the second actual output, a fault cause of the processing chip in the downlink further includes: In the case where the second actual output of the symbol-level processing module does not match the second standard output, obtaining the second actual output of the bit-level processing module; Querying a third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by performing a simulation test on the bit-level processing module according to the test parameters; When the second actual output of the bit-level processing module matches the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is that the symbol-level processing module fails.

6. The method according to claim 5, characterized in that The determining, according to the second actual output, a fault cause of the processing chip in the downlink further includes: In a case where the second actual output of the bit-level processing module does not match the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is that the bit-level processing module fails.

7. The method according to claim 2, characterized in that The determining the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module further includes: If the processing chip is not faulty, it is determined that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

8. The method according to any one of claims 1 to 7, characterized in that The storage module is used to store a parameter file of at least one cell, wherein the parameter file includes a test parameter of the corresponding cell in the current radio frame, the current radio frame includes M subframes, and M is a positive integer; When a downlink failure of the target cell is detected, reading the test parameters of the target cell in the current radio frame from a storage module in a processing chip in an indoor baseband processing unit BBU corresponding to the target cell includes: When a downlink failure in the target cell is detected, performing a first reading process M times on the storage module; The data read in the i-th first reading process is used as the sub-test parameter of the i-th sub-frame; wherein i is a positive integer not greater than M; The test parameter is determined according to the sub-test parameters of the M sub-frames.

9. The method according to claim 8, characterized in that When a downlink failure in the target cell is detected, performing a first reading process M times on the storage module includes: Determine a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; For the i-th first reading process, determining a target storage address from each of the candidate storage addresses; wherein the target storage address is used to store the sub-test parameters of the i-th sub-frame; According to the target data amount and the total amount of data stored in the target storage address, the second reading process is performed N times on the storage module; wherein the target data amount is used to indicate the amount of data read in a single time; and N is determined according to the ratio of the total amount to the target data amount; The data read in the N second reading processes are used as the data read in the i-th first reading process.

10. The method according to claim 9, characterized in that The first second reading process includes: determining a base address for starting reading in the first second reading process according to the first storage address of each target storage address; starting from the base address read in the first second reading process, reading the target data amount of data and using it as the data read in the first second reading process; determining a base address for starting reading in the second second reading process according to the end address of the first second reading process; The non-first second reading process includes: starting from the base address read by the second reading process this time, reading the target data volume and using it as the data read by the second reading process this time; and determining the base address for starting reading by the next second reading process based on the end address where the second reading process ends reading.

11. The method according to claim 9, characterized in that The determining, according to the test parameters, scheduling parameters and cell parameters comprises: storing the data read in each of the second reading processes into a cache module in the processing chip in sequence; Reading the scheduling parameter from a first storage area in the cache module; The cell parameters are read from the second storage area in the cache module.

12. The method according to claim 11, characterized in that The step of sequentially storing the data read in each of the second reading processes into a cache module in the processing chip includes: For any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to a cell from data read in any second reading process; According to a first output format of the PCIE interface in the processing chip, format conversion is performed on the first sub-parameter to obtain a first sub-parameter of the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; According to a second output format of the PCIE interface in the processing chip, format conversion is performed on the second sub-parameter to obtain a second sub-parameter of the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by the layer 2 to the processing chip; The first sub-parameter of the first output format is cached in the first storage area, and the second sub-parameter of the second output format is cached in the second storage area.

13. The method according to claim 12, characterized in that When a downlink failure of the target cell is detected, the method further includes: Disconnecting the communication link between the PCIE interface and the bit-level processing module; A communication link is established between the storage unit and the bit-level processing module.

14. The method according to any one of claims 1 to 7, characterized in that The processing chip is a field programmable gate array FPGA, and the storage module is a double data rate synchronous dynamic random access memory DDR SDRAM.

15. An access network device, characterized in that: Including memory, transceiver, processor; Memory for storing computer programs; a transceiver, for transmitting and receiving data under the control of the processor; A processor is configured to read the computer program in the memory and perform the following operations: When a downlink failure of the target cell is detected, the test parameters of the target cell under the current radio frame are read from a storage module in a processing chip of an indoor baseband processing unit BBU; wherein the downlink includes a communication link between the BBU and an active antenna unit AAU corresponding to the target cell; Determining scheduling parameters and cell parameters according to the test parameters; Inputting the scheduling parameters and the cell parameters in series into a bit-level processing module, a symbol-level processing module, a compression module, and a carrier antenna CA switching module in the processing chip; The cause of the downlink failure is determined according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module.

16. The access network device according to claim 15, characterized in that: The processor determines the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module, specifically: Obtaining a first actual output of the CA switching module, and determining whether the processing chip fails according to the first actual output; If the processing chip fails, a second actual output of a target processing module is obtained; wherein the target processing module includes the bit-level processing module and / or the symbol-level processing module; A fault cause of the processing chip in the downlink is determined according to the second actual output.

17. The access network device according to claim 16, characterized in that: The processor determines, according to the first actual output, whether the processing chip fails, specifically: querying a first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by performing a simulation test on the CA switching module according to the test parameters; In the case where the first standard output does not match the first actual output, determining that the processing chip fails; When the first standard output matches the first actual output, it is determined that the processing chip has not failed.

18. The access network device according to claim 16, characterized in that: The processor determines, according to the second actual output, a fault cause of the processing chip in the downlink, specifically: Obtaining a second actual output of the symbol-level processing module in the processing chip; Querying a second standard output corresponding to the symbol-level processing module in the current wireless frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; When the second actual output of the symbol-level processing module matches the second standard output, it is determined that the cause of the failure of the processing chip in the downlink is that the compression module and / or the CA switching module fails.

19. The access network device according to claim 18, characterized in that: The processor determines, according to the second actual output, a fault cause of the processing chip in the downlink, specifically: In the case where the second actual output of the symbol-level processing module does not match the second standard output, obtaining the second actual output of the bit-level processing module; Querying a third standard output corresponding to the bit-level processing module in the current wireless frame; wherein the third standard output is obtained by performing a simulation test on the bit-level processing module according to the test parameters; When the second actual output of the bit-level processing module matches the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is that the symbol-level processing module fails.

20. The access network device according to claim 19, characterized in that: The processor determines, according to the second actual output, a fault cause of the processing chip in the downlink, specifically: In a case where the second actual output of the bit-level processing module does not match the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is that the bit-level processing module fails.

21. The access network device according to claim 16, characterized in that: The processor determines the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module, specifically: If the processing chip is not faulty, it is determined that the cause of the downlink failure is a failure of layer 2 in the BBU or a failure of the AAU.

22. The access network device according to any one of claims 15 to 21, characterized in that: The storage module is used to store a parameter file of at least one cell, wherein the parameter file includes a test parameter of the corresponding cell in the current radio frame, the current radio frame includes M subframes, and M is a positive integer; The processor executes, when monitoring a downlink failure of the target cell, reading the test parameters of the target cell in the current radio frame from a storage module in a processing chip in an indoor baseband processing unit BBU corresponding to the target cell, specifically: When a downlink failure in the target cell is detected, performing a first reading process M times on the storage module; The data read in the i-th first reading process is used as the sub-test parameter of the i-th sub-frame; wherein i is a positive integer not greater than M; The test parameter is determined according to the sub-test parameters of the M sub-frames.

23. The access network device according to claim 22, characterized in that: When the processor detects that a downlink failure occurs in the target cell, the processor executes a first reading process M times on the storage module, specifically: Determine a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; For the i-th first reading process, determining a target storage address from each of the candidate storage addresses; wherein the target storage address is used to store the sub-test parameters of the i-th sub-frame; According to the target data amount and the total amount of data stored in the target storage address, the second reading process is performed N times on the storage module; wherein the target data amount is used to indicate the amount of data read in a single time; and N is determined according to the ratio of the total amount to the target data amount; The data read in the N second reading processes are used as the data read in the i-th first reading process.

24. The access network device according to claim 23, characterized in that: The processor performs the first second reading process, specifically: determining a base address for starting to read the first second reading process according to a first storage address in each of the target storage addresses; Starting from the base address read by the first second reading process, reading the target data amount of data, and using it as the data read by the first second reading process; Determine a base address for starting reading of the second reading process for the second time according to the end address of the first reading of the second reading process; The processor executes the non-first second reading process, specifically: starting from the base address read by the second reading process this time, read the target data volume and use it as the data read by the second reading process this time; according to the end address where the second reading process ends reading this time, determine the base address for starting reading by the next second reading process.

25. The access network device according to claim 23, characterized in that: The processor determines the scheduling parameters and the cell parameters according to the test parameters, specifically: storing the data read in each of the second reading processes into a cache module in the processing chip in sequence; Reading the scheduling parameter from a first storage area in the cache module; The cell parameters are read from the second storage area in the cache module.

26. The access network device according to claim 25, characterized in that: The processor executes the step of sequentially storing the data read in each of the second reading processes into a cache module in the processing chip, specifically: For any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to a cell from data read in any second reading process; According to a first output format of the PCIE interface in the processing chip, format conversion is performed on the first sub-parameter to obtain a first sub-parameter of the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; According to a second output format of the PCIE interface in the processing chip, format conversion is performed on the second sub-parameter to obtain a second sub-parameter of the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by the layer 2 to the processing chip; The first sub-parameter of the first output format is cached in the first storage area, and the second sub-parameter of the second output format is cached in the second storage area.

27. The access network device according to claim 26, characterized in that: The processor is further configured to perform the following operations: When a downlink failure of the target cell is detected, disconnecting the communication link between the PCIE interface and the bit-level processing module; A communication link is established between the storage unit and the bit-level processing module.

28. The access network device according to any one of claims 15 to 21, characterized in that: The processing chip is a field programmable gate array FPGA, and the storage module is a double data rate synchronous dynamic random access memory DDR SDRAM.

29. A downlink fault detection device, characterized in that: include: A reading unit, configured to read the test parameters of the target cell in the current radio frame from a storage module in a processing chip of an indoor baseband processing unit BBU when a downlink failure of the target cell is detected; wherein the downlink includes a communication link between the BBU and an active antenna unit AAU corresponding to the target cell; A first determining unit, configured to determine a scheduling parameter and a cell parameter according to the test parameter; An input unit, used to serially input the scheduling parameters and the cell parameters into a bit-level processing module, a symbol-level processing module, a compression module, and a carrier antenna CA switching module in the processing chip; The second determining unit is used to determine the fault cause of the downlink according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

30. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the method according to any one of claims 1 to 14.

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