Manufacturing method of circuit board, double-sided circuit board and multi-layer circuit board

Abstract

The invention discloses a circuit board and a manufacturing method thereof, and relates to the technical field of electronic circuit additive manufacturing. The manufacturing method comprises the following steps: preparing a laminated body; the laminated body comprises a first insulating layer with a first surface and a second surface which are vertically opposite to each other, and a metal foil layer formed on the first surface of the first insulating layer; etching the metal foil layer to form an etching circuit pattern; a first blind hole penetrating through the first insulating layer and directly abutting against the etching circuit pattern is formed; forming a first printed circuit pattern on the second surface of the first insulating layer by using conductive slurry, and filling the first blind hole to form a first conductive column for realizing conductive interconnection between the first printed circuit pattern and the etched circuit pattern; according to the invention, the printing process and the etching process are combined, so that the production efficiency of the circuit board can be effectively improved, and the waste and pollution treatment cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit additive manufacturing, and in particular relates to a method for manufacturing a circuit board, and a double-sided and multi-layer circuit board. Background Art

[0002] Double-sided or multi-layer circuit boards on the market are mostly produced and processed using chemical etching technology. Although the technology is mature and can meet the production and processing of higher-precision circuit patterns, it has low production efficiency, severe environmental pollution, and high waste and pollution treatment costs. In addition, as the country's demand for environmental improvement and carbon emission control continues to increase, its cost will continue to increase in the future. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a method for manufacturing a circuit board, a double-sided circuit board and a multi-layer circuit board, so as to solve the problems of low production efficiency, high environmental pollution, and high waste material and pollution treatment costs of traditional circuit board processes.

[0004] In some illustrative embodiments, the method for manufacturing a circuit board includes: preparing a stack; the stack includes: a first insulating layer having a first surface and a second surface vertically opposite to each other, and a metal foil layer formed on the first surface of the first insulating layer; etching the metal foil layer to form an etched circuit pattern; opening a first blind hole penetrating the first insulating layer and reaching the etched circuit pattern; forming a first printed circuit pattern on the second surface of the first insulating layer using a conductive paste, and filling the first blind hole to form a first conductive column that realizes conductive interconnection between the first printed circuit pattern and the etched circuit pattern; and electroplating on the first printed circuit pattern to form a first plated circuit pattern.

[0005] In some optional embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern is greater than that of the etched circuit pattern.

[0006] In some optional embodiments, the laying density of the printed circuit pattern on the insulating layer is lower than that of the etched circuit pattern.

[0007] In some optional embodiments, a stacked structure that has been etched but not electroplated is used as a semi-process circuit board, so that before electroplating, two semi-process circuit boards are temporarily bonded together with the surface where the etched circuit pattern is located, and after the electroplating is completed, the semi-process circuit boards are separated and restored.

[0008] In some optional embodiments, before temporarily bonding the two half-process circuit boards with the etched circuit pattern on the surface, it also includes: forming a third insulating layer on the first surface of the first insulating layer to shield the etched circuit pattern, so that the two half-process circuit boards are temporarily bonded with the third insulating layer on the surface.

[0009] In some optional embodiments, temporarily bonding the two half-process circuit boards with the etched circuit pattern surface specifically includes: temporarily bonding the two half-process circuit boards through an adhesive layer; wherein the adhesive layer includes: a stacked first adhesive layer, a carrier layer and a second adhesive layer; wherein the structural strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than the adhesion to the half-process circuit board.

[0010] In some optional embodiments, before applying the conductive paste, it also includes: forming a primer layer on the printing surface of the conductive paste, and the conductive paste is applied on the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the supporting surface.

[0011] In some optional embodiments, after etching the metal foil layer to form an etched circuit pattern, the method further includes: forming a second insulating layer on the first side of the first insulating layer to shield the etched circuit pattern; opening a second blind hole that penetrates the second insulating layer and reaches the metal foil layer; forming a second printed circuit pattern on the side of the second insulating layer away from the metal foil layer using a conductive paste, and filling the second blind hole to form a second conductive column that realizes conductive interconnection between the second printed circuit pattern and the etched circuit pattern; and electroplating on the second printed circuit pattern to form a second plated circuit pattern.

[0012] In some optional embodiments, the first plating circuit pattern and / or the second plating circuit pattern are formed synchronously or asynchronously.

[0013] Another object of the present invention is to provide a double-sided circuit board to solve the problems in the prior art.

[0014] In some illustrative embodiments, the double-sided circuit board can be obtained by the above-mentioned manufacturing method.

[0015] Another object of the present invention is to provide a multilayer circuit board to solve the problems in the prior art.

[0016] In some illustrative embodiments, the multilayer wiring board can be obtained by the above-mentioned manufacturing method.

[0017] Compared with the existing technology, this application has the following advantages:

[0018] The present invention can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs by combining the printing process with the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1This is an example of the process of the method for manufacturing a circuit board in an embodiment of the present invention;

[0020] Figure 2 This is a process example 1 of the method for manufacturing a circuit board in an embodiment of the present invention;

[0021] Figure 3 This is process example 2 of the method for manufacturing a circuit board in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0023] It should be noted that the various technical features in the embodiments of the present invention can be combined with each other without conflict.

[0024] The embodiment of the present invention discloses a method for manufacturing a circuit board, specifically, as follows: Figure 1-3 As shown, Figure 1 This is an example of the process of the method for manufacturing a circuit board in an embodiment of the present invention; Figure 2 This is a process example 1 of the method for manufacturing a circuit board in an embodiment of the present invention; Figure 3 This is a second process example of a method for manufacturing a circuit board in an embodiment of the present invention; the method for manufacturing a circuit board includes:

[0025] Step S11, preparing a stacked body;

[0026] The laminate includes: a first insulating layer 110 having a first surface and a second surface vertically opposite to each other, and a metal foil layer 210 formed on the first surface of the first insulating layer 110;

[0027] Optionally, the first insulating layer may be made of a hard board or a soft board. Hard boards include but are not limited to FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (Acrylic), etc.; soft boards include but are not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.

[0028] Optionally, the metal foil layer includes but is not limited to gold, silver, copper, iron, aluminum, zinc, nickel, etc. The metal foil layer may also include a conductive alloy material with the aforementioned materials as main components.

[0029] Optionally, the metal foil layer may be formed on the first insulating layer by lamination or deposition (chemical deposition, evaporation or sputtering), etc., which is not limited in the present invention.

[0030] Step S12: etching the metal foil layer 210 to form an etched circuit pattern 210E;

[0031] The metal foil layer can be etched by traditional chemical etching, that is, the metal foil layer is covered with a resist / film, and then an etched circuit pattern is obtained through processes such as exposure, development, etching, and film stripping. This is a prior art and will not be described in detail in this application.

[0032] Step S13: Opening a first blind via 610 penetrating the first insulating layer 110 and reaching the etched circuit pattern 210E;

[0033] The first blind hole in the embodiment of the present invention is not limited to being realized by mechanical drilling or laser drilling. Specifically, it can be etched from the second surface of the insulating layer until the etching circuit pattern is reached.

[0034] Optionally, after the first blind hole processing is completed, the method may further include: using a plasma plasma generator to clean the blind hole, thereby removing the residual insulating layer and exposing the complete metal surface at the bottom of the blind hole as much as possible, so as to improve the reliability of subsequent conductive interconnection and reduce contact resistance.

[0035] Preferably, the temperature of the insulating layer can be controlled to reach the glass transition temperature of the material, and then the blind hole cleaning process can be performed by plasma, which can effectively improve the removal effect of residual impurities.

[0036] Step S14: forming a first printed circuit pattern 310 on the second surface of the first insulating layer 110 using a conductive paste, and filling the first blind via to form a first conductive pillar 510 for achieving conductive interconnection between the first printed circuit pattern 310 and the etched circuit pattern 210E;

[0037] Optionally, the first printed circuit pattern 310 and the first conductive pillar 510 may be formed by one printing process, or may be formed separately by multiple printing processes, which is not limited in the present application.

[0038] Moreover, when the two are formed separately through multiple printings, the forming order of the conductive column and the first printed circuit pattern can be reversed, depending on actual needs, that is, the hole can be plugged first and then surface printed, or the surface can be printed first and then plugged. This application does not impose any restrictions on this.

[0039] Optionally, the printing process used for the conductive paste in the embodiment of the present invention includes but is not limited to screen printing, direct writing printing, inkjet printing, etc.

[0040] Preferably, when using the screen printing process, the printed circuit pattern and the conductive column can be formed separately through at least two printing processes, so that different printing parameters (such as the scraper pressure (degree of pressure) of screen printing) can be adjusted in the printing processes with different requirements for the printed circuit pattern and the conductive column to meet the surface forming and plugging forming quality.

[0041] The conductive paste in the embodiment of the present invention refers to a composite low-temperature conductive paste mainly composed of a thorough mixture of conductive fillers, resin binders and solvents. After the paste is fully cured, the solvent will fully evaporate, thereby converting it into a conductive film in which the conductive fillers are bound by the resin film-forming material.

[0042] The conductive filler is not limited to one or more of metal particles, graphene, conductive carbon black, carbon nanotubes, and conductive particles such as core-shell structures. The metal particles are not limited to one or more of gold, silver, copper, iron, nickel, zinc, and silver-coated copper powder. The resin binder can be any commercially available resin, including but not limited to one or more of epoxy resin, acrylic resin, naphthalene-containing epoxy resin, polyaromatic epoxy resin, multifunctional epoxy resin, bismaleimide resin, and polyimide resin. This application does not impose any restrictions on the choice of solvent.

[0043] The curing method of the conductive paste in the embodiment of the present invention is not limited to thermosetting, light curing, electromagnetic radiation or other curing methods, and a corresponding curing initiator can be selected or added according to actual needs.

[0044] During the process of applying curing conditions to the low-temperature conductive paste, the insulating layer may also be affected accordingly, resulting in shrinkage and expansion deformation of the insulating layer. However, due to the existence of the etched circuit pattern closely combined with it, the etched circuit pattern that is not affected by the curing conditions can to a certain extent hinder the shrinkage and expansion of the insulating layer. Although the effect is not as good as that of a whole metal foil layer, it can also ensure the quality of the circuit board to a certain extent and reduce the difficulty of the alignment compensation calculation in the corresponding process.

[0045] Step S15 : forming a first plated circuit pattern 410 on the first printed circuit pattern 310 by electroplating.

[0046] The main function of the plated circuit pattern is to improve one or more of the conductivity, stability, solderability, oxidation resistance, and surface properties of the printed circuit pattern.

[0047] In some embodiments, the metal foil layer in the embodiments of the present invention can directly use a metal foil of the target thickness, so that an etched circuit pattern of the target thickness can be directly produced through a chemical etching process, and therefore there is no need to increase the plating thickness of the etched circuit pattern surface; therefore, the etched circuit pattern can be shielded before step S15 to prevent contact with the electroplating solution.

[0048] Since the first printed circuit pattern requires electroplating to improve its conductivity and surface properties, using a thin metal foil and thickening it to the target thickness through an electroplating process is difficult to control precision in actual production. This is primarily because the conductive materials on both sides are different, so the same electroplating parameters are unlikely to produce the same plating effect on both sides. During electroplating, the coating formation rate on the metal foil side is often much higher than that on the printed circuit side, making it difficult to achieve the same plating parameters for both sides in a single electroplating process. Separate electroplating would require additional, cumbersome steps, significantly reducing production efficiency and making actual costs difficult to estimate. Therefore, in the embodiments of the present invention, by electroplating only the printed circuit pattern to form the plated circuit pattern, parameters such as the thickness of the plated circuit pattern can be effectively controlled.

[0049] In some embodiments, the plated metal includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, and the like.

[0050] The present invention can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs by combining the printing process with the etching process.

[0051] The applicant has discovered that in the double-sided circuit boards / multi-layer circuit boards currently on the market, circuits with higher laying density and higher precision can be implemented using only one or several layers of two or more layers of circuits, without all of them being designed as higher precision circuits. Therefore, traditional etching processes can be used to implement circuits with higher precision requirements (i.e., the circuits actually occupy more area within a specified range), while circuits in other layers can be implemented using printing processes with relatively lower precision.

[0052] Furthermore, since the etching target is targeted at the side with a higher laying density, the amount of metal foil actually etched away is greatly reduced. While ensuring quality, this can effectively reduce waste costs and pollution treatment costs.

[0053] In some embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern (the first printed circuit pattern and / or the second printed circuit pattern) in the embodiments of the present invention is greater than that of the etched circuit pattern.

[0054] In some embodiments, the laying density of the printed circuit patterns (the first printed circuit patterns and / or the second printed circuit patterns) on the insulating layer is lower than that of the etched circuit patterns.

[0055] Optionally, the minimum line spacing and / or minimum line width of the etched circuit pattern may range from 1-100 μm, and the minimum line spacing and / or minimum line width of the printed circuit pattern (first printed circuit pattern and / or second printed circuit pattern) may range from 2-200 μm.

[0056] Those skilled in the art should understand that although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected to be smaller than the actual parameters of the minimum line spacing and / or minimum line width of the printed circuit pattern according to needs.

[0057] In some embodiments, after etching the metal foil layer to form an etched circuit pattern, the present invention further includes:

[0058] forming a second insulating layer 120 on the first surface of the first insulating layer 110 to shield the etched circuit pattern 210E;

[0059] A second blind via 620 is formed through the second insulating layer 120 and directly reaches the etched circuit pattern 210E;

[0060] Using a conductive paste to form a second printed circuit pattern 320 on a side of the second insulating layer 120 away from the etched circuit pattern 210E, and filling the second blind via to form a second conductive pillar 520 for achieving conductive interconnection between the second printed circuit pattern 320 and the etched circuit pattern 210E;

[0061] A second plated circuit pattern 420 is formed on the second printed circuit pattern 320 by electroplating.

[0062] The material selection range of the second insulating layer is the same as that of the first insulating layer.

[0063] This embodiment is suitable for manufacturing a three-layer circuit board with a simple structure. The opening and cleaning of the second blind hole, or the second printed circuit pattern, the second conductive column, the second plated circuit pattern, etc. can all refer to the above-mentioned corresponding embodiments and will not be repeated here.

[0064] In some embodiments, the first plated circuit pattern and / or the second plated circuit pattern are formed synchronously or asynchronously. The first plated circuit pattern and the second plated circuit pattern can be formed simultaneously by a single electroplating operation or can be formed separately. Preferably, the first plated circuit pattern and the second plated circuit pattern are formed simultaneously by a single electroplating operation.

[0065] In some embodiments, the stacked structure that has been etched but not electroplated can be used as a semi-process circuit board, so that before electroplating, two semi-process circuit boards are temporarily bonded together with the surface where the etched circuit pattern is located, and after the electroplating is completed, the semi-process circuit boards are separated and restored.

[0066] This embodiment uses two half-process circuit boards to shield their respective etched circuit patterns to prevent them from being affected by electroplating. On the other hand, it can also combine the two circuit boards into a temporary integrated structure to improve electroplating efficiency, and then separate and reduce them after electroplating is completed.

[0067] In some embodiments, temporarily bonding the two semi-processed circuit boards together using the etched circuit pattern surfaces specifically includes:

[0068] Temporary bonding of the two semi-process circuit boards is achieved through the adhesive layer 800; wherein, the adhesive layer 800 may include: a stacked first adhesive layer, a carrier layer, and a second adhesive layer; wherein the structural strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than the adhesion to the semi-process circuit board.

[0069] Through the design of the carrier layer and the double-sided adhesive layer and the adhesion between them, on the one hand, the problem of the single adhesive layer being difficult to peel off due to lack of structural strength is solved, making the adhesive layer easier to remove; on the other hand, the addition of a carrier layer with a certain structural strength is conducive to reducing bubbles between the colloid bonding surfaces, making the bonding surfaces tighter, and avoiding leakage of the plating liquid and causing undesirable plating on the metal foil layer.

[0070] Optionally, the carrier layer includes but is not limited to a non-adhesive soft board or a hard board.

[0071] In some embodiments, before temporarily bonding the two semi-processed circuit boards on the surfaces where the etched circuit patterns are located, the following steps may be further included:

[0072] A third insulating layer for shielding the etched circuit pattern is formed on the first surface of the first insulating layer, so that the two half-process circuit boards are temporarily bonded together with the surface where the third insulating layer is located.

[0073] In some embodiments, before applying the conductive paste, it also includes: forming a primer layer on the printing surface of the conductive paste, and the conductive paste is applied on the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the supporting surface.

[0074] The primer layer includes but is not limited to a first primer layer 910 between the first insulating layer 110 and the first printed circuit layer 310 and / or a second primer layer 920 between the second insulating layer 120 and the second printed circuit layer 320 .

[0075] In some embodiments, after the electroplating is completed, the following steps may be performed: forming a cover layer (first cover layer 710, second cover layer 720) on the etched circuit pattern and / or the plated circuit pattern (first plated circuit pattern and / or second plated circuit pattern); wherein the cover layer partially or completely shields the etched circuit pattern and / or the plated circuit pattern. The cover film may be bonded to the etched circuit pattern and the plated circuit pattern via a fourth adhesive layer and a fifth adhesive layer.

[0076] The cover layer shields part or all of the etched circuit pattern and / or the plated circuit pattern (the first plated circuit pattern and / or the second plated circuit pattern). The areas of the etched circuit pattern and / or the plated circuit pattern (the first plated circuit pattern and / or the second plated circuit pattern) exposed by the cover film are not limited to being used for gold fingers, solder pads, etc.

[0077] In some embodiments, the second insulating layer or the third insulating layer may serve as a cover layer.

[0078] Example 1

[0079] A method for manufacturing a double-sided circuit board, comprising:

[0080] S21, preparing a laminate; the laminate comprising: a first insulating layer having a first surface and a second surface vertically opposite to each other, and a metal foil layer formed on the first surface of the first insulating layer;

[0081] S22, etching the metal foil layer to form an etched circuit pattern;

[0082] S23, forming a first covering layer (second insulating layer) on the first surface of the first insulating layer to shield the etching circuit pattern; wherein the first covering layer has a window to partially expose the etching circuit pattern;

[0083] S24, forming a first primer layer on the second surface of the first insulating layer;

[0084] S25, opening a first blind hole penetrating through the first base coating layer and the first insulating layer and directly reaching the etching circuit pattern;

[0085] S26, forming a first printed circuit pattern on the first primer layer using a conductive paste, and filling the first blind hole to form a first conductive pillar for achieving conductive interconnection between the first printed circuit pattern and the etched circuit pattern;

[0086] S27, temporarily laminating two semi-processed circuit boards after step S26, using the surface where the first printed circuit pattern is located;

[0087] S28, electroplating on the first printed circuit patterns on both sides to form a first plated circuit pattern;

[0088] S29, split and restore 2 half-process circuit boards;

[0089] S30, forming a second covering layer on the first plated circuit pattern of the semi-processed circuit board, wherein the second covering layer is provided with a window exposing a portion of the first etched circuit pattern.

[0090] Example 2

[0091] A method for manufacturing a three-layer circuit board, comprising:

[0092] S41, preparing a laminate; the laminate comprising: a first insulating layer having a first surface and a second surface vertically opposite to each other, and a metal foil layer formed on the first surface of the first insulating layer;

[0093] S42, etching the metal foil layer to form an etched circuit pattern;

[0094] S43, forming a second insulating layer on the first surface of the first insulating layer to shield the etched circuit pattern;

[0095] S44, forming a first primer layer on the second surface of the first insulating layer, and forming a second primer layer on a side of the second insulating layer away from the etching circuit pattern;

[0096] S45, opening a first blind hole penetrating the first primer layer and the first insulating layer and directly reaching the etched circuit pattern, and a second blind hole penetrating the second primer layer and the second insulating layer and directly reaching the etched circuit pattern;

[0097] S46, forming a first printed circuit pattern on the first primer layer using a conductive paste, and filling the first blind via to form a first conductive pillar for achieving conductive interconnection between the first printed circuit pattern and the etched circuit pattern; and forming a second printed circuit pattern on the second primer layer using a conductive paste, and filling the second blind via to form a second conductive pillar for achieving conductive interconnection between the second printed circuit pattern and the etched circuit pattern;

[0098] S47 , forming a first plated circuit pattern by electroplating on the first printed circuit pattern, and forming a second plated circuit pattern by electroplating on the second printed circuit pattern.

[0099] S48, forming a covering layer on the first plated circuit pattern and the second plated circuit pattern; wherein the covering layer has windows for partially exposing the first plated circuit pattern and the second plated circuit pattern.

[0100] An embodiment of the present invention discloses a circuit board, which can be obtained by the above-mentioned manufacturing method.

[0101] An embodiment of the present invention discloses a double-sided circuit board, comprising: an etched circuit pattern 210E, a first insulating layer 110, a first printed circuit pattern 310, and a first plated circuit pattern 410 stacked in sequence; wherein the first plated circuit pattern 410 is formed on the first printed circuit pattern 310, and the first printed circuit pattern 310 and the etched circuit pattern 210E are interconnected via a first conductive column penetrating the first insulating layer 110.

[0102] In some embodiments, a first primer layer is provided between the first insulating layer and the first printed circuit layer;

[0103] In some embodiments, a first covering layer is provided on the etched circuit pattern, and a second covering layer is provided on the first plated circuit pattern; wherein the first covering layer and the second covering layer are respectively provided with windows exposing parts of the corresponding circuit patterns.

[0104] An embodiment of the present invention discloses a multilayer circuit board, comprising: a first plated circuit pattern, a first printed circuit pattern, a first insulating layer, an etched circuit pattern, a second insulating layer, a second printed circuit pattern, and a second plated circuit pattern stacked in sequence; wherein the first plated circuit pattern is formed on the first printed circuit pattern, and the second plated circuit pattern is formed on the second printed circuit pattern; the first printed circuit pattern and the etched circuit pattern are interconnected by a first conductive column penetrating the first insulating layer, and the second printed circuit pattern and the etched circuit pattern are interconnected by a second conductive column penetrating the second insulating layer.

[0105] In some embodiments, a first primer layer is provided between the first insulating layer and the first printed circuit layer; and a second primer layer is provided between the second insulating layer and the second printed circuit layer.

[0106] In some embodiments, a second covering layer is provided on the first plated circuit pattern, and a first covering layer is provided on the second plated circuit pattern. The two covering layers are respectively provided with windows exposing a portion of the corresponding circuit pattern.

[0107] In some embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern in the embodiments of the present invention is greater than that of the etched circuit pattern.

[0108] In some embodiments, the printed circuit pattern is laid out on the insulating layer at a density lower than that of the etched circuit pattern.

[0109] The minimum line spacing and / or minimum line width of the etched circuit pattern may be in the range of 1-100 μm, while the minimum line spacing and / or minimum line width of the printed circuit pattern may be in the range of 2-200 μm.

[0110] Those skilled in the art should understand that although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected to be smaller than the actual parameters of the minimum line spacing and / or minimum line width of the printed circuit pattern according to needs.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a circuit board, characterized in that: include: Prepare a layer of laminate; The stacked body comprises: a first insulating layer having a first surface and a second surface vertically opposite to each other, and a metal foil layer formed on the first surface of the first insulating layer; Etching the metal foil layer to form an etched circuit pattern; Opening a first blind hole that penetrates the first insulating layer and reaches the etching circuit pattern; Forming a first printed circuit pattern on the second surface of the first insulating layer using a conductive paste, and filling the first blind hole to form a first conductive column for realizing conductive interconnection between the first printed circuit pattern and the etched circuit pattern; A first plated circuit pattern is formed by electroplating on the first printed circuit pattern.

2. The method according to claim 1, characterized in that: The minimum line width and / or minimum line spacing of the printed circuit pattern is greater than that of the etched circuit pattern; and / or, The laying density of the printed circuit pattern on the insulating layer is smaller than that of the etched circuit pattern.

3. The method according to claim 1, characterized in that: The stacked structure that has been etched but not electroplated is used as a semi-process circuit board, so that before electroplating, two semi-process circuit boards are temporarily bonded together on the surface where the etched circuit pattern is located, and after the electroplating is completed, the semi-process circuit boards are separated and restored.

4. The method according to claim 3, characterized in that: Before temporarily bonding the two half-process circuit boards on the surface where the etched circuit pattern is located, the method further includes: A third insulating layer for shielding the etching circuit pattern is formed on the first surface of the first insulating layer, so that the two half-process circuit boards are temporarily bonded together with the surface where the third insulating layer is located.

5. The manufacturing method according to claim 3, characterized in that: The temporarily bonding the two half-process circuit boards by etching the circuit pattern surface specifically includes: Temporary bonding of the two half-process circuit boards is achieved through an adhesive layer; wherein the adhesive layer includes: a stacked first adhesive layer, a carrier layer, and a second adhesive layer; wherein the structural strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than that to the half-process circuit board.

6. The method according to claim 1, characterized in that: Before applying the conductive paste, it also includes: forming a primer layer on the printing surface of the conductive paste, and the conductive paste is applied on the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the supporting surface.

7. The manufacturing method according to claim 1, characterized in that: After etching the metal foil layer to form an etching circuit pattern, the method further comprises: forming a second insulating layer on the first surface of the first insulating layer to shield the etching circuit pattern; Opening a second blind hole penetrating through the second insulating layer and directly reaching the etching circuit pattern; Using conductive paste to form a second printed circuit pattern on a side of the second insulating layer away from the etching circuit pattern, and filling the second blind hole to form a second conductive column to achieve conductive interconnection between the second printed circuit pattern and the etching circuit pattern; A second plated circuit pattern is formed on the second printed circuit pattern by electroplating.

8. The method according to claim 7, characterized in that: The first plating circuit pattern and / or the second plating circuit pattern are formed synchronously or asynchronously.

9. A double-sided circuit board, characterized in that: Obtained by the preparation method according to any one of claims 1 to 6.

10. A multilayer circuit board, characterized in that: Obtained by the preparation method according to any one of claims 1 to 8.

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