Multilayer circuit board and manufacturing method thereof

Abstract

The invention discloses a multilayer circuit board and a manufacturing method thereof, and relates to the technical field of electronic circuit additive manufacturing. The manufacturing method comprises the following steps: preparing a first laminated body; a first blind hole penetrating through the first insulating layer and directly abutting against the first metal foil layer is formed; forming a printed circuit pattern on the second surface of the insulating layer, and filling the first blind hole to form a conductive column; electroplating on the printed circuit pattern to form a plated circuit pattern; preparing a second laminated body; bonding the surface of the second insulating layer of the second laminated body with the surface of the plated circuit pattern of the first laminated body; a second blind hole penetrating through the second metal foil layer and the second insulating layer and directly abutting against the plating circuit pattern is formed; performing hole metallization processing on the second blind hole to obtain a plated-through hole; and etching the first metal foil layer and the second metal foil layer to form a first etching circuit pattern and a second etching circuit pattern. According to the method, the printing process and the etching process are combined, so that the production efficiency of the circuit board can be effectively improved, and the waste and pollution treatment cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit additive manufacturing, and in particular relates to a multilayer circuit board and a manufacturing method thereof. Background Art

[0002] Double-sided or multi-layer circuit boards on the market are mostly produced and processed using chemical etching technology. Although the technology is mature and can meet the production and processing of higher-precision circuit patterns, it has low production efficiency, severe environmental pollution, high waste costs and pollution treatment costs. In addition, as the country's demand for environmental improvement and carbon emission control continues to increase, its cost will continue to increase in the future. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a method for manufacturing a circuit board, a double-sided circuit board and a multi-layer circuit board, so as to solve the problems of low production efficiency, large environmental pollution, high waste cost and pollution treatment cost of traditional circuit board processes.

[0004] In some illustrative embodiments, the method for manufacturing the multilayer circuit board includes: preparing a first laminate; the first laminate includes: a first insulating layer having a first surface and a second surface vertically opposite to each other, and a first metal foil layer formed on the first surface of the first insulating layer; opening a first blind hole penetrating through the first insulating layer and reaching the first metal foil layer; forming a printed circuit pattern on the second surface of the insulating layer using a conductive paste, and filling the first blind hole to form a conductive column for realizing conductive interconnection between the printed circuit pattern and the first metal foil layer; electroplating on the printed circuit pattern to form a plated circuit pattern; preparing a second laminate; the second laminate The invention comprises: a second insulating layer having a first surface and a second surface vertically opposite to each other, and a second metal foil layer formed on the first surface of the second insulating layer; the surface of the second laminate where the second insulating layer is located is bonded to the surface of the first laminate where the plated circuit pattern is located; a second blind hole is opened which penetrates the second metal foil layer and the second insulating layer and reaches the plated circuit pattern; the second blind hole is subjected to hole metallization treatment to obtain a metallized hole which realizes conductive interconnection between the second metal foil layer and the plated circuit pattern; the first metal foil layer is etched to form a first etched circuit pattern, and the second metal foil layer is etched to form a second etched circuit pattern.

[0005] In some optional embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern is greater than that of the etched circuit pattern.

[0006] In some optional embodiments, the laying density of the printed circuit pattern on the insulating layer is lower than that of the etched circuit pattern.

[0007] In some optional embodiments, the printed circuit pattern includes: at least two printed circuit units that are not in direct contact, and the printed circuit units are electrically connected to the first metal foil layer through conductive pillars.

[0008] In some optional embodiments, the metallization treatment of the second blind hole specifically includes: forming a conductive carbon layer electrically connected to the metal foil layer and the second metal foil layer on the hole wall of the second blind hole, and then forming a plated metal layer on the conductive carbon layer by electroplating.

[0009] In some optional embodiments, the first metal foil layer and / or the second metal foil layer has or does not have surface plating during the electroplating process.

[0010] In some optional embodiments, before the first blind hole is opened that penetrates the first insulating layer and reaches the first metal foil layer, it also includes: forming a primer layer on the second surface of the first insulating layer, and the first blind hole penetrates the primer layer; wherein the primer layer is used to enhance the adhesion of the conductive paste on the first insulating layer.

[0011] In some optional embodiments, after etching the first metal foil layer to form a first etching circuit pattern, and etching the second metal foil layer to form a second etching circuit pattern, it also includes: forming a covering layer on the first etching circuit pattern and / or the second etching circuit pattern; wherein the covering layer shields part or all of the first etching circuit pattern and / or the second etching circuit pattern.

[0012] Another object of the present invention is to provide a multilayer circuit board to solve the problems in the prior art.

[0013] In some illustrative embodiments, the multilayer wiring board can be obtained by any of the manufacturing methods described above.

[0014] In some illustrative embodiments, the multilayer circuit board includes: a second etched circuit pattern, a second insulating layer, a plated circuit pattern, a printed circuit pattern, a first insulating layer and a second etched circuit pattern stacked in sequence; wherein the plated circuit pattern is formed on the printed circuit pattern, the printed circuit pattern and the first etched circuit are interconnected via a conductive column penetrating the first insulating layer, and the plated circuit pattern and the second etched circuit are interconnected via a metallized hole penetrating the second insulating layer.

[0015] In some optional embodiments, a covering layer is formed on the first etching circuit pattern and / or the second etching circuit pattern; wherein the covering layer shields part or all of the first etching circuit pattern and / or the second etching circuit pattern.

[0016] In some optional embodiments, a primer layer is formed between the first insulating layer and the printed circuit pattern, and the conductive column penetrates the primer layer; wherein the primer layer is used to enhance the adhesion of the conductive paste on the first insulating layer.

[0017] In some optional embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern is greater than that of the etched circuit pattern.

[0018] In some optional embodiments, the laying density of the printed circuit pattern on the insulating layer is lower than that of the etched circuit pattern.

[0019] Compared with the prior art, this application has the following advantages:

[0020] The present invention can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs by combining the printing process with the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is an example of a process of a method for manufacturing a circuit board in an embodiment of the present invention;

[0022] Figure 2 This is a process example of a method for manufacturing a circuit board in an embodiment of the present invention;

[0023] Figure 3 This is an example of an island structure of a circuit board in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] It should be noted that the various technical features in the embodiments of the present invention can be combined with each other without conflict.

[0026] The present invention discloses a method for manufacturing a circuit board. Specifically, Figure 1-2 As shown, Figure 1 This is an example of a process of a method for manufacturing a circuit board in an embodiment of the present invention; Figure 2 This is a process example of a method for manufacturing a circuit board in an embodiment of the present invention. The method for manufacturing a circuit board includes:

[0027] Step S11, preparing a first stack;

[0028] The first stacked body includes: a first insulating layer 110 having a first surface and a second surface vertically opposite to each other, and a first metal foil layer 120 formed on the first surface of the first insulating layer 110;

[0029] The first insulating layer may be made of a hard board or a soft board. The hard board includes but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (Acrylic), etc.; the soft board includes but is not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.;

[0030] The first metal foil layer includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, etc. The first metal foil layer may also include a conductive alloy material with the aforementioned materials as main components.

[0031] The first metal foil layer may be formed on the first insulating layer by lamination or deposition (chemical deposition, evaporation or sputtering), etc., and the present invention is not limited to this.

[0032] Step S12, opening a first blind hole 610 penetrating through the first insulating layer 110 and directly reaching the first metal foil layer 120;

[0033] The first blind hole is not limited to being realized by mechanical drilling or laser drilling, and can be specifically etched from the second surface of the first insulating layer until the first metal foil layer is etched.

[0034] Optionally, after the first blind hole is processed, the method may further include: using a plasma generator to clean the first blind hole, thereby removing the remaining first insulating layer and exposing the complete metal surface at the bottom of the first blind hole as much as possible, so as to improve the reliability of subsequent conductive interconnection and reduce contact resistance.

[0035] Preferably, the temperature of the first insulating layer can be controlled to reach the glass transition temperature of the material, and then surface treatment can be performed by plasma, which can effectively improve the removal effect of residual impurities.

[0036] Step S13, forming a printed circuit pattern 310 on the second surface of the first insulating layer 110 by using a conductive paste, and filling the first blind hole 610 to form a conductive column 510 for realizing conductive interconnection between the printed circuit pattern 310 and the first metal foil layer 120;

[0037] The printed circuit pattern and the conductive column can be formed by one printing process or by multiple printing processes, and the present application does not limit this. In the embodiment of separate forming, the forming order of the conductive column and the printed circuit pattern can be reversed, depending on actual needs, and the present application does not limit this.

[0038] The printing process used in the embodiments of the present invention includes but is not limited to screen printing, direct writing printing, inkjet printing, etc.

[0039] For the embodiments using the screen printing process, the printed circuit pattern and the conductive pillars can be achieved through one or two printing processes; preferably, the printed circuit pattern and the conductive pillars can be achieved through two printing processes, so that different printing parameters are set for different printing processes to meet the molding quality of different surface and plug hole molding requirements.

[0040] The conductive paste in the embodiment of the present invention refers to a composite low-temperature conductive paste mainly composed of a conductive filler, a resin binder and a solvent. After the paste is fully cured, the solvent will fully evaporate, thereby converting it into a conductive film in which the conductive filler is bound by the resin film-forming material.

[0041] The conductive filler is not limited to one or at least two of metal particles, graphene, conductive carbon black, carbon nanotubes, and conductive particles such as core-shell structures; the metal particles are not limited to one or at least two of gold, silver, copper, iron, nickel, zinc, and silver-coated copper powder; the resin binder can be any resin on the market, including but not limited to one or at least two of epoxy resin, acrylic resin, naphthalene-containing epoxy resin, polyaromatic epoxy resin, multifunctional epoxy resin, bismaleimide resin, and polyimide resin. The present application does not limit the selection of solvents.

[0042] The curing method of the low-temperature conductive paste in the embodiment of the present invention is not limited to thermosetting, photocuring, electromagnetic radiation or other curing methods.

[0043] In the process of applying curing conditions to the conductive paste, the first insulating layer may also be affected accordingly, resulting in shrinkage and expansion deformation of the first insulating layer. However, due to the presence of the first metal foil layer closely combined with it, the first metal foil layer that is not affected by the curing conditions can effectively hinder the shrinkage and expansion of the first insulating layer, thereby improving the quality of the circuit board and reducing the difficulty of alignment in the corresponding process.

[0044] Step S14, electroplating to form a plated circuit pattern 410 on the printed circuit pattern 310;

[0045] Among them, the role of plating the circuit pattern is mainly to improve one or more of the conductivity, stability, solderability, oxidation resistance, surface properties, etc. of the printed circuit pattern.

[0046] In some embodiments, the first metal foil layer in the embodiments of the present invention can directly use a metal foil of target thickness, so that in a subsequent process, a first metal foil layer of target thickness can be directly formed through a chemical etching process. Therefore, there is no need to increase the surface plating of the first metal foil layer. Furthermore, before implementing step S14, the first metal foil layer can be shielded to prevent contact with the plating solution.

[0047] In other embodiments, the first metal foil layer may also be made of a metal foil having a thickness less than the target thickness, so that during the process of electroplating to form a plated circuit pattern, additional plating is simultaneously achieved on the surface of the first metal foil to reach the target thickness. This embodiment can omit the masking operation.

[0048] In some embodiments, the plated metal includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, and the like.

[0049] Step S15, preparing a second stack;

[0050] The second laminate includes: a second insulating layer 120 having a first surface and a second surface vertically opposite to each other, and a second metal foil layer 220 formed on the first surface of the second insulating layer 120;

[0051] The second insulating layer may be made of a hard board or a soft board. The hard board includes but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (Acrylic), etc.; the soft board includes but is not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.;

[0052] The second metal foil layer includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, etc. The second metal foil layer may also include a conductive alloy material with the aforementioned materials as main components.

[0053] The second metal foil layer may be formed on the second insulating layer by lamination or deposition (chemical deposition, evaporation or sputtering), etc., and the present invention is not limited thereto.

[0054] Step S16 , laminating the surface of the second laminate where the second insulating layer 120 is located with the surface of the first laminate where the plated circuit pattern 410 is located; wherein the two can be laminated to each other via the first adhesive layer 810 .

[0055] Step S17, opening a second blind hole 620 penetrating through the second metal foil layer 220 and the second insulating layer 120 and directly reaching the plated circuit pattern 410;

[0056] The second blind hole is not limited to being realized by mechanical drilling or laser drilling, and can be specifically etched from the second surface of the second insulating layer until the second metal foil layer is etched.

[0057] Optionally, after the second blind hole is processed, the method may further include: using a plasma generator to clean the second blind hole, thereby removing the remaining second insulating layer and exposing the complete metal surface at the bottom of the second blind hole as much as possible, so as to improve the reliability of subsequent conductive interconnection and reduce contact resistance.

[0058] Preferably, the temperature of the second insulating layer can be controlled to reach the glass transition temperature of the material, and then surface treatment can be performed by plasma, which can effectively improve the removal effect of residual impurities.

[0059] Step S18, performing hole metallization processing on the second blind hole 620 to obtain a metallized hole that realizes conductive interconnection between the second metal foil layer 220 and the plated circuit pattern 410;

[0060] Specifically, a conductive carbon layer 515 electrically connected to the plated circuit pattern 410 and the second metal foil layer 220 is formed on the hole wall of the second blind hole, and then a plated metal layer 520 is formed on the conductive carbon layer 515 by electroplating. The conductive carbon layer is not limited to conductive carbon black or conductive graphite, and is not limited to being achieved by black hole or black shadow processing. In other embodiments, the conductive carbon layer can also be formed by laser carbon planting (laser ablation to form a surface carbon layer) and other methods.

[0061] The plated metal layer 520 may fill up the second blind hole 620 , or may only be formed on the hole wall of the second blind hole 620 .

[0062] The first metal foil layer and / or the second metal foil layer may or may not be plated on the surface during the electroplating process, which may be determined according to the raw material thickness of the first metal foil layer and the second metal foil layer, and the target thickness of the first etched circuit pattern and the second etched circuit pattern; if the surface plating is not required, the first metal foil layer and the second metal foil layer may be shielded.

[0063] Step S19 , etching the first metal foil layer 210 to form a first etched circuit pattern 210E, and etching the second metal foil layer 220 to form a second etched circuit pattern 220E.

[0064] In this step, the etching treatment of the first metal foil layer and / or the second metal foil layer can be carried out by traditional chemical etching, that is, covering the metal foil layer with a resist / film, and then obtaining an etched circuit pattern through processes such as exposure, development, etching, and film stripping. This is the prior art and this application will not elaborate on it.

[0065] The etching process for the first metal foil layer and the second metal foil layer may be performed simultaneously or asynchronously.

[0066] The present invention can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs by combining the printing process with the etching process.

[0067] The applicant has found that in the double-sided circuit boards / multi-layer circuit boards currently on the market, circuits with higher laying density and higher precision can be implemented using only one or several layers of two or more layers of circuits, without all of them being designed as higher precision circuits. Therefore, the traditional etching process can be used to implement the circuits with higher precision requirements (that is, the circuits actually occupy more area within a specified range), while the circuits of other layers can be implemented using a printing process with relatively lower precision.

[0068] Furthermore, since the etching target is directed toward the side with a higher laying density, the amount of metal foil actually etched away is greatly reduced. While ensuring quality, the waste cost and pollution treatment cost can be effectively reduced.

[0069] In some embodiments, the minimum line width and / or minimum line spacing of the printed circuit pattern in the embodiments of the present invention is greater than that of the etched circuit pattern (the first etched circuit pattern and / or the second etched circuit pattern).

[0070] In some embodiments, the laying density of the printed circuit pattern on the insulating layer is smaller than that of the etched circuit pattern (the first etched circuit pattern and / or the second etched circuit pattern).

[0071] Optionally, the minimum line pitch and / or minimum line width of the etched circuit pattern (first etched circuit pattern and / or second etched circuit pattern) may range from 1-100 μm, while the minimum line pitch and / or minimum line width of the printed circuit pattern may range from 2-200 μm.

[0072] Those skilled in the art should understand that although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected to be smaller than the actual parameters of the minimum line spacing and / or minimum line width of the printed circuit pattern according to needs.

[0073] In addition, the outermost side of the multilayer circuit board in the embodiment of the present invention is an etched circuit pattern formed by a metal foil layer, and thus has good surface properties and can be well adapted to various welding processes.

[0074] Furthermore, the entire metal foil layer is fully conductively interconnected with the printed circuit pattern on the other side, which can support the requirement of including an island structure in the printed circuit pattern (that is, the printed circuit pattern includes multiple independent unit patterns) without the need to design additional electroplating leads for the island structure.

[0075] like Figure 3 As shown, in some embodiments, the printed circuit pattern may include: at least two printed circuit units 31U that are not in direct contact, and the printed circuit units 31U are electrically connected to the first metal foil layer 210 through the conductive pillars 510 .

[0076] In some embodiments, before the first blind hole 610 is opened and passes through the first insulating layer 110 and reaches the first metal foil layer 210, it also includes: forming a primer layer 710 on the second surface of the first insulating layer 110, and the first blind hole 610 passes through the primer layer 710; wherein the primer layer 710 is used to enhance the adhesion of the conductive paste on the first insulating layer 110.

[0077] In some embodiments, after etching the first metal foil layer 210 to form the first etching circuit pattern 210E, and etching the second metal foil layer 220 to form the second etching circuit pattern 220E, the process further includes: forming a covering layer (first covering layer 910, second covering layer 920) on the first etching circuit pattern 210E and / or the second etching circuit pattern 220E; wherein the covering layer shields part or all of the first etching circuit pattern and / or the second etching circuit pattern. The area exposed by the covering layer of the etching circuit pattern is not limited to being used for gold fingers, pads, etc.

[0078] The cover film may be attached to the etching circuit pattern and the plating circuit pattern through a second adhesive layer (not shown).

[0079] An embodiment of the present invention discloses a multi-layer circuit board, which can be obtained by any of the above-mentioned manufacturing methods.

[0080] An embodiment of the present invention discloses a multilayer circuit board, comprising: a second etched circuit pattern 220E, a second insulating layer 120, a plated circuit pattern 410, a printed circuit pattern 310, a first insulating layer 110, and a second etched circuit pattern 210E stacked in sequence; wherein the plated circuit pattern 410 is formed on the printed circuit pattern 310, the printed circuit pattern 310 and the first etched circuit 210E are interconnected via a conductive column 510 penetrating the first insulating layer 110, and the plated circuit pattern 410 and the second etched circuit pattern 220E are interconnected via a metallized hole penetrating the second insulating layer 120.

[0081] In some embodiments, a covering layer (first covering layer 910, second covering layer 920) is formed on the first etching circuit pattern 210E and / or the second etching circuit pattern 220E; wherein the covering layer shields part or all of the first etching circuit pattern and / or the second etching circuit pattern.

[0082] In some embodiments, a primer layer 710 is formed between the first insulating layer 110 and the printed circuit pattern 310 , and the conductive pillar 510 penetrates the primer layer 710 ; wherein the primer layer 710 is used to enhance the adhesion of the conductive paste on the first insulating layer 110 .

[0083] In some embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern 310 in the embodiments of the present invention is greater than that of the etched circuit pattern (the first etched circuit pattern 210E and / or the second etched circuit pattern 220E).

[0084] In some embodiments, the printed circuit pattern 310 is laid out at a density smaller than that of the etched circuit pattern (the first etched circuit pattern 210E and / or the second etched circuit pattern 220E) on the insulating layer (the first insulating layer 110 / the second insulating layer 120 ).

[0085] Optionally, the minimum line pitch and / or minimum line width of the etching circuit pattern (the first etching circuit pattern 210E and / or the second etching circuit pattern 220E) may range from 1-100 μm, and the minimum line pitch and / or minimum line width of the printed circuit pattern 310 may range from 2-200 μm.

[0086] Those skilled in the art should understand that although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected to be smaller than the actual parameters of the minimum line spacing and / or minimum line width of the printed circuit pattern according to needs.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a multilayer circuit board, characterized in that: include: preparing a first stack; The first laminate includes: a first insulating layer having a first surface and a second surface vertically opposite to each other, and a first metal foil layer formed on the first surface of the first insulating layer; Opening a first blind hole that penetrates the first insulating layer and reaches the first metal foil layer; Forming a printed circuit pattern on the second surface of the first insulating layer using a conductive paste, and filling the first blind hole to form a conductive column for realizing conductive interconnection between the printed circuit pattern and the first metal foil layer; Electroplating on the printed circuit pattern to form a plated circuit pattern; preparing a second laminate; The second laminate includes: a second insulating layer having a first surface and a second surface vertically opposite to each other, and a second metal foil layer formed on the first surface of the second insulating layer; The second insulating layer of the second laminate is bonded to the plated circuit pattern of the first laminate; A second blind hole is formed which penetrates through the second metal foil layer and the second insulating layer and directly reaches the plated circuit pattern; Performing hole metallization processing on the second blind hole to obtain a metallized hole that realizes conductive interconnection between the second metal foil layer and the plated circuit pattern; The first metal foil layer is etched to form a first etched circuit pattern, and the second metal foil layer is etched to form a second etched circuit pattern.

2. The method according to claim 1, characterized in that: The minimum line width and / or minimum line spacing of the printed circuit pattern is greater than the first etching circuit pattern and / or the second etching circuit pattern; and / or, The laying density of the printed circuit pattern on the insulating layer is smaller than that of the etched circuit pattern.

3. The method according to claim 1, characterized in that: The printed circuit pattern includes: at least two printed circuit units that are not in direct contact, and the printed circuit units are electrically connected to the first metal foil layer through conductive columns.

4. The method according to claim 1, characterized in that: The performing hole metallization processing on the second blind hole specifically includes: A conductive carbon layer electrically connected to the metal foil layer and the second metal foil layer is formed on the hole wall of the second blind hole, and then a plated metal layer is formed on the conductive carbon layer by electroplating.

5. The production method according to claim 1 or 2, characterized in that: The first metal foil layer and / or the second metal foil layer may or may not have surface plating added during the electroplating process.

6. The method according to claim 1, characterized in that: Before the first blind hole is formed through the first insulating layer and directly reaches the first metal foil layer, the method further includes: A primer layer is formed on the second surface of the first insulating layer, and the first blind hole penetrates the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the first insulating layer.

7. The manufacturing method according to claim 1, characterized in that: After etching the first metal foil layer to form a first etching circuit pattern, and etching the second metal foil layer to form a second etching circuit pattern, the method further includes: A covering layer is formed on the first etching circuit pattern and / or the second etching circuit pattern; wherein the covering layer shields a part or the whole of the first etching circuit pattern and / or the second etching circuit pattern.

8. A multilayer circuit board, characterized in that: Obtained by the preparation method described in any one of claims 1-7.

9. A multilayer circuit board, characterized in that: include: A second etched circuit pattern, a second insulating layer, a plated circuit pattern, a printed circuit pattern, a first insulating layer and a second etched circuit pattern are stacked in sequence; wherein the plated circuit pattern is formed on the printed circuit pattern, the printed circuit pattern and the first etched circuit are interconnected via a conductive column penetrating the first insulating layer, and the plated circuit pattern and the second etched circuit are interconnected via a metallized hole penetrating the second insulating layer.

10. The multilayer circuit board according to claim 9, characterized in that: A covering layer is formed on the first etching circuit pattern and / or the second etching circuit pattern; wherein the covering layer shields part or all of the first etching circuit pattern and / or the second etching circuit pattern; and / or, a primer layer is formed between the first insulating layer and the printed circuit pattern, and the conductive column penetrates the primer layer; wherein the primer layer is used to enhance the adhesion of the conductive paste on the first insulating layer.

Images