Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to the technical field of semiconductor technology, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate; a group of memory cells on the substrate, the group of memory cells comprising a plurality of vertically stacked memory cells, each memory cell comprising a transistor and a capacitor, the capacitor extending along a first direction parallel to the substrate; and a first conductive structure on a first side of the group of memory cells, the first conductive structure being arranged along a second direction parallel to the substrate with the group of memory cells, the first conductive structure extending along a third direction perpendicular to the substrate, the first conductive structure being coupled with a plurality of capacitors in the group of memory cells, and the first direction intersecting the second direction. Embodiments of the present disclosure are at least beneficial to reduce the length of the semiconductor structure in the first direction and improve the integration density of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the continuous development of semiconductor structures, their critical dimensions are constantly decreasing. However, due to the limitations of lithography machines, there is a limit to the reduction of these critical dimensions. Therefore, how to create chips with higher storage density on a single wafer is a research direction for many scientific researchers and semiconductor practitioners. In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Therefore, the integration density of two-dimensional or planar semiconductor devices can be determined by the area occupied by each unit memory cell. However, the integration density of two-dimensional or planar semiconductor devices is greatly affected by the technology used to form fine patterns, which means that there is a limit to the continued increase in the integration density of two-dimensional or planar semiconductor devices. Therefore, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, in three-dimensional semiconductor devices, how to arrange more memory cells in a limited layout space remains to be studied. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial in reducing the length of the semiconductor structure in a first direction and improving the integration density of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; a memory cell group located on the substrate, the memory cell group comprising a plurality of vertically stacked memory cells, the memory cells comprising transistors and capacitors, the capacitors extending along a first direction parallel to the substrate; a first conductive structure located on a first side of the memory cell group, the first conductive structure and the memory cell group being arranged along a second direction parallel to the substrate, the first conductive structure extending along a third direction perpendicular to the substrate, the first conductive structure coupled to the plurality of capacitors in the memory cell group, the first direction and the second direction intersecting.

[0006] In some embodiments, a plurality of the memory cell groups and a plurality of the first conductive structures are alternately arranged along the second direction; the first conductive structure is located on a first side of at least one of the memory cell groups, and the memory cell group is in contact with at least one of the first conductive structures.

[0007] In some embodiments, the first conductive structure is plate-shaped, and the first conductive structure extends along the first direction and the third direction.

[0008] In some embodiments, at least one of the first conductive structures is coupled to the capacitors in two memory cell groups located on both sides of the first conductive structure.

[0009] In some embodiments, the second height of the first conductive structure along the third direction is greater than the first height of the memory cell group along the third direction; the semiconductor structure also includes: a first isolation layer, the first isolation layer at least covers the top of the memory cell group, and the first conductive structure is adjacent to the first isolation layer.

[0010] In some embodiments, the capacitor includes a first electrode extending along the first direction; the semiconductor structure further includes a first dielectric layer located between the first conductive structure and the first electrode.

[0011] In some embodiments, the semiconductor structure further includes: a conductive protrusion protruding from the sidewall of the first conductive structure and sandwiched between the first electrodes adjacent to each other along the third direction; and the first dielectric layer is also located between the conductive protrusion and the first electrode.

[0012] In some embodiments, the first electrode is a cup-shaped structure having an opening facing the first direction, and the semiconductor structure further includes: a first conductive portion extending along the first direction, the first conductive portion corresponding to the first electrode one-to-one and embedded in the first electrode through the opening; a second dielectric layer located between the first conductive portion and the first electrode; a second conductive structure located on a second side of the memory cell group and arranged along the first direction with the memory cell group, the second conductive structure extending along the third direction, the second conductive structure being electrically connected to the first conductive portion, and the second dielectric layer being further located on a sidewall of the second conductive structure.

[0013] In some embodiments, the second conductive structure is in contact with and connected to all of the first conductive portions, or a plurality of second conductive structures are arranged at intervals along the second direction, and each second conductive structure is in contact with and connected to a plurality of first conductive portions arranged at intervals along the third direction.

[0014] In some embodiments, the semiconductor structure further includes: a second conductive portion, the second conductive portion extending along the second direction and arranged at intervals along the third direction, the second conductive portion having a third side and a fourth side opposite to each other along the first direction, the third side being in contact and connected with a plurality of the first conductive portions arranged at intervals along the second direction, and the fourth side being in contact and connected with the second conductive structure; the second dielectric layer also covers the side walls of the second conductive portion.

[0015] In some embodiments, the storage cell groups are also arranged at intervals along the first direction, the first conductive parts are also arranged at intervals along the first direction, adjacent first conductive parts along the first direction are in contact and connected with the same second conductive structure, and the two adjacent storage cell groups arranged at intervals along the first direction are mirror-distributed along the second conductive structure.

[0016] In some embodiments, the first electrode is a columnar structure extending along the first direction, and the first dielectric layer covers at least a portion of a sidewall of the first electrode parallel to the first direction.

[0017] In some embodiments, along the third direction, a portion of the height of the first conductive structure is embedded in the substrate.

[0018] In some embodiments, the semiconductor structure further includes: a first electrical connection layer, the first electrical connection layer electrically connecting a plurality of the first conductive structures spaced apart along the second direction, the first electrical connection layer being located above the plurality of the first conductive structures.

[0019] In some embodiments, along the first direction, the first length of the first conductive structure is less than the second length of the first electrode; the semiconductor structure also includes: a second isolation layer, the second isolation layer is located on at least one side of the first conductive structure along the first direction, and the second isolation layer contacts the side wall of the first electrode.

[0020] In some embodiments, the semiconductor structure further includes: a first conductive plug located on the first conductive structure and electrically connected to the first conductive structure; a second conductive plug located on the second conductive structure and electrically connected to the second conductive structure; and a second electrical connection layer located on the first conductive plug and the second conductive plug and electrically connecting the first conductive plug and the second conductive plug.

[0021] In some embodiments, the transistor includes a semiconductor layer extending along the first direction, and the semiconductor layer includes a first surface and a second surface facing each other along the first direction, and the first surface is in contact with the capacitor; the semiconductor structure also includes: a bit line structure, which is in contact with the second surface; and a word line structure, which is located on the side of the semiconductor layer; wherein the word line structure extends along the second direction, and the bit line structure extends along a third direction; or, the word line structure extends along the third direction, and the bit line structure extends along the second direction.

[0022] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a memory cell group on the substrate, the memory cell group comprising a plurality of vertically stacked memory cells, the memory cells comprising transistors and capacitors, the capacitors extending along a first direction parallel to the substrate; forming a first conductive structure located on a first side of the memory cell group, the first conductive structure and the memory cell group being arranged along a second direction parallel to the substrate, the first conductive structure extending along a third direction perpendicular to the substrate, the first conductive structure being coupled to the plurality of capacitors in the memory cell group, the first direction and the second direction intersecting.

[0023] In some embodiments, the storage cell group is formed on the substrate, including: forming a stacked structure on the substrate, the stacked structure including a first sacrificial layer and a second sacrificial layer alternately stacked along the third direction; patterning the second sacrificial layer to form a capacitor groove extending along the first direction, and a plurality of the capacitor grooves are arranged at intervals along at least the second direction; forming the first electrode in the capacitor groove, a plurality of the first electrodes are arranged at intervals along the second direction and the third direction, the first direction and the second direction intersect and are both parallel to the substrate; forming a first dielectric layer, the first dielectric layer being located on a side wall of the first electrode; after forming the first conductive structure, the first conductive structure is in contact with the first dielectric layer.

[0024] In some embodiments, forming the first conductive structure includes: etching the stacked structure to form a first through hole passing through the stacked structure in the third direction, the first through hole being located between the first electrodes adjacent to each other along the second direction; and forming the first conductive structure in the first through hole.

[0025] In some embodiments, the first through hole exposes the side wall of the first electrode and the side wall of the first sacrificial layer, and the manufacturing method further includes: lateral etching along the first through hole to remove the first sacrificial layer exposed by the first through hole and form a connecting groove, wherein the connecting groove is located between the first electrodes adjacent to each other along the third direction, and the connecting groove is connected to two adjacent first through holes along the second direction; the formed first dielectric layer also covers the inner wall of the connecting groove; the step of forming the first conductive structure in the first through hole further includes: forming a conductive protrusion in the connecting groove.

[0026] In some embodiments, the second sacrificial layer is patterned, including: etching the stacked structure to form a second through hole passing through the stacked structure in the third direction, the second through hole exposing the first sacrificial layer and the second sacrificial layer; laterally etching along the second through hole to remove a portion of the second sacrificial layer and form the capacitor groove; forming the first electrode in the capacitor groove, including: forming the first electrode conformally covering the inner wall of the capacitor groove, the first electrode being a cup-shaped structure with an opening facing the first direction; the manufacturing method also includes: forming a second dielectric layer conformally covering at least the inner wall of the first electrode; forming a first conductive portion and a second conductive structure located on the surface of the second dielectric layer, the first conductive portion and the first electrode corresponding one-to-one and embedded in the first electrode through the opening, and the second conductive structure filling the second through hole.

[0027] In some embodiments, multiple first through holes are arranged at intervals along at least the second direction; after forming the first conductive structure in the first through hole, the manufacturing method further includes: forming a first electrical connection layer on the top surface of the multiple first conductive structures, and the first electrical connection layer electrically connects the multiple first conductive structures arranged at intervals along the second direction.

[0028] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0029] A column of memory cells stacked along the third direction constitutes a memory cell group, and multiple memory cell groups are spaced apart along the second direction to form a three-dimensional semiconductor structure. On this basis, a first conductive structure is provided between adjacent memory cell groups along the second direction, and the first conductive structure is coupled to multiple capacitors in at least one memory cell group. It is understandable that a portion of the first conductive structure can serve as a conductive plate in a capacitor, such as an upper electrode in a capacitor, that is, the first conductive structure and the multiple capacitors coupled thereto can form a capacitor structure. Then, the structure for storing data in each memory cell includes a capacitor and a portion of the first conductive structure coupled to the memory cell. This facilitates increasing the capacitance of the capacitor structure for storing data corresponding to each memory cell by providing the first conductive structure, thereby increasing the capacitance of the memory cell group.

[0030] Moreover, on the one hand, the first conductive structure is arranged between adjacent memory cell groups along the second direction, and the length of the semiconductor structure along the first direction will not be increased due to the addition of the first conductive structure. The first conductive structure is located in the isolation layer originally provided to isolate adjacent memory cell groups, and does not occupy additional layout space in the semiconductor structure, which is conducive to reducing the length of the semiconductor structure in the first direction to improve the integration density of the semiconductor structure; on the other hand, the first conductive structure extends along the third direction. It can be understood that the first conductive structure can be prepared along a direction perpendicular to the substrate, that is, the vertical direction. The preparation process is simple, so it is easy to control the dimensional accuracy of the first conductive structure to improve the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic diagram of a partial three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 2a for Figure 1 A schematic diagram of a partial cross-sectional structure of the semiconductor structure shown along a first cross-sectional direction AA1;

[0034] Figure 2b for Figure 1 A schematic diagram of a partial cross-sectional structure of the semiconductor structure shown along a second cross-sectional direction BB1;

[0035] Figure 3a and Figure 3b for Figure 1 Two schematic diagrams of partial cross-sectional structures of the semiconductor structure shown along the third cross-sectional direction CC1;

[0036] Figure 4a and Figure 4b for Figure 1 Two other partial cross-sectional structural schematic diagrams of the semiconductor structure along the third cross-sectional direction CC1 are shown;

[0037] Figure 5a and Figure 5b for Figure 1Two further partial cross-sectional structural schematic diagrams of the semiconductor structure along the third cross-sectional direction CC1 are shown;

[0038] Figure 6 3 to 5 ;

[0039] Figure 7a and Figure 7b Two other partial cross-sectional structural schematic diagrams of the first electrode in the semiconductor structure provided in one embodiment of the present disclosure;

[0040] FIG8 is a schematic diagram of three partial three-dimensional structures of a semiconductor structure provided by an embodiment of the present disclosure;

[0041] Figures 9 to 12 Schematic diagrams of four other partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure along the first cross-sectional direction AA1;

[0042] Figure 13 and Figure 14 Two other partial cross-sectional structural schematic diagrams of the semiconductor structure provided by an embodiment of the present disclosure along the second cross-sectional direction BB1;

[0043] Figure 15 Figure 1 Three schematic diagrams of partial cross-sectional structures of the semiconductor structure shown along the third cross-sectional direction CC1;

[0044] Figure 16 Figure 1 Three other partial cross-sectional structural schematic diagrams of the semiconductor structure along the third cross-sectional direction CC1 are shown;

[0045] FIG17 is a schematic diagram of two other partial cross-sectional structures of the first electrode in the improved semiconductor structure according to an embodiment of the present disclosure;

[0046] Figure 18 A schematic diagram of another partial three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figures 19 to 23 A schematic diagram of the cross-sectional structures corresponding to each step in a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] As known from the background art, the integration density of three-dimensional semiconductor structures needs to be improved.

[0049] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure, a first conductive structure is disposed between adjacent memory cell groups along a second direction, based on the construction of a three-dimensional semiconductor structure. The first conductive structure is coupled to multiple capacitors in at least one memory cell group. The structure for storing data in each memory cell includes a capacitor and a portion of the first conductive structure coupled to the memory cell. This facilitates increasing the capacitance of the data-storing capacitor structure corresponding to each memory cell by disposing the first conductive structure, thereby increasing the capacitance of the memory cell group. Furthermore, since the first conductive structure is disposed between adjacent memory cell groups along the second direction, the length of the semiconductor structure along the first direction is not increased due to the addition of the first conductive structure. Furthermore, the space occupied by the first conductive structure is a portion of the space provided by the isolation layer used to isolate adjacent memory cell groups, eliminating the need for additional layout space within the semiconductor structure. This facilitates reducing the length of the semiconductor structure in the first direction and improving the integration density of the semiconductor structure. Furthermore, since the first conductive structure extends along a third direction, the first conductive structure can be fabricated vertically, resulting in a simple fabrication process and ease of controlling the dimensional accuracy of the first conductive structure, thereby improving the electrical performance of the semiconductor structure.

[0050] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0051] An embodiment of the present disclosure provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings.

[0052] refer to Figure 1 2 , the semiconductor structure includes: a substrate 100; a memory cell group 101 located on the substrate 100, the memory cell group 101 including a plurality of vertically stacked memory cells 111, the memory cell 111 including a transistor 102 and a capacitor 103, the capacitor 103 extending along a first direction X parallel to the substrate 100; a first conductive structure 104 located on a first side a of the memory cell group 101, the first conductive structure 104 and the memory cell group 101 being arranged along a second direction Y parallel to the substrate 100, the first conductive structure 104 extending along a third direction Z perpendicular to the substrate 100, the first conductive structure 104 being coupled to the plurality of capacitors 103 in the memory cell group 101, and the first direction X and the second direction Y intersecting.

[0053] It should be noted that Figure 1A schematic diagram of a partial three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure is shown. Figure 2a for Figure 1 A schematic diagram of a partial cross-sectional structure of the semiconductor structure shown along a first cross-sectional direction AA1; Figure 2b for Figure 1 The semiconductor structure shown is a schematic diagram of a partial cross-sectional structure along the second cross-sectional direction BB1. Figure 1 In order to reflect the three-dimensional morphology of the first conductive structure 104, the same filling method is used for the top surface and the side surface perpendicular to the first direction X of the first conductive structure 104, and different filling methods are used for the side surface perpendicular to the first direction X and the side surface perpendicular to the second direction Y of the first conductive structure 104.

[0054] In some embodiments, referring to FIG. 2 , a first side surface a of the memory cell group 101 is perpendicular to the second direction Y, and the same first side surface a includes side surfaces of a plurality of capacitors 103 arranged along the third direction Z. A memory cell group 101 may have two first side surfaces a disposed opposite each other along the second direction Y. The positional relationship between the first conductive structure 104 and the memory cell group 101 will be described in detail later using various embodiments.

[0055] It should be noted that Figure 1 In FIG, a storage cell group 101 including four storage cells 111 stacked along the third direction Z is used as an example, and in FIG2 a storage cell group 101 including two storage cells 111 stacked along the third direction Z is used as an example. In actual applications, there is no limit on the number of storage cells 111 stacked along the third direction Z included in a storage cell group 101, and the number of vertically stacked storage cells 111 can also be 3, 5, or 8. In addition, Figure 1 In the figure, four storage unit groups 101 are arranged along the second direction Y as an example. In actual applications, there is no limit on the number of storage unit groups 101 arranged along the second direction Y, for example, it can also be 2, 5 or 8.

[0056] It is understood that a column of memory cells 111 stacked along the third direction Z constitutes a memory cell group 101, and multiple memory cell groups 101 are spaced apart along the second direction Y to form a three-dimensional semiconductor structure. On this basis, a first conductive structure 104 is provided between adjacent memory cell groups 101 along the second direction Y, and the first conductive structure 104 is coupled to multiple capacitors 103 in at least one memory cell group 101. It is understood that a portion of the first conductive structure 104 can serve as a conductive plate of the capacitor 103, such as the upper electrode of the capacitor 103, that is, the first conductive structure 104 and the multiple capacitors 103 coupled thereto can form a capacitor structure. Then, the structure for storing data in each memory cell 111 includes the capacitor 103 and a portion of the first conductive structure 104 coupled to the memory cell 111, thereby facilitating the provision of the first conductive structure 104 to increase the capacitance of the capacitor structure for storing data corresponding to each memory cell 111, thereby increasing the capacitance of the memory cell group 101.

[0057] Moreover, on the one hand, the first conductive structure 104 is arranged between the adjacent memory cell groups 101 along the second direction Y, and the length of the semiconductor structure along the first direction X will not be increased due to the addition of the first conductive structure 104, and the space occupied by the first conductive structure 104 is part of the space of the isolation layer set to isolate the adjacent memory cell groups 101, which is beneficial to reducing the length of the semiconductor structure in the first direction X to improve the integration density of the semiconductor structure; on the other hand, the first conductive structure 104 extends along the third direction Z. It can be understood that the first conductive structure 104 can be prepared in a direction perpendicular to the substrate 100, that is, in the vertical direction. The preparation process is simple, so it is easy to control the dimensional accuracy of the first conductive structure 104 to improve the electrical performance of the semiconductor structure.

[0058] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0059] In some embodiments, in conjunction with reference Figure 1 2 , the transistor 102 includes a semiconductor layer 112 extending along a first direction X, and the semiconductor layer 112 includes a first surface e and a second surface f facing each other along the first direction X, and the first surface e is in contact with the capacitor 103 ; the semiconductor structure may further include: a bit line structure 108 , which is in contact with the second surface f; and a word line structure 109 , which is located on the side of the semiconductor layer 112 .

[0060] In some embodiments, reference Figure 1, the word line structure 109 extends along the second direction Y, and the bit line structure 108 extends along the third direction Z, one word line structure 109 surrounds the multiple semiconductor layers 112 spaced apart along the second direction Y, and one bit line structure 108 is in contact with and connected to the second surfaces f of the multiple semiconductor layers 112 spaced apart along the third direction Z; in other embodiments, the word line structure extends along the third direction, the bit line structure extends along the second direction, one word line structure covers at least one side surface of each of the multiple semiconductor layers spaced apart along the third direction to form a single-sided gate, a double-sided gate, or a full-ring gate, and one bit line structure is in contact with and connected to the second surfaces of the multiple semiconductor layers spaced apart along the second direction. It should be noted that Figure 1 FIG. 1 is a schematic diagram showing a positional relationship among the word line structure 109 , the bit line structure 108 , the semiconductor layer 112 and the capacitor 103 .

[0061] It can be understood that the wordline structure 109 is used to control the transistors 102. A wordline structure 109 has multiple portions corresponding to the multiple semiconductor layers 112. Each portion of the wordline structure 109 surrounds a semiconductor layer 112. In addition to the semiconductor layer 112, the transistor 102 may also include a portion of the wordline structure 109 surrounding the semiconductor layer 112. In other words, a transistor 102 includes only a portion of the wordline structure 109, and a single wordline structure 109 is coupled to the semiconductor layers 112 of multiple transistors 102. Thus, if multiple transistors 102 each include a portion of the wordline structure 109, a single wordline structure 109 can control multiple transistors 102 arranged along the second direction Y or the third direction Z. This helps improve the integration density of the transistors 102, bitline structure 108, wordline structure 109, and capacitor 103 in the semiconductor structure while reducing the complexity of controlling multiple devices in the semiconductor structure.

[0062] In some embodiments, the portion of the semiconductor layer 112 that is in contact with the capacitor 103 includes metal silicide. Metal silicide has a relatively small resistivity compared to unmetallized semiconductor materials. Therefore, compared with the semiconductor layer 112 that does not include metal silicide, the semiconductor layer 112 including metal silicide has a smaller resistivity, which is beneficial to reducing the resistance of the semiconductor layer 112. The semiconductor layer 112 including metal silicide is in contact with the capacitor 103, which is beneficial to reducing the contact resistance between the semiconductor layer 112 and the capacitor 103, thereby further improving the electrical performance of the storage unit 111.

[0063] In some embodiments, the metal silicide includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0064] In some embodiments, reference Figure 1The wordline structure 109 may include a gate dielectric layer 119 and a gate conductive layer 129. The gate dielectric layer 119 surrounds a portion of the sidewall of the semiconductor layer 112 extending along the first direction X, and the gate conductive layer 129 surrounds the sidewall of the gate dielectric layer 119 extending along the first direction X away from the semiconductor layer 112. The gate conductive layer 129 extends along the second direction Y, such that a gate conductive layer 129 is in contact with a plurality of gate dielectric layers 119 arranged at intervals along the second direction Y. It will be understood that, along the first direction X, the semiconductor layer 112 surrounded by the gate dielectric layer 119 may serve as a channel region in the transistor 102, and the gate conductive layer 129 is used to control whether the channel region is turned on or off.

[0065] In some embodiments, the gate conductive layer 129 may be made of at least one conductive material such as titanium nitride, tungsten, or cobalt, and the gate dielectric layer 119 may be made of at least one insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0066] In some embodiments, referring to Figures 2 to 5, and Figures 15 and 16, multiple memory cell groups 101 and multiple first conductive structures 104 are alternately arranged along a second direction Y; the first conductive structure 104 is located on a first side surface a of at least one memory cell group 101, and the memory cell group 101 is in contact with at least one first conductive structure 104. Thus, the positional relationship between the first conductive structure 104 and the memory cell group 101 can be configured in a variety of ways. While ensuring that the structure for storing data in each memory cell 111 includes the capacitor 103 and a portion of the first conductive structure 104 coupled to the memory cell 111, by adjusting the positional relationship between the first conductive structure 104 and the memory cell group 101, the area of ​​the first conductive structure 104 coupled to any capacitor 103 can be controlled, thereby controlling the capacitance of the capacitor structure for storing data in each memory cell 111.

[0067] It should be noted that Figure 3a and Figure 3b for Figure 1 Two schematic diagrams of partial cross-sectional structures of the semiconductor structure shown along the third cross-sectional direction CC1; Figure 4a and Figure 4b for Figure 1 Two other partial cross-sectional structural schematic diagrams of the semiconductor structure along the third cross-sectional direction CC1 are shown; Figure 5a and Figure 5b for Figure 1 3 to 5 illustrate a portion of the semiconductor layer 112 in the transistor 102 for simplicity of illustration to illustrate the electrical connection between the capacitor 103 and the transistor 102 .

[0068] The positional relationship between the first conductive structure 104 and the memory cell group 101 is described in detail below.

[0069] In some embodiments, referring to FIG. 3 and FIG. Figure 4a The first conductive structure 104 may be plate-shaped, and the first conductive structure 104 extends along the first direction X and the third direction Z. It is understood that the first conductive structure 104 being plate-shaped means that the length of the first conductive structure 104 in the first direction X is much greater than the width of the first conductive structure 104 in the second direction Y. For example, the ratio of the length of the first conductive structure 104 in the first direction X to the width of the first conductive structure 104 in the second direction Y is greater than 2, so that the first conductive structure 104 presents a plate-shaped structure perpendicular to the second direction Y.

[0070] The following Figure 3a 、 Figure 3b and Figure 4a The corresponding semiconductor structures are described in detail respectively.

[0071] In some examples, reference Figure 3a , a first conductive structure 104 is coupled to the capacitors 103 in the two memory cell groups 101 (see FIG2 ) located on either side of the first conductive structure 104, and only one first conductive structure 104 is provided between two adjacent memory cell groups 101 along the second direction Y. In other words, for a first conductive structure 104, its two opposite side surfaces in the second direction Y are in contact with the two first side surfaces a of the two memory cell groups 101, respectively, i.e., the same first conductive structure 104 is shared by the two memory cell groups 101 coupled thereto. In this way, the structure for storing data in each memory cell 111 includes a capacitor 103 and two first conductive structures 104 coupled to the capacitor 103, thereby further increasing the capacitance of the capacitor structure for storing data corresponding to each memory cell 111, thereby improving the data storage capability of the memory cell 111 and thereby improving the electrical performance of the memory cell group 101.

[0072] In other examples, reference Figure 3b , the first conductive structures 104 and the memory cell groups 101 (refer to FIG2 ) correspond one to one, that is, any first conductive structure 104 is coupled only to one first side surface a of a memory cell group 101, the other first side surface a of the memory cell group 101 is in contact with and connected to the second isolation layer 115, and only one first conductive structure 104 is provided in the interval between two adjacent memory cell groups 101 along the second direction Y.

[0073] In some other examples, reference Figure 4a, any first conductive structure 104 is coupled to only one first side surface a of a memory cell group 101 (refer to FIG2 ), and for a memory cell group 101, its two first side surfaces a opposite to each other in the second direction Y are respectively coupled to two first conductive structures 104. In other words, two first conductive structures 104 are provided in the gap between two adjacent memory cell groups 101 in the second direction Y, and the two first conductive structures 104 are arranged at intervals along the second direction Y. In this way, it is beneficial to further increase the capacitance of the capacitor structure for storing data corresponding to each memory cell 111, and reduce the layout area occupied by any first conductive structure 104 in the semiconductor structure. Moreover, under the premise of increasing the capacitance of the capacitor structure for storing data corresponding to each memory cell 111, the width of any first conductive structure 104 in the second direction Y is reduced, which is beneficial to reduce the material cost of preparing the first conductive structure 104.

[0074] In other embodiments, referring to FIG. Figure 4b , the first conductive structure 104 can be columnar. It is understood that the columnar shape of the first conductive structure 104 means that the length of the first conductive structure 104 in the first direction X and the width of the first conductive structure 104 in the second direction Y are substantially equal, such that the first conductive structure 104 presents a columnar structure perpendicular to the second direction Y. In other words, with the plane defined by the first direction X and the second direction Y as a reference plane, the orthographic projection or cross-sectional shape of the first conductive structure 104 on the reference plane is a rectangle, and the aspect ratio of the rectangle is close to 1, for example, a ratio of 0.9 to 1.1.

[0075] It should be noted that Figure 4b Take as an example any first conductive structure 104 as a columnar structure and the capacitors 103 in two memory cell groups 101 (see FIG. 2 ) located on both sides of the first conductive structure 104 as coupling. In practical applications, any first conductive structure as a columnar structure can also be as follows: Figure 3b The positional relationship between the first conductive structure 104 and the memory cell group 101 is the same, that is, any first conductive structure as a columnar structure is only coupled to one first side surface of a memory cell group, and the other first side surface of the memory cell group is in contact with the second isolation layer; alternatively, any first conductive structure as a columnar structure may also be as shown. Figure 4a The positional relationship between the illustrated first conductive structure 104 and the storage cell group 101 is the same, that is, any first conductive structure as a columnar structure is only coupled with one first side surface of a storage cell group, and for a storage cell group, its two first sides opposite to each other in the second direction are respectively coupled with two first conductive structures.

[0076] also, Figure 4bTake, for example, two first conductive structures 104 as columnar structures disposed in the interval between two adjacent memory cell groups 101 along the second direction Y, and the two first conductive structures 104 are spaced apart along the first direction X. In practical applications, for any interval between two adjacent memory cell groups 101, there is no limit on the number of first conductive structures 104 disposed in the interval and spaced apart along the first direction X, and for example, the number may be 3, 4, or 7.

[0077] In some other embodiments, referring to FIG5 , the first conductive structure 104 may be annular. It is understood that, with the plane defined by the first direction X and the second direction Y as a reference plane, the annular shape of the first conductive structure 104 means that the orthographic projection shape or cross-sectional shape of the first conductive structure 104 on the reference plane is annular.

[0078] In some embodiments, referring to FIG. 5 , the capacitor 103 may include a first electrode 113 extending along a first direction X. The semiconductor structure may further include a first dielectric layer 123 located between the first conductive structure 104 and the first electrode 113 .

[0079] The following Figure 5a and Figure 5b The corresponding semiconductor structures are described in detail respectively.

[0080] In some examples, reference Figure 5a The annular first conductive structure 104 has an outer wall 104a and an inner wall 104b oppositely disposed, as well as a bottom surface (not shown in FIG5 ) connecting the outer wall 104a and the inner wall 104b. The first dielectric layer 123 covers the outer wall 104a, the inner wall 104b, and the bottom surface of the first conductive structure 104. In other words, the second isolation layer 115 has an annular groove for accommodating the first conductive structure 104 and the first dielectric layer 123. The first dielectric layer 123 conformally covers the inner wall of the annular groove, and the first conductive structure 104 fills the remaining portion of the annular groove.

[0081] In other examples, reference Figure 5bThe annular first conductive structure 104 has an outer wall 104a and an inner wall 104b disposed opposite each other, as well as a bottom surface (not shown in FIG5 ) connecting the outer wall 104a and the inner wall 104b. The first dielectric layer 123 covers the outer wall 104a and the bottom surface of the first conductive structure 104. The fourth isolation layer 135 is located in the groove formed by the inner wall 104b of the first conductive structure 104. In other words, the second isolation layer 115 has a groove for accommodating the first conductive structure 104, the first dielectric layer 123, and the fourth isolation layer 135. The groove has a rectangular shape when projected onto the substrate 100. The first dielectric layer 123 and the first conductive structure 104 sequentially conformally cover the inner wall of the groove, and the fourth isolation layer 135 fills the remaining portion of the groove.

[0082] In the above embodiment, reference Figure 3a 、 Figure 4b 5, at least one first conductive structure 104 is coupled to the capacitors 103 in the two memory cell groups 101 located on both sides of the first conductive structure 104. This is beneficial to further improve the connection between each memory cell 111 (refer to Figure 1 ) corresponding to the capacitance of the capacitor structure for storing data, so as to improve the data storage capability of the memory cell 111, thereby improving the memory cell group 101 (reference Figure 1 )'s electrical properties.

[0083] In the above embodiment, referring to FIG. 3 to FIG. 5 , the capacitor 103 may include a first electrode 113 extending along the first direction X; the semiconductor structure may further include a first dielectric layer 123 located between the first conductive structure 104 and the first electrode 113 .

[0084] It can be understood that, in some examples, referring to Figures 3 and 4, when the first conductive structure 104 is a solid plate-like structure or a columnar structure, on the premise that the first dielectric layer 123 is located between the first conductive structure 104 and the first electrode 113, the first dielectric layer 123 at least surrounds the four side walls of the first conductive structure 104 extending along the third direction Z; in other examples, referring to Figure 5, when the first conductive structure 104 is a hollow plate-like structure or a columnar structure, that is, the first conductive structure 104 is annular, on the premise that the first dielectric layer 123 is located between the first conductive structure 104 and the first electrode 113, the first dielectric layer 123 at least surrounds the outer wall 104a of the first conductive structure 104 extending along the third direction Z.

[0085] It should be noted that the first dielectric layer 123 is used to achieve electrical insulation between the first electrode 113 and the first conductive structure 104. In an embodiment of the present disclosure, it is only necessary that the first dielectric layer 123 is located between the first conductive structure 104 and the first electrode 113. An embodiment of the present disclosure includes but is not limited to the embodiments of the positional relationship between the first dielectric layer 123, the first conductive structure 104 and the first electrode 113 shown in Figures 3 to 5.

[0086] In addition, in addition to the first electrode 113, the capacitor 103 may also include a first dielectric layer 123 that is in contact with the first electrode 113, that is, a capacitor 103 includes a first electrode 113 and a portion of the first dielectric layer 123, and the portion of the first dielectric layer 123 is in contact with the first electrode 113.

[0087] It can be understood that in the examples shown in Figures 3 to 5, the first dielectric layer 123 extends along the third direction X like the first conductive structure 104 in contact with it, that is, the same first dielectric layer 123 corresponds to a plurality of capacitors 103 arranged along the third direction Z, and each capacitor 103 only includes a portion of the first dielectric layer 123.

[0088] It should be noted that FIG3 to FIG5 illustrate top views of the capacitor 103 . It is understandable that the top view of the memory cell group 101 (see FIG2 ) to which the capacitor 103 belongs overlaps with the top view of the capacitor 103 .

[0089] In some embodiments, reference Figure 6 , Figure 6 3 to 5 are partial cross-sectional views of the first electrode 113 in the semiconductor structure. The first electrode 113 may be a cup-shaped structure having an opening 133 facing the first direction X. Figure 6 The semiconductor structure may further include: a first conductive portion 143 extending along the first direction X, the first conductive portion 143 corresponding to the first electrode 113 one-to-one and embedded in the first electrode 113 through the opening 133; a second dielectric layer 153, located between the first conductive portion 143 and the first electrode 113; a second conductive structure 163, located on the second side b of the memory cell group 101 and arranged along the first direction X with the memory cell group 101, the second conductive structure 163 extends along the third direction Z, the second conductive structure 163 is electrically connected to the first conductive portion 143, and the second dielectric layer 153 is also located on the sidewall of the second conductive structure 163.

[0090] It is understandable that the first electrode 113 itself forms a groove 183 with an opening 133. In the cross section perpendicular to the first direction X, the cross section of the first electrode 113 is annular, which can be a circular ring, a square ring or other polygonal ring.

[0091] Furthermore, given that the first conductive structure 104 coupled to the capacitor 103 is already provided, i.e., the capacitance of the capacitor structure for storing data corresponding to each memory cell 111 is guaranteed, the first electrode 113 is designed to be a cup-shaped structure having an opening 133 facing the first direction X, so that the first conductive portion 143 and the second conductive structure 163 can be further provided within the limited layout space. It will be appreciated that the entire structure formed by the first conductive portion 143 and the second conductive structure 163 can serve as the upper electrode of the capacitor structure in the memory cell 111. This facilitates further increasing the capacitance of the capacitor structure for storing data corresponding to each memory cell 111 by adding the first conductive portion 143 and the second conductive structure 163 without reducing the integration density of the semiconductor structure.

[0092] Moreover, since the first conductive structure 104 can serve as the upper electrode of the capacitor structure in the storage unit 111, the first conductive portion 143 and the second conductive structure 163 as a whole can also serve as the upper electrode of the capacitor structure in the storage unit 111. Therefore, when the capacitance of the capacitor structure in the storage unit 111 is constant, the length of the first electrode 113 in the first direction X of the semiconductor structure provided in an embodiment of the present disclosure can be reduced, thereby facilitating the reduction of the length of the semiconductor structure as a whole in the first direction X, so as to improve the integration density of the semiconductor structure; further, the reduction of the length of the first electrode 113 in the first direction X is conducive to forming a second dielectric layer 153 and a first conductive portion 143 with higher dimensional accuracy in the groove surrounded by the first electrode 113, so as to improve the electrical performance of the semiconductor structure.

[0093] In some embodiments, referring to FIG. 3 to FIG. 5 , the second side b of the memory cell group 101 is perpendicular to the first direction X, and the same second side b includes side surfaces of a plurality of capacitors 103 arranged along the third direction Z. It is understood that the second conductive structure 163 is located on a side of the capacitor 103 away from the semiconductor layer 112 .

[0094] It should be noted that the second dielectric layer 153 is used to achieve electrical insulation between the first electrode 113 and the first conductive portion 143, as well as to achieve electrical insulation between the first electrode 113 and the second conductive structure 163. In one embodiment of the present disclosure, it is only necessary that the second dielectric layer 153 is located between the first conductive portion 143 and the first electrode 113, and between the second conductive structure 163 and the first electrode 113. An embodiment of the present disclosure includes but is not limited to the embodiments of the positional relationship between the second dielectric layer 153, the second conductive structure 163 and the first electrode 113 shown in Figures 3 to 5.

[0095] On the basis that the first electrode 113 may be a cup-shaped structure with an opening 133 facing the first direction X, the following is combined Figure 6 7 and 8 illustrate the morphology of the first electrode 113 in detail.

[0096] In some embodiments, reference Figure 6 The inner wall of the groove 183 with the opening 133 formed by the first electrode 113 itself is flat.

[0097] In other embodiments, reference Figure 7a The inner wall of the groove 183 formed by the first electrode 113 itself has a stepped morphology. The first electrode 113 can be regarded as a film layer conformally covering the inner wall of the groove 183. That is, the first electrode 113 itself also has a stepped morphology, and along the first direction X, the cross-sectional area of ​​the groove 183 perpendicular to the first direction X increases. In other embodiments, the first electrode 113 itself has a stepped morphology, and along the first direction X, the cross-sectional area of ​​the groove 183 perpendicular to the first direction X decreases.

[0098] In some other embodiments, reference Figure 7b The groove 183 formed by the first electrode 113 itself includes a first sub-groove 183a and a second sub-groove 183b alternately stacked along the first direction X, and the positive projection area of ​​the first sub-groove 183a on the substrate 100 is larger than the positive projection area of ​​the second sub-groove 183b on the substrate 100, that is, the inner wall of the groove 183 formed by the first electrode 113 itself has an uneven morphology.

[0099] It is understandable that Figure 7a and Figure 7b FIG7 is a schematic diagram of two other partial cross-sectional structures of the first electrode in the semiconductor structure provided in an embodiment of the present disclosure. Two examples of uneven surface morphologies of the first electrode 113 are shown. Referring to FIG7 and FIG5 , on the basis of the first electrode 113 presenting the morphology shown in FIG7 , the first dielectric layer 123 and the first conductive structure 104 sequentially conformally cover at least a portion of the outer wall of the first electrode 113 extending along the first direction X, that is, the sidewall of the first conductive structure 104 facing the memory cell group 101 is non-planar and has a stepped or sawtooth morphology in the first direction X. In this way, it is beneficial to increase the facing area between the first electrode 113 and the first conductive structure 104. It can be understood that the first electrode 113 can serve as the lower electrode of the capacitor structure in the memory cell 111, and the first conductive structure 104 can serve as the upper electrode of the capacitor structure in the memory cell 111. In this way, it is beneficial to further increase the capacitance of the capacitor structure for storing data corresponding to each memory cell 111 by increasing the facing area between the first electrode 113 and the first conductive structure 104.

[0100] In addition, referring to FIG7 and FIG5 , on the basis that the first electrode 113 presents the morphology shown in FIG7 , the second dielectric layer 153 conformally covers the inner wall of the groove 183 surrounded by the first electrode 113, and the first conductive portion 143 fills the remaining portion of the groove 183. This helps to increase the area facing each other between the first electrode 113 and the first conductive portion 143. It can be understood that the first electrode 113 can serve as the lower electrode of the capacitor structure in the memory cell 111, and the first conductive portion 143 can also serve as the upper electrode of the capacitor structure in the memory cell 111. This helps to further increase the capacitance of the capacitor structure for storing data corresponding to each memory cell 111 by increasing the area facing each other between the first electrode 113 and the first conductive portion 143.

[0101] It should be noted that examples of uneven surface morphology of the first electrode 113 include but are not limited to the two embodiments shown in FIG7 . Figure 6 7 is a schematic diagram of the cross-sectional structure of the first electrode 113 along the third cross-sectional direction CC1. In practical applications, the schematic diagram of the cross-sectional structure of the first electrode 113 along the first cross-sectional direction AA1 may also be as shown in FIG. Figure 6 and as shown in Figure 7.

[0102] The corresponding relationship between the second conductive structure 163 and the first conductive portion 143 is described in detail below with reference to FIG8 . FIG8 is a schematic diagram of three partial three-dimensional structures of a semiconductor structure provided by an embodiment of the present disclosure.

[0103] In some embodiments, reference Figure 8a , a plurality of second conductive structures 163 are arranged at intervals along the second direction Y, and each second conductive structure 163 is in contact with a plurality of first conductive portions 143 arranged at intervals along the third direction Z. It can be understood that the second conductive structure 163 and the memory cell group 101 (refer to Figure 1 ) one-to-one correspondence, that is, part of the storage unit 111 (reference Figure 1 ) share the same second conductive structure 163.

[0104] It should be noted that the second conductive structure 163 and the plurality of first conductive portions 143 in contact with it can be an integrally formed structure, that is, the second conductive structure 163 and the plurality of first conductive portions 143 in contact with it can be formed by the same manufacturing process. In addition, in order to clearly illustrate the corresponding relationship between the second conductive structure 163 and the first conductive portion 143, Figure 8a The second conductive structure 163 and the first conductive portion 143 are drawn using different filling methods.

[0105] In other embodiments, reference Figure 8b, the second conductive structure 163 is in contact with all the first conductive portions 143. It can be understood that all the memory cell groups 101 (refer to Figure 1 ) share a second conductive structure 163.

[0106] It should be noted that the second conductive structure 163 and all the first conductive parts 143 can be an integrally formed structure, that is, the second conductive structure 163 and all the first conductive parts 143 can be formed by the same preparation process. In addition, in order to clearly illustrate the corresponding relationship between the second conductive structure 163 and the first conductive part 143, Figure 8b The second conductive structure 163 and the first conductive portion 143 are also drawn using different filling methods.

[0107] In some other embodiments, reference Figure 8c 、 Figure 11 and Figure 12 The semiconductor structure may further include: a second conductive portion 173, the second conductive portion 173 extending along the second direction Y and arranged at intervals along the third direction Z, the second conductive portion 173 having a third side surface c and a fourth side surface d opposite to each other along the first direction X, the third side surface c being in contact with and connected to the plurality of first conductive portions 143 arranged at intervals along the second direction Y, and the fourth side surface d being in contact with and connected to the second conductive structure 163. It should be noted that Figure 8c The second conductive structure 163 is drawn in a perspective manner to clearly illustrate the corresponding relationship between the first conductive portion 143 , the second conductive portion 173 and the second conductive structure 163 .

[0108] It should be noted that the first conductive portion 143, the second conductive portion 173 and the second conductive structure 163 can be an integrally formed structure, that is, the first conductive portion 143, the second conductive portion 173 and the second conductive structure 163 can be formed by the same preparation process. In addition, in order to clearly illustrate the corresponding relationship between the first conductive portion 143, the second conductive portion 173 and the second conductive structure 163, Figure 8c The first conductive portion 143 , the second conductive portion 173 and the second conductive structure 163 are drawn using different filling methods.

[0109] In addition, for clarity of illustration, Figures 8a to 8c Only one row of first conductive portions 143 spaced apart along the second direction Y is shown. In an actual semiconductor structure, the first conductive portions 143 shown in FIG8 may be arranged in multiple rows along the third direction Z. The disclosed embodiments do not restrict the spacing of first conductive portions 143 along the second direction Y or along the third direction Z, and adjustments can be made based on actual needs. Furthermore, the number of second conductive portions 173 spaced apart along the third direction Z is consistent with the number of first conductive portions 143 spaced apart along the third direction Z in any memory cell group 101.

[0110] In some embodiments, reference Figure 11 or Figure 12 , the second dielectric layer 153 also covers the sidewalls of the second conductive portion 173. It is understandable that the second dielectric layer 153 is also used to achieve electrical insulation between the first electrode 113 and the second conductive portion 173. In one embodiment of the present disclosure, it is only necessary to satisfy that the second dielectric layer 153 is located between the second conductive portion 173 and the first electrode 113. One embodiment of the present disclosure includes but is not limited to Figure 11 and Figure 12 FIG. 1 shows an embodiment of the positional relationship among the second dielectric layer 153 , the second conductive portion 173 and the first electrode 113 .

[0111] In some embodiments, reference Figure 9 and Figure 10 The storage cell groups 101 can also be arranged at intervals along the first direction X, and the first conductive portions 143 are also arranged at intervals along the first direction X. The adjacent first conductive portions 143 along the first direction X are in contact and connected with the same second conductive structure 163, and the two adjacent storage cell groups 101 arranged at intervals along the first direction X are mirror-distributed along the second conductive structure 163.

[0112] It should be noted that Figures 9 to 12 Schematic diagrams of four other partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure along the first cross-sectional direction AA1; Figure 13 and Figure 14 Schematic diagrams of two other partial cross-sectional structures of the semiconductor structure provided by an embodiment of the present disclosure along the second cross-sectional direction BB1.

[0113] It can be understood that, along the first direction X, the second conductive structure 163 has a relative fifth side g and a sixth side h, and the first conductive portion 143 corresponding to one of the two adjacent storage cell groups 101 arranged at intervals along the first direction X is in contact with the fifth side g, and the first conductive portion 143 corresponding to the other storage cell group 101 is in contact with the sixth side h, that is, the two adjacent storage cell groups 101 arranged at intervals along the first direction X share a second conductive structure 163, which is beneficial to further improve the integration density of the semiconductor structure.

[0114] It should be noted that the second conductive structure 163, the plurality of first conductive portions 143 in contact with the fifth side surface g, and the plurality of first conductive portions 143 in contact with the sixth side surface h may be an integrally formed structure. Figure 9 In the figure, the first conductive portions 143 corresponding to different memory cell groups 101 are drawn using the same filling method. Figure 9 and Figure 10As shown, the second conductive structure 163, the multiple first conductive portions 143 in contact with the fifth side surface g, and the multiple first conductive portions 143 in contact with the sixth side surface h can be regarded as the upper electrodes of the capacitor structure, and the upper electrodes can correspond to the multiple first electrodes 113. In addition, Figure 9 The approximate range of the storage unit group 101 is indicated by a dotted box.

[0115] It is understandable that Figure 9 and Figure 10 That is, Figure 8a The schematic diagram of the partial cross-sectional structure of the semiconductor structure shown in FIG. 1 along the first cross-sectional direction AA1 can also be Figure 8b The shown schematic diagram is a partial cross-sectional structure of the semiconductor structure along the first cross-sectional direction AA1.

[0116] In other embodiments, reference Figure 11 and Figure 12 On the basis that the semiconductor structure also includes the second conductive portion 173, the memory cell groups 101 can also be arranged at intervals along the first direction X, the first conductive portions 143 are also arranged at intervals along the first direction X, and the second conductive portions 173 are also arranged at intervals along the first direction X. Adjacent second conductive portions 173 along the first direction X are in contact and connected with the same second conductive structure 163, and two adjacent memory cell groups 101 arranged at intervals along the first direction X are distributed in a mirror image along the second conductive structure 163. Adjacent second conductive portions 173y arranged at intervals along the first direction X are also distributed in a mirror image along the second conductive structure 163.

[0117] In some embodiments, reference Figure 10 、 Figure 12 and Figure 13 The semiconductor structure may further include: a conductive protrusion 114 protruding from the sidewall of the first conductive structure 104 and sandwiched between adjacent first electrodes 113 along the third direction Z; and a first dielectric layer 123 is also located between the conductive protrusion 114 and the first electrode 113.

[0118] In some embodiments, the conductive protrusion 114 and the first conductive structure 104 may be an integrally formed structure. Figure 10 、 Figure 12 and Figure 13 The filling method of the conductive protrusion 114 and Figure 13 The filling method for the first conductive structure 104 is the same.

[0119] Understandably, the reference Figure 13Except for the row of first electrodes 113 that are farthest from the substrate 100 and arranged along the second direction Y, the four sidewalls of the other first electrodes 113 that extend along the first direction X are surrounded by the conductive protrusions 114 and the first conductive structures 104. In some embodiments, the top of the row of first electrodes 113 that are farthest from the substrate 100 and arranged along the second direction Y is covered with a first isolation layer 105.

[0120] It should be noted that Figure 13 The conductive protrusion 114 and the first conductive structure 104 are distinguished by a dotted line. Figure 1 and Figure 13 , multiple first electrodes 113 arranged at intervals along the third direction Z all belong to one storage cell group 101, the conductive protrusion 114 is located in the interval between two adjacent first electrodes 113 along the third direction Z in any storage cell group 101, and the first conductive structure 104 is located in the interval between two adjacent storage cell groups 101.

[0121] It can be understood that the first electrode 113 can serve as the lower electrode of the capacitor structure in the storage unit 111, and the conductive protrusion 114 and the first conductive structure 104 as a whole can also serve as the upper electrode of the capacitor structure in the storage unit 111. In this way, it is beneficial to increase the facing area between the first electrode 113 and the upper electrode of the capacitor structure by adding the conductive protrusion 114, so as to further increase the capacitance of the capacitor structure for storing data corresponding to each storage unit 111.

[0122] In some embodiments, the first electrode 113 serves as the lower electrode of the capacitor structure in the storage cell 111, the conductive protrusion 114 and the first conductive structure 104 as a whole serve as the first upper electrode of the capacitor structure in the storage cell 111, the first conductive portion 143 and the second conductive structure 163 as a whole serve as the second upper electrode of the capacitor structure in the storage cell 111, or the first conductive portion 143, the second conductive portion 173 and the second conductive structure 163 as a whole serve as the second upper electrode of the capacitor structure in the storage cell 111. In this way, it is beneficial to configure two upper electrodes for each storage cell 111 to further increase the capacitance of the capacitor structure for storing data corresponding to each storage cell 111.

[0123] In other embodiments, reference Figure 9 、 Figure 11 and Figure 14 The semiconductor structure may also not include the conductive protrusion 114 , and the intervals between adjacent first electrodes 113 along the third direction Z are filled with the second isolation layer 115 .

[0124] In some embodiments, reference Figure 13 or Figure 14, a second height H2 of the first conductive structure 104 along the third direction Z is greater than a first height H1 of the memory cell group 101 along the third direction Z; the semiconductor structure may further include: a first isolation layer 105, the first isolation layer 105 at least covers the top of the memory cell group 101, and the first conductive structure 104 is adjacent to the first isolation layer 105.

[0125] It can be understood that the first isolation layer 105 can be used to achieve insulation between the first electrode 113 and other conductive structures in the semiconductor structure, and setting the first conductive structure 104 on the layer to which the first isolation layer 105 belongs is conducive to subsequent control of the potential of the first conductive structure 104.

[0126] It should be noted that in the above embodiments, the first electrode 113 is a cup-shaped structure having an opening 133 facing the first direction X, so that the semiconductor structure also includes a first conductive portion 143 and a second conductive structure 163. Another form of the first electrode 113 will be described in detail later.

[0127] In other embodiments, referring to Figures 15 to 17 , the first electrode 113 is a columnar structure extending along the first direction X, and the first dielectric layer 123 covers at least a portion of the sidewalls of the first electrode 113 parallel to the first direction X. It will be understood that the first electrode 113 shown in Figures 15 to 17 is a solid structure, that is, the first electrode 113 itself does not form a groove.

[0128] It should be noted that Figure 15a 、 Figure 15b and 15c for Figure 1 Three schematic diagrams of partial cross-sectional structures of the semiconductor structure shown along the third cross-sectional direction CC1; Figure 16a 、 Figure 16b and 16c for Figure 1 Three other partial cross-sectional structural schematic diagrams of the semiconductor structure along the third cross-sectional direction CC1 are shown; Figure 17a and Figure 17b Two additional partial cross-sectional structural diagrams of the first electrode in the improved semiconductor structure according to one embodiment of the present disclosure are provided. Furthermore, for simplicity of illustration, FIG15 and FIG16 illustrate a portion of the semiconductor layer 112 in the transistor 102 to illustrate the electrical connection between the capacitor 103 and the transistor 102.

[0129] It is understood that the cross-sectional shape of the first electrode 113 along the cross section perpendicular to the first direction X can be circular, rectangular, or other deformable shapes. The following detailed description is given by taking the cross-sectional shape of the first electrode 113 along the cross section perpendicular to the first direction X as an example.

[0130] In some embodiments, referring to FIG15 , the first dielectric layer 123 surrounds at least four sidewalls of the first electrode 113 extending along the first direction X. In other embodiments, still referring to FIG15 , the first dielectric layer 123 , in addition to surrounding the four sidewalls of the first electrode 113 extending along the first direction X, may further cover a side of the first electrode 113 away from the semiconductor layer 112 .

[0131] In some other embodiments, referring to FIG. 16 , the first dielectric layer 123 may surround four sidewalls of the first conductive structure 104 extending along the third direction Z.

[0132] It should be noted that the first dielectric layer 123 is used to achieve electrical insulation between the first electrode 113 and the first conductive structure 104. In an embodiment of the present disclosure, it is only necessary that the first dielectric layer 123 is located between the first conductive structure 104 and the first electrode 113. An embodiment of the present disclosure includes but is not limited to the embodiments of the positional relationship between the first dielectric layer 123, the first conductive structure 104 and the first electrode 113 shown in Figures 15 and 16.

[0133] The corresponding relationship among the first electrode 113 , the first conductive structure 104 and the first dielectric layer 123 will be described in detail below with reference to FIG. 15 and FIG. 16 , and parts identical or corresponding to those in the previous embodiment will not be repeated here.

[0134] In some embodiments, referring to FIG. 15 , any first conductive structure 104 is coupled to capacitors 103 in two memory cell groups 101 (see FIG. 2 ) located on both sides of the first conductive structure 104 .

[0135] In some examples, reference Figure 15a The first conductive structure 104 is plate-shaped, and only one first conductive structure 104 is provided between two adjacent memory cell groups 101 along the second direction Y. In other words, for a memory cell group 101, its two opposing first side surfaces a along the second direction Y are respectively coupled to two first conductive structures 104, i.e., the same first conductive structure 104 is shared by the two memory cell groups 101 coupled thereto.

[0136] In other examples, reference Figure 15b The first conductive structure 104 may be columnar, and two first conductive structures 104 as columnar structures are provided between two adjacent memory cell groups 101 along the second direction Y, and the two first conductive structures 104 are arranged at intervals along the first direction X as an example.

[0137] In some other examples, reference Figure 15cThe first conductive structure 104 may be ring-shaped, and only one first conductive structure 104 is provided in the interval between two adjacent memory cell groups 101 along the second direction Y.

[0138] In some other embodiments, referring to FIG. 16 , the first conductive structure 104 is located on a first side surface a of at least one memory cell group 101 (see FIG. 2 ), and the memory cell group 101 is in contact with the at least one first conductive structure 104 .

[0139] In some examples, reference Figure 16a , a first conductive structure 104 is coupled to the capacitors 103 in two memory cell groups 101 (see FIG. 2 ) located on both sides of the first conductive structure 104 .

[0140] In other examples, reference Figure 16b , the first conductive structures 104 and the memory cell groups 101 (refer to FIG2 ) correspond one to one, that is, any first conductive structure 104 is coupled only to one first side surface a of a memory cell group 101, the other first side surface a of the memory cell group 101 is in contact with and connected to the second isolation layer 115, and only one first conductive structure 104 is provided in the interval between two adjacent memory cell groups 101 along the second direction Y.

[0141] In some other examples, reference Figure 16c Any first conductive structure 104 is coupled with only one first side surface a of a memory cell group 101 (refer to FIG. 2 ), and for a memory cell group 101, its two first side surfaces a opposite to each other in the second direction Y are respectively coupled with two first conductive structures 104 .

[0142] It should be noted that FIG16 takes the first conductive structure 104 as a plate as an example. In actual applications, the first conductive structure 104 shown in FIG16 may also be columnar or ring-shaped.

[0143] The morphology of the first electrode 113 is described in detail below with reference to FIG. 15 to FIG. 17 , and parts identical or corresponding to those in the previous embodiment are not described in detail here.

[0144] In some embodiments, referring to FIG. 15 and FIG. 16 , four sidewalls of the first electrode 113 extending along the first direction X are flat.

[0145] In other embodiments, reference Figure 17aAt least one of the four sidewalls of the first electrode 113 extending along the first direction X has a stepped morphology, and along the first direction X, the cross-sectional area of ​​the first electrode 113 in a direction perpendicular to the first direction X increases sequentially. It is understandable that the first dielectric layer 123 can be considered as a film layer that conformally covers the sidewalls of the first electrode 113, that is, the first dielectric layer 123 itself also has a stepped morphology, so that the sidewall of the first conductive structure 104 coupled to the first electrode 113 and facing the first electrode 113 also has a stepped morphology.

[0146] In some other embodiments, reference Figure 17b The first electrode 113 includes first sub-electrodes 113a and second sub-electrodes 113b alternately stacked along the first direction X. The orthographic projection area of ​​the first sub-electrode 113a on the substrate 100 is larger than the orthographic projection area of ​​the second sub-electrode 113b on the substrate 100. That is, at least one of the four sidewalls of the first electrode 113 extending along the first direction X has an uneven topography. It is understood that the first dielectric layer 123 can be considered as a film layer that conformally covers the sidewalls of the first electrode 113. That is, the first dielectric layer 123 itself also has an uneven topography, causing the sidewalls of the first conductive structure 104 coupled to the first electrode 113, which are opposite to the first electrode 113, to also have an uneven topography.

[0147] It should be noted that Figures 15 and 16 both take the four flat side walls of the first electrode 113 extending along the first direction X as an example. In actual applications, the first electrode 113 in Figures 15 and 16 can also be the same as the first electrode 113 shown in Figure 17, and the appearance of the side walls of the first dielectric layer 123 and the first conductive structure 104 facing the first electrode 113 changes with the change of the morphology of the side walls of the first electrode 113.

[0148] In some embodiments, reference Figure 13 and Figure 14 , along the third direction Z, a portion of the first conductive structure 104 is embedded in the substrate 100. In other words, a groove is provided in the substrate 100 opposite to the first conductive structure 104, and the first dielectric layer 123 and the first conductive structure 104 also fill the groove together. Figure 13 This helps ensure that the four sidewalls of a row of first electrodes 113 arranged along the second direction Y closest to the substrate 100 are coupled to the first conductive structure 104, so as to ensure that the capacitance of the capacitor structure corresponding to each first electrode 113 is larger.

[0149] In some embodiments, reference Figures 9 to 12Along the third direction Z, a portion of the second conductive structure 163 is embedded in the substrate 100. In other words, the bottom surface of the second conductive structure 163 is lower than the top surface of the substrate 100. A trench is formed on the top of the substrate 100 opposite the second conductive structure 163, and the second conductive structure 163 is accommodated in the trench.

[0150] In some embodiments, reference Figure 14 The semiconductor structure may further include: a first electrical connection layer 106 , the first electrical connection layer 106 electrically connecting a plurality of first conductive structures 104 spaced apart along the second direction Y, and the first electrical connection layer 106 is located on the plurality of first conductive structures 104 .

[0151] It is understandable that Figure 14 In the embodiment, there is no conductive protrusion 114 between the adjacent first conductive structures 104 along the second direction Y (refer to Figure 13 ),but Figure 14 The potentials of the multiple first conductive structures 104 are independent of each other. On this basis, a first electrical connection layer 106 electrically connected to the multiple first conductive structures 104 is provided, which is conducive to achieving unified control of the potentials of the multiple first conductive structures 104 with the help of the first electrical connection layer 106.

[0152] It should be noted that Figure 14 The example in which the first electrical connection layer 106 is in contact with multiple first conductive structures 104 is taken as an example. In actual applications, any electrical connection structure that can achieve electrical connection between the first electrical connection layer 106 and multiple first conductive structures 104 arranged at intervals along the second direction Y can be regarded as the first electrical connection layer 106.

[0153] In some embodiments, referring to FIG3 , along the first direction X, the first length L1 of the first conductive structure 104 is less than the second length L2 of the first electrode 113. It is understood that each memory cell 111 (refer to FIG3 ) may be configured to have a first length L1 of less than the second length L2 of the first electrode 113. Figure 1 ) The ratio of the first length L1 to the second length L2 is adjusted according to the capacitance requirement of the capacitor structure corresponding to the data storage.

[0154] In some embodiments, the ratio of the first length L1 to the second length L2 may range from 0.6 to 1.

[0155] It should be noted that the various first conductive structures 104 and various first electrodes 113 shown in FIG3 to FIG5 and FIG15 and FIG16 all meet the above-mentioned requirement of “the first length L1 is less than the second length L2”. Figure 4b or Figure 15b , the first length L1 may be the total length of the plurality of first conductive structures 104 arranged along the first direction X; Figure 5a 、 Figure 5bor Figure 15c , the first length L1 may be the length of the outer contour of the first conductive structure 104 of the ring structure; referring to FIG3 to FIG5 and FIG15 and FIG16 , the second length L2 may be the length of the outer contour of the first electrode 113 .

[0156] In some embodiments, referring to FIG3 to FIG5 and FIG15 and FIG16 , the semiconductor structure may further include a second isolation layer 115 , the second isolation layer 115 being located on at least one side of the first conductive structure 104 along the first direction X, and the second isolation layer 115 being in contact with a sidewall of the first electrode 113 . For example, the first conductive structure 104 and the second conductive structure 163 are separated by the second isolation layer 115 .

[0157] It should be noted that the second isolation layer 115 is located at least between adjacent memory cell groups 101 along the second direction Y, the first isolation layer 105 is located on top of the memory cell group 101, and the third isolation layer 125 is located between adjacent capacitors 103 along the third direction Z in any memory cell group 101. It will be understood that the isolation layers in the semiconductor structure include but are not limited to the first isolation layer 105, the second isolation layer 115, and the third isolation layer 125. The division of the isolation layers in one embodiment of the present disclosure is merely an example to facilitate the description of the positional relationship between the capacitor 103, the first conductive structure 104, the second conductive structure 163, etc. in the semiconductor structure.

[0158] In some embodiments, reference Figure 18 The semiconductor structure may also include: a first conductive plug 107, located on the first conductive structure 104 and electrically connected to the first conductive structure 104; a second conductive plug 117, located on the second conductive structure 163 and electrically connected to the second conductive structure 163; a second electrical connection layer 116, located on the first conductive plug 107 and the second conductive plug 117, and electrically connecting the first conductive plug 107 and the second conductive plug 117.

[0159] It should be noted that Figure 18 This is another partial cross-sectional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure along the second cross-sectional direction BB1. Figure 18 In order to reflect the three-dimensional morphology of the first conductive structure 104, the top surface and the side surface perpendicular to the first direction X of the first conductive structure 104 are filled in the same manner, and the side surface perpendicular to the first direction X and the side surface perpendicular to the second direction Y of the first conductive structure 104 are filled in different manners; similarly, Figure 18Different filling methods are used for the side surfaces of the first conductive plug 107 perpendicular to the first direction X and the side surfaces perpendicular to the second direction Y, the same filling method is used for the top surface and the side surfaces perpendicular to the first direction X of the second electrical connection layer 116, and different filling methods are used for the side surfaces of the second electrical connection layer 116 perpendicular to the first direction X and the side surfaces perpendicular to the second direction Y. Figure 18 The second conductive structure 163 is also drawn in a perspective manner.

[0160] It can be understood that the first electrode 113 can serve as the lower electrode of the capacitor structure in the storage unit 111, the first conductive structure 104 can serve as the upper electrode of the capacitor structure in the storage unit 111, and the first conductive portion 143 and the second conductive structure 163 as a whole can also serve as the upper electrode of the capacitor structure in the storage unit 111, that is, one storage unit 111 can correspond to two upper electrodes, and the electrical connection between the first conductive structure 104 and the second conductive structure 163 can be achieved through the first conductive plug 107, the second conductive plug 117 and the second electrical connection layer 116, which is conducive to the unified control of the potential of the two upper electrodes corresponding to the storage unit 111 with the help of the second electrical connection layer 116.

[0161] It should be noted that the first conductive plug 107, the second conductive plug 117 and the second electrical connection layer 116 are used to achieve electrical connection between the first conductive structure 104 and the second conductive structure 163. To achieve electrical connection between the first conductive structure 104 and the second conductive structure 163, the embodiments of the present disclosure include but are not limited to Figure 18 The examples shown, for example, in conjunction with reference Figure 14 The first conductive plug 107 can also be electrically connected to the first conductive structure 104 through the first electrical connection layer 106. In addition, to clearly illustrate the first conductive plug 107 and the second conductive plug 117, the second electrical connection layer 116 is drawn in a perspective manner.

[0162] It can be understood that other conductive structures can also be arranged in the film layer where the first conductive plug 107 and the second conductive plug 117 are located. The functions of the first conductive plug 107 and the second conductive plug 117 are to lead the first conductive structure 104 and the second conductive structure 163 to the second electrical connection layer 116 respectively, so as to avoid the overlapping problem of the layout space between the second electrical connection layer 116 and other conductive structures in the film layer where the first conductive plug 107 is located, that is, different conductive structures are arranged in film layers at different heights to achieve diversified wiring.

[0163] In summary, part of the first conductive structure 104 can serve as a conductive plate of the capacitor 103, such as the upper electrode of the capacitor 103, that is, the first conductive structure 104 and the multiple capacitors 103 coupled thereto can form a capacitor structure. Then, the structure for storing data in each storage unit 111 includes the capacitor 103 and part of the first conductive structure 104 coupled to the storage unit 111, which is conducive to increasing the capacitance of the capacitor structure for storing data corresponding to each storage unit 111 by setting the first conductive structure 104, thereby increasing the capacitance of the storage unit group 101. Moreover, on the one hand, the first conductive structure 104 is arranged between the adjacent memory cell groups 101 along the second direction Y, and the length of the semiconductor structure along the first direction X will not be increased due to the addition of the first conductive structure 104, and the space occupied by the first conductive structure 104 is part of the space of the isolation layer set to isolate the adjacent memory cell groups 101, which is beneficial to reducing the length of the semiconductor structure in the first direction X to improve the integration density of the semiconductor structure; on the other hand, the first conductive structure 104 extends along the third direction Z. It can be understood that the first conductive structure 104 can be prepared in a direction perpendicular to the substrate 100, that is, in the vertical direction. The preparation process is simple, so it is easy to control the dimensional accuracy of the first conductive structure 104 to improve the electrical performance of the semiconductor structure.

[0164] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which is used to form the semiconductor structure provided by the aforementioned embodiment. The manufacturing method provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 19 to 23 This is a schematic cross-sectional view of each step in the method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Figures 19 to 23 All of them are schematic diagrams of partial structures of semiconductor structures. Parts identical or corresponding to the above embodiments are not described in detail here.

[0165] refer to Figures 1 to 23 The manufacturing method of the semiconductor structure includes: providing a substrate 100; forming a memory cell group 101 on the substrate 100, the memory cell group 101 including a plurality of vertically stacked memory cells 111, the memory cell 111 including a transistor 102 and a capacitor 103, the capacitor 103 extending along a first direction X parallel to the substrate 100; forming a first conductive structure 104, located on a first side a of the memory cell group 101, the first conductive structure 104 and the memory cell group 101 are arranged along a second direction Y parallel to the substrate 100, the first conductive structure 104 extends along a third direction perpendicular to the substrate 100, the first conductive structure 104 is coupled with the plurality of capacitors 103 in the memory cell group 101, and the first direction X and the second direction Y intersect.

[0166] It can be understood that the first conductive structure 104 can serve as a conductive plate of any capacitor 103, and the first conductive structure 104 and multiple capacitors 103 coupled thereto can form a capacitor structure. Then, the structure for storing data in each storage unit 111 includes the capacitor 103 and a portion of the first conductive structure 104 coupled to the storage unit 111. Under this premise, a first conductive structure 104 is formed between the storage cell groups 101 arranged at intervals along the second direction Y. On the one hand, the first conductive structure 104 can be formed by vertical etching and vertical filling. The formation process of the first conductive structure 104 is simple, which is conducive to improving the dimensional accuracy of the formed first conductive structure 104. On the other hand, due to the addition of the first conductive structure 104, the length of the capacitor 103 in the first direction X can be reduced. Therefore, when a through hole is formed by etching and the capacitor 103 is formed in the through hole, it is conducive to reducing the aspect ratio of the through hole, reducing the difficulty of etching, and further reducing the difficulty of filling the capacitor 103 when the capacitor 103 is formed in the through hole, thereby simplifying the process steps of preparing the capacitor 103 and improving the dimensional accuracy of the formed capacitor 103.

[0167] In addition, a first conductive structure 104 is provided at least in the isolation layer for isolating adjacent memory cell groups 101, that is, the space occupied by the first conductive structure 104 is part of the space of the isolation layer for isolating adjacent memory cell groups 101, which is beneficial for increasing the capacitance of the capacitor structure corresponding to any memory cell group 101 while reducing the length of the semiconductor structure in the first direction X, so as to improve the integration density of the semiconductor structure.

[0168] Therefore, the preparation method provided in another embodiment of the present disclosure can not only increase the capacitance of the capacitor structure corresponding to any storage unit group 101 without setting up additional layout space, but also is conducive to simplifying the process steps of forming the capacitor 103 and the first conductive structure 104, and improving the dimensional accuracy of the formed capacitor 103 and the first conductive structure 104, thereby improving the electrical performance of the semiconductor structure while improving the integration density of the semiconductor structure.

[0169] It should be noted that before forming the capacitor 103 and the first conductive structure 104, the transistor 102, the bit line structure 108 and the word line structure 109 may all have been formed in the semiconductor structure; or, after forming the capacitor 103 and the first conductive structure 104, the transistor 102, the bit line structure 108 and the word line structure 109 may be formed in the semiconductor structure.

[0170] In the following, the transistor 102, the bit line structure 108 and the word line structure 109 may all be formed in the semiconductor structure as an example. Figures 1 to 23How to form the capacitor 103 and the first conductive structure 104 in another embodiment of the present disclosure is described in detail.

[0171] In some embodiments, forming a memory cell group 101 on a substrate 100 includes the following steps:

[0172] refer to Figures 1 to 21 A plurality of first electrodes 113 extending along a first direction X are formed on the substrate 100 . The plurality of first electrodes 113 are arranged at intervals along a second direction Y and a third direction Z. The first direction X and the second direction Y intersect and are both parallel to the substrate 100 .

[0173] In some embodiments, the step of forming a plurality of first electrodes 113 extending along the first direction X on the substrate 100 includes:

[0174] refer to Figure 19 A stacked structure 110 is formed on a substrate 100 , and the stacked structure 110 includes first sacrificial layers 120 and second sacrificial layers 130 alternately stacked along a third direction Z. It is understood that the first sacrificial layers 120 and the second sacrificial layers 130 are made of different materials. Figure 19 The figure is merely an example of the first sacrificial layers 120 and the second sacrificial layers 130 alternately stacked in the stack structure 110 . In practical applications, there is no limitation on the number of the first sacrificial layers 120 and the number of the second sacrificial layers 130 in the stack structure 110 .

[0175] In some embodiments, the stacked structure 110 may be formed by epitaxial growth, for example, the first sacrificial layer 120 and the second sacrificial layer 130 are germanium silicon and silicon respectively; in other embodiments, the stacked structure 110 may be formed by chemical vapor deposition, for example, the first sacrificial layer 120 and the second sacrificial layer 130 are an insulating layer and a semiconductor layer respectively, and the semiconductor layer may be polycrystalline silicon or a metal oxide semiconductor layer, and the metal oxide semiconductor layer includes but is not limited to zinc tin oxide (ZnO). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn x O), indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O, commonly known as "IGSO"), indium tungsten oxide (In x W y O, commonly known as "IWO"), indium oxide (In x O) etc.

[0176] in, Figure 19 This is a schematic cross-sectional structural diagram along a first cross-sectional direction AA1 of a stacked structure 110 formed in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0177] It is understood that after forming the stacked structure 110 and before forming the capacitor trench 131, the manufacturing method may further include forming the transistor 102, the bit line structure 108, and the word line structure 109. It should be noted that the positional relationship between the transistor 102, the bit line structure 108, and the word line structure 109 and the subsequently formed capacitor 103 has been described in detail in the aforementioned embodiment and will not be repeated here.

[0178] refer to Figures 19 to 21 , the second sacrificial layer 130 is patterned to form a capacitor groove 131 extending along the first direction X, and a plurality of capacitor grooves 131 are arranged at intervals at least along the second direction Y; Figure 21 and Figures 3 to 8, or in conjunction with reference Figure 21 15 to 17 , a first electrode 113 is formed in the capacitor groove 131 .

[0179] In some embodiments, patterning the second sacrificial layer 130 includes the following steps:

[0180] Combined with reference Figure 19 and Figure 20 , the stacked structure 110 is etched to form a second through hole 149 penetrating the stacked structure 110 in the third direction Z. The second through hole 149 exposes the first sacrificial layer 120 and the second sacrificial layer 130. It can be understood that the second through hole 149 is mainly used to position the second conductive structure 163 (refer to Figure 9 ) position, a second dielectric layer 153 will be formed in the second through hole 149 later (refer to Figure 9 ) and a second conductive structure 163.

[0181] in, Figure 20 This is a schematic cross-sectional structure diagram along a first cross-sectional direction AA1 when forming a second through hole 149 in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0182] In some examples, in conjunction with reference Figure 8a and Figure 20 In the step of etching the stacked structure 110 to form the second through hole 149, the number of the formed second through holes 149 can be multiple, and the multiple second through holes 149 are arranged at intervals along the second direction Y; in other examples, combined with reference Figure 8b and Figure 20 , or combined with reference Figure 8c and Figure 20In the step of etching the stacked structure 110 to form the second through hole 149 , the number of the formed second through hole 149 can be one, which is beneficial to further simplify the process steps.

[0183] In some embodiments, reference Figure 8b or 8c, the second conductive structure 163 is electrically connected to all the first conductive portions 143, and the reference Figure 1 , Figure 8 and Figure 20 Multiple memory cell groups 101 are arranged along the second direction Y. The formed second through-holes 149 can only expose the first sacrificial layer 120 and the second sacrificial layer 130 corresponding to one memory cell group 101. In other words, the opening size of the second through-holes 149 can be small, and the second through-holes 149 do not need to expose the first sacrificial layer 120 and the second sacrificial layer 130 corresponding to each memory cell group 101. Subsequently, the stacked structure is wet-etched based on the second through-holes 149 to form capacitor trenches at the locations of the portions of the second sacrificial layers corresponding to any memory cell group 101. This helps to streamline the process steps for forming the second through-holes 149 and shorten the time required to form the second through-holes 149.

[0184] In some embodiments, reference Figure 20 In the step of etching the stacked structure 110 to form the second through hole 149 , the substrate 100 is also etched, that is, the second through hole 149 also penetrates a portion of the thickness of the substrate 100 , so that the subsequently formed second conductive structure is embedded in the substrate 100 .

[0185] Combined with reference Figure 20 and Figure 21 , etching is performed laterally along the second through hole 149 to remove a portion of the second sacrificial layer 130 and form a capacitor groove 131 .

[0186] in, Figure 21 This is a schematic cross-sectional structural diagram along a first cross-sectional direction AA1 when forming a capacitor trench 131 in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0187] In some embodiments, the cross-sectional shape of the second through hole 149 may be square, circular, or other polygonal along a cross section perpendicular to the first direction X. The following description will take the cross-sectional shape of the second through hole 149 along the cross section of the first direction X as an example.

[0188] In some embodiments, the second sacrificial layer 130 includes a first sub-sacrificial layer and a second sub-sacrificial layer alternately arranged along the second direction Y, wherein the semiconductor layer 112 is in contact with the first sub-sacrificial layer, and the semiconductor layer 112 corresponds to the first sub-sacrificial layer one-to-one. A portion of the second sub-sacrificial layer subsequently serves as the second isolation layer 115 (see FIG3 ). On this basis, the step of laterally etching along the second through hole 149 to remove a portion of the second sacrificial layer 130 includes: laterally etching along the second through hole 149 to remove the first sub-sacrificial layer to form a capacitor trench 131 exposing the semiconductor layer 112.

[0189] It is understandable that, in some examples, the capacitor groove 131 can be subsequently used to form the first electrode 113 shown in Figures 15 to 17, that is, the first electrode 113 itself is a solid structure. It should be noted that to form the first electrode 113 shown in Figure 17, the initial capacitor groove is formed after the first sub-sacrificial layer is removed by lateral etching along the second through hole 149. The initial capacitor groove is processed by an etching process to form a capacitor groove with an inner wall having a stepped morphology or an uneven morphology. Another embodiment of the present disclosure does not limit the specific process of forming a capacitor groove with an inner wall having a stepped morphology or an uneven morphology.

[0190] In other examples, the capacitor groove 131 can be subsequently used to form the first electrode 113 shown in Figures 3 to 7, and further used to form the second dielectric layer 153 and the first conductive portion 143 shown in Figures 3 to 5. It should be noted that in order to form the first electrode 113 shown in Figure 7, the initial capacitor groove is formed after the first sub-sacrificial layer is removed by lateral etching along the second through hole 149. The initial capacitor groove is processed by an etching process to form a capacitor groove with an inner wall having a stepped morphology or an uneven serrated morphology. Another embodiment of the present disclosure does not limit the specific process of forming a capacitor groove with an inner wall having a stepped morphology or an uneven serrated morphology.

[0191] It can be understood that the formed capacitor slots 131 are arranged in an array along the second direction Y and the third direction Z, and the plurality of capacitor slots 131 spaced apart along the third direction Z are subsequently used to form the memory cell group 101 (refer to FIG. Figure 1 )).

[0192] In some embodiments, in conjunction with reference Figure 21 and Figure 9The step of forming the first electrode 113 in the capacitor groove 131 includes: forming the first electrode 113 conformally covering the inner wall of the capacitor groove 131, the first electrode 113 is a cup-shaped structure having an opening 133 facing the first direction X; the manufacturing method may also include: forming a second dielectric layer 153 conformally covering at least the inner wall of the first electrode 113; forming a first conductive portion 143 and a second conductive structure 163 located on the surface of the second dielectric layer 153, the first conductive portion 143 and the first electrode 113 corresponding to each other one by one and embedded in the first electrode 113 through the opening 133, and the second conductive structure 163 filling the second through hole 149.

[0193] Understandably, the reference Figure 21 , multiple capacitor slots 131 are connected to the second through-holes 149 to form a first gap, and the step of forming the first electrode 113 includes: conformally covering the inner wall of the first gap with a layer of first electrode film, etching part of the first electrode film with the help of the second through-holes 149 to form the first electrodes 113 corresponding to each other in the capacitor slots 131, that is, the first electrodes 113 are arranged in an array along the second direction Y and the third direction Z; then, conformally covering the remaining part of the first gap with a second dielectric layer 153, and finally filling the first gap with a conductive material. Among them, the conductive material filled horizontally, that is, filled into the capacitor slots 131 along the first direction X, serves as the first conductive part 143, and the conductive material filled into the second through-holes 149 along the third direction Z, that is, along the vertical direction, serves as the second conductive structure 163, so that the first conductive part 143 and the second conductive structure 163 are formed as one piece.

[0194] In addition, referring to FIG3 , the first conductive structure 104 formed subsequently can increase the capacitance of the capacitor structure for storing data corresponding to each memory cell 111. Moreover, the first conductive structure 104 is disposed between adjacent memory cell groups 101 along the second direction Y, and the length of the semiconductor structure along the first direction X is not increased due to the addition of the first conductive structure 104.

[0195] On this basis, reference Figure 21 , a capacitor trench 131 with a shallower depth in the first direction X can be prepared, that is, in another embodiment of the present disclosure, the aspect ratio of the capacitor trench 131 can be reduced. In this way, when the first electrode 113 subsequently conformally covers the inner wall of the capacitor trench 131, it is helpful to avoid the problem of insufficient filling of the first electrode 113 due to the excessive aspect ratio of the capacitor trench 131, thereby improving the dimensional accuracy of the formed first electrode 113. Similarly, it is helpful to avoid the problem of insufficient filling of the second dielectric layer 153 and the first conductive portion 143 in the capacitor trench 131, thereby improving the dimensional accuracy of the formed second dielectric layer 153 and the first conductive portion 143.

[0196] In some other embodiments, after the first sub-sacrificial layer is removed by side etching along the second through hole 149 to form the capacitor groove 131 exposing the semiconductor layer 112, the first sub-sacrificial layer 131 is removed by side etching along the second through hole 149 to form the capacitor groove 131 exposing the semiconductor layer 112. Figure 21 and Figure 11 After forming the first electrode 113 in the capacitor groove 131 and before forming the second dielectric layer 153, the manufacturing method may further include: laterally etching along the second through hole 149 to remove a portion of the second sub-sacrificial layer and a portion of the first electrode 113 to form a groove extending along the second direction Y, and the plurality of grooves are arranged at intervals along the third direction Z, and one groove exposes a plurality of capacitor grooves 131 arranged along the second direction Y.

[0197] It can be understood that the plurality of capacitor slots 131, the plurality of grooves, and the second through-hole 149 are all connected to form a second gap, and a second dielectric layer 153 is conformally covered on the inner wall of the second gap, and finally the second gap is filled with a conductive material. Among them, the conductive material filled horizontally, that is, filled into the capacitor slot 131 along the first direction X, serves as the first conductive portion 143, the conductive material filled into the groove along the first direction X serves as the second conductive portion 173, and the conductive material filled into the second through-hole 149 along the third direction Z, that is, along the vertical direction, serves as the second conductive structure 163, so that the first conductive portion 143, the second conductive portion 173, and the second conductive structure 163 are integrally formed.

[0198] In some embodiments, after forming the first electrode 113, forming the storage cell group 101 on the substrate 100 also includes the following steps: referring to Figures 3 to 17, forming a first dielectric layer 123, the first dielectric layer 123 is located on the side wall of the first electrode 113; after forming the first conductive structure 104, the first conductive structure 104 is in contact with the first dielectric layer 123.

[0199] In some embodiments, the steps of forming the first conductive structure 104 include: Figure 22 , etching the stacked structure 110 (refer to Figure 19 ), so as to form a first through hole 139 penetrating the stacked structure 110 in the third direction Z, the first through hole 139 being located between the first electrodes 113 adjacent to each other along the second direction Y; Figure 22 and Figure 14 , forming a first conductive structure 104 in the first through hole 139 .

[0200] in, Figure 22 This is a schematic cross-sectional structural diagram along a first cross-sectional direction AA1 when forming a first through hole 139 in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0201] In some embodiments, reference Figure 14In the step of etching the stacked structure 110 to form the first through hole 139 , the substrate 100 is also etched, that is, the first through hole 139 also penetrates a portion of the thickness of the substrate 100 , so that the subsequently formed first conductive structure is embedded in the substrate 100 .

[0202] In some embodiments, in conjunction with reference Figure 22 and Figure 14 The top surface of the row of first electrodes 113 that is farthest from the substrate 100 and arranged along the second direction Y further comprises a first isolation layer 105. During the step of etching the stacked structure 110 to form the first through-holes 139, the first isolation layer 105 is also etched. That is, the first through-holes 139 penetrate the first isolation layer 105, so that the second height of the subsequently formed first conductive structure along the third direction is greater than the first height of the memory cell group along the third direction.

[0203] In some embodiments, based on the first electrode 113 being a cup-shaped structure with an opening 133 as shown in Figures 3 to 5, before forming the first conductive structure 104 in the first through hole 139, a first dielectric layer 123 is first formed to conformally cover the inner wall of the first through hole 139, and then the first conductive structure 104 is formed to fill the remaining portion of the first through hole 139.

[0204] In other embodiments, based on the columnar structure of the first electrode 113 as shown in FIG. 15 , the first dielectric layer 123 may be formed after the first electrode 113 is formed, and only the first conductive structure 104 may be formed in the first through hole 139 .

[0205] In some other embodiments, based on the columnar structure of the first electrode 113 as shown in Figure 16, before forming the first conductive structure 104 in the first through hole 139, a first dielectric layer 123 conformally covering the inner wall of the first through hole 139 is first formed, and then the first conductive structure 104 filling the remaining part of the first through hole 139 is formed.

[0206] It is understandable that the formation timing of the first dielectric layer 123 can be flexibly adjusted according to the morphology of the first electrode 113 to be formed. Figure 22 and Figure 14 , the remaining first sacrificial layer 120 can serve as the third isolation layer 125 .

[0207] In some embodiments, reference Figure 22 , a plurality of first through holes 139 are arranged at intervals at least along the second direction Y; Figure 14After forming the first conductive structure 104 in the first through hole 139, the manufacturing method may further include: forming a first electrical connection layer 106 on the top surface of the multiple first conductive structures 104, the first electrical connection layer 106 electrically connecting the multiple first conductive structures 104 arranged at intervals along the second direction Y.

[0208] In other embodiments, reference Figure 21 , the first through hole 139 exposes the sidewall of the first electrode 113 and the sidewall of the first sacrificial layer 120 , and the manufacturing method may further include the following steps:

[0209] Combined with reference Figure 21 and Figure 22 , laterally etching along the first through hole 139 to remove the first sacrificial layer 120 exposed by the first through hole 139 and form a connecting groove 121, the connecting groove 121 is located between the first electrodes 113 adjacent along the third direction Z, and the connecting groove 121 is connected to the two adjacent first through holes 139 along the second direction Y.

[0210] Combined with reference Figure 22 and Figure 13 The formed first dielectric layer 123 also covers the inner wall of the connecting groove 121.

[0211] Combined with reference Figure 22 and Figure 13 The step of forming the first conductive structure 104 in the first through hole 139 may further include: forming a conductive protrusion 114 in the connecting groove 121 .

[0212] in, Figure 23 This is a schematic cross-sectional structure diagram along a first cross-sectional direction AA1 when forming a connecting groove 121 in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0213] It is understandable that, in conjunction with reference Figure 1 and Figure 23 A plurality of memory cell groups 101 are arranged along the second direction Y, and the first through holes 139 may be formed only in the intervals between some adjacent memory cell groups 101. Figure 23 While the example of forming two first through-holes 139 is used, in actual applications, only one first through-hole 139 may be formed. In other words, the opening size of first through-hole 139 can be smaller, and first through-hole 139 does not need to expose the first electrode 113 and first sacrificial layer 120 corresponding to each memory cell group 101. Subsequently, the stacked structure is wet-etched based on first through-holes 139 to form connecting grooves 121 at the locations of the first sacrificial layer 120 corresponding to any memory cell group 101. This facilitates streamlining the process steps for forming first through-hole 139 and shortens the time required to form first through-hole 139.

[0214] In addition, referring to Figures 3 to 5 or Figures 15 and 16, the first conductive structure 104 only surrounds a portion of the length of the first electrode 113 along the first direction X. Therefore, in the step of wet etching the stacked structure based on the first through hole 139, the side wall of the first electrode 113 extending along the first direction X is also connected to the remaining first sacrificial layer 120. It can be understood that this portion of the first sacrificial layer 120 can serve as a supporting layer to avoid the collapse of the prepared first electrode 113, which is beneficial to improving the yield of the final semiconductor structure.

[0215] In some embodiments, the first electrode 113 is a cup-shaped structure as shown in Figures 3 to 7. On this basis, before forming the first through hole 139, the first electrode 113 is also embedded with the second dielectric layer 153 and the first conductive portion 143, and the first conductive portion 143 is in contact and connected with the second conductive structure 163. In this way, the second dielectric layer 153, the first conductive portion 143 and the second conductive structure 163 can jointly support the first electrode 113. In the step of wet etching the stacked structure based on the first through hole 139, the collapse of the prepared first electrode 113 is avoided, which is beneficial to improving the yield of the semiconductor structure finally formed.

[0216] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a memory cell group located on the substrate, the memory cell group including a plurality of vertically stacked memory cells, the memory cells including transistors and capacitors, the capacitors extending along a first direction parallel to the substrate; A first conductive structure is located on a first side of the memory cell group, the first conductive structure and the memory cell group are arranged along a second direction parallel to the substrate, the first conductive structure extends along a third direction perpendicular to the substrate, the first conductive structure is coupled with multiple capacitors in the memory cell group, and the first direction and the second direction intersect.

2. The semiconductor structure according to claim 1, wherein: The plurality of memory cell groups and the plurality of first conductive structures are alternately arranged along the second direction; the first conductive structure is located on a first side of at least one memory cell group, and the memory cell group is in contact with at least one first conductive structure.

3. The semiconductor structure according to claim 1, wherein: The first conductive structure is plate-shaped and extends along the first direction and the third direction.

4. The semiconductor structure according to claim 2, wherein: At least one first conductive structure is coupled to the capacitors in two memory cell groups respectively located on both sides of the first conductive structure.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that The second height of the first conductive structure along the third direction is greater than the first height of the memory cell group along the third direction; the semiconductor structure also includes: a first isolation layer, the first isolation layer at least covers the top of the memory cell group, and the first conductive structure is adjacent to the first isolation layer.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that The capacitor includes a first electrode extending along the first direction; The semiconductor structure further includes a first dielectric layer located between the first conductive structure and the first electrode.

7. The semiconductor structure according to claim 6, wherein: Also includes: a conductive protrusion protruding from a sidewall of the first conductive structure and sandwiched between adjacent first electrodes along the third direction; The first dielectric layer is also located between the conductive protrusion and the first electrode.

8. The semiconductor structure according to claim 6, wherein: The first electrode is a cup-shaped structure having an opening facing the first direction, and the semiconductor structure further includes: a first conductive portion extending along the first direction, the first conductive portion corresponding to the first electrode in a one-to-one manner and passing through the opening and embedded in the first electrode; a second dielectric layer located between the first conductive portion and the first electrode; A second conductive structure is located on a second side of the memory cell group and is arranged along the first direction with the memory cell group. The second conductive structure extends along the third direction. The second conductive structure is electrically connected to the first conductive portion. The second dielectric layer also covers the sidewalls of the second conductive structure.

9. The semiconductor structure according to claim 8, wherein: The second conductive structure is in contact with and connected to all the first conductive portions, or a plurality of second conductive structures are arranged at intervals along the second direction, and each second conductive structure is in contact with and connected to a plurality of first conductive portions arranged at intervals along the third direction.

10. The semiconductor structure according to claim 8, wherein: Also includes: A second conductive portion, the second conductive portion extends along the second direction and is arranged at intervals along the third direction, the second conductive portion has a third side surface and a fourth side surface opposite to each other along the first direction, the third side surface is in contact and connected with multiple first conductive portions arranged at intervals along the second direction, and the fourth side surface is in contact and connected with the second conductive structure; the second dielectric layer also covers the side walls of the second conductive portion.

11. The semiconductor structure according to claim 8, wherein: The storage cell groups are also arranged at intervals along the first direction, the first conductive parts are also arranged at intervals along the first direction, adjacent first conductive parts along the first direction are in contact and connected with the same second conductive structure, and the two adjacent storage cell groups arranged at intervals along the first direction are mirror-distributed along the second conductive structure.

12. The semiconductor structure according to claim 6, wherein: The first electrode is a columnar structure extending along the first direction, and the first dielectric layer covers at least a portion of a sidewall of the first electrode parallel to the first direction.

13. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Along the third direction, a portion of the height of the first conductive structure is embedded in the substrate.

14. The semiconductor structure according to any one of claims 1 to 4, characterized in that Also includes: A first electrical connection layer electrically connects a plurality of first conductive structures spaced apart along the second direction, and the first electrical connection layer is located on the plurality of first conductive structures.

15. The semiconductor structure according to claim 6, wherein: Along the first direction, the first length of the first conductive structure is less than the second length of the first electrode; the semiconductor structure also includes: a second isolation layer, the second isolation layer is located on at least one side of the first conductive structure along the first direction, and the second isolation layer is in contact with the side wall of the first electrode.

16. The semiconductor structure according to claim 8, wherein: Also includes: a first conductive plug, located on the first conductive structure and electrically connected to the first conductive structure; a second conductive plug, located on the second conductive structure and electrically connected to the second conductive structure; The second electrical connection layer is located on the first conductive plug and the second conductive plug, and electrically connects the first conductive plug and the second conductive plug.

17. The semiconductor structure according to claim 1, wherein: The transistor includes a semiconductor layer extending along the first direction, and the semiconductor layer includes a first surface and a second surface facing each other along the first direction, and the first surface is in contact with the capacitor; The semiconductor structure further comprises: a bit line structure, contact-connected to the second surface; A word line structure, located on a side of the semiconductor layer; The word line structure extends along the second direction, and the bit line structure extends along the third direction; or the word line structure extends along the third direction, and the bit line structure extends along the second direction.

18. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a memory cell group on the substrate, the memory cell group comprising a plurality of vertically stacked memory cells, the memory cells comprising transistors and capacitors, the capacitors extending along a first direction parallel to the substrate; A first conductive structure is formed and located on a first side of the memory cell group. The first conductive structure and the memory cell group are arranged along a second direction parallel to the substrate. The first conductive structure extends along a third direction perpendicular to the substrate. The first conductive structure is coupled with a plurality of the capacitors in the memory cell group, and the first direction and the second direction intersect.

19. The manufacturing method according to claim 18, characterized in that: forming the memory cell group on the substrate, comprising: forming a stack structure on the substrate, the stack structure comprising first sacrificial layers and second sacrificial layers alternately stacked along the third direction; Performing patterning on the second sacrificial layer to form capacitor grooves extending along the first direction, wherein a plurality of the capacitor grooves are arranged at intervals at least along the second direction; forming a first electrode in the capacitor groove, wherein a plurality of the first electrodes are arranged at intervals along the second direction and the third direction, wherein the first direction and the second direction intersect and are both parallel to the substrate; forming a first dielectric layer, wherein the first dielectric layer is located on a sidewall of the first electrode; After the first conductive structure is formed, the first conductive structure contacts the first dielectric layer.

20. The manufacturing method according to claim 19, characterized in that Forming the first conductive structure includes: Etching the stack structure to form a first through hole penetrating the stack structure in the third direction, wherein the first through hole is located between adjacent first electrodes along the second direction; The first conductive structure is formed in the first through hole.

21. The manufacturing method according to claim 20, characterized in that: The first through hole exposes a sidewall of the first electrode and a sidewall of the first sacrificial layer, and the manufacturing method further includes: performing lateral etching along the first through-hole to remove the first sacrificial layer exposed by the first through-hole and form a connecting groove, wherein the connecting groove is located between the first electrodes adjacent to each other along the third direction and is connected to two adjacent first through-holes along the second direction; The formed first dielectric layer also covers the inner wall of the communicating groove; The step of forming the first conductive structure in the first through hole further includes: forming a conductive protrusion in the connecting groove.

22. The manufacturing method according to claim 19, characterized in that The second sacrificial layer is patterned, comprising: Etching the stack structure to form a second through hole penetrating the stack structure in the third direction, wherein the second through hole exposes the first sacrificial layer and the second sacrificial layer; Laterally etching along the second through hole to remove a portion of the second sacrificial layer and form the capacitor groove; Forming the first electrode in the capacitor slot includes: forming the first electrode conformally covering an inner wall of the capacitor slot, wherein the first electrode is a cup-shaped structure having an opening facing the first direction; The manufacturing method further includes: forming a second dielectric layer that conformally covers at least an inner wall of the first electrode; A first conductive portion and a second conductive structure are formed on the surface of the second dielectric layer. The first conductive portion corresponds to the first electrode one-to-one and is embedded in the first electrode through the opening. The second conductive structure fills the second through hole.

23. The manufacturing method according to claim 20, characterized in that Multiple first through holes are arranged at intervals at least along the second direction; after forming the first conductive structure in the first through hole, the manufacturing method further includes: forming a first electrical connection layer on the top surface of the multiple first conductive structures, the first electrical connection layer electrically connecting the multiple first conductive structures arranged at intervals along the second direction.

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