Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming first isolation layers and second isolation layers, which are alternately stacked, on the substrate; the first isolation layer and the second isolation layer are etched, a capacitor hole group is formed, and the capacitor hole group comprises at least two capacitor sub-holes which are arranged at intervals in the first direction and extend to the substrate; performing lateral etching on the second isolation layer from the capacitance sub-hole to form a first surrounding groove surrounding the capacitance sub-hole; forming a first capacitor electrode which extends along the first direction and fills the first surrounding groove; and forming a capacitor dielectric layer on the side wall and the bottom of the capacitor sub-hole, and forming a second capacitor electrode on the surface of the capacitor dielectric layer. The embodiment of the invention can effectively improve the performance of the device.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In the traditional three-dimensional memory device manufacturing process, a stacked structure of silicon / silicon germanium is usually prepared first, and before forming the transistors and capacitors of the memory cell, the stacked structure is etched to form an isolation trench. The isolation trench is used to isolate the transistors and / or capacitors formed subsequently. Then, an insulating dielectric layer is filled in the isolation trench.

[0003] However, as the number of stacked layers of three-dimensional memory devices increases, the depth of the isolation trench becomes deeper and deeper. At this time, the bottom of the isolation trench may not be completely etched, resulting in incorrect electrical connections of the transistors and / or capacitors at the bottom, causing the performance of the entire memory cell to be unstable, thereby affecting the device performance. Summary of the invention

[0004] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce the process difficulty of manufacturing a memory device, especially a three-dimensional memory device.

[0005] A method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, and forming a first isolation layer and a second isolation layer stacked alternately on the substrate;

[0007] Etching the first isolation layer and the second isolation layer to form a capacitor hole group, wherein the capacitor hole group includes at least two capacitor sub-holes arranged at intervals along a first direction and extending to the substrate;

[0008] Laterally etching the second isolation layer from the capacitor hole to form a first surrounding groove surrounding the capacitor hole;

[0009] forming a first capacitor electrode extending along the first direction and filling the first surrounding groove;

[0010] A capacitor dielectric layer is formed on the sidewall and bottom of the capacitor hole, and a second capacitor electrode is formed on the surface of the capacitor dielectric layer.

[0011] In one embodiment, the shortest distance between the capacitor sub-holes adjacent to each other along the first direction in the same capacitor sub-hole group is H1, and the etching depth of the second isolation layer lateral etching from the capacitor sub-hole is H2, and H2>=0.5H1.

[0012] In one embodiment, forming a capacitor hole group penetrating the stacked structure includes:

[0013] Forming a plurality of capacitor hole groups spaced apart along a second direction, wherein the second direction intersects the first direction, and a plane defined by the second direction and the first direction intersects an extension direction of the capacitor sub-holes;

[0014] Furthermore, the shortest distance between the capacitor subholes adjacent to each other along the second direction is H3, and H3>2H2.

[0015] In one embodiment, H3>=3H2.

[0016] In one embodiment, a capacitor region and a transistor region arranged along the first direction are provided on the substrate, and the capacitor hole group is located in the capacitor region.

[0017] The etching of the first isolation layer and the second isolation layer to form a capacitor hole group also forms a word line hole arranged opposite to the capacitor hole group in the first direction, wherein the word line hole is located in the transistor region and extends to the substrate;

[0018] Before the second isolation layer is laterally etched from the capacitor hole, the method further includes:

[0019] filling a sacrificial layer in the word line hole;

[0020] After forming a capacitor dielectric layer on the sidewall and bottom of the capacitor sub-hole and forming a second capacitor electrode on the surface of the capacitor dielectric layer, the method further includes:

[0021] removing the sacrificial layer located in the word line hole;

[0022] Laterally etching the second isolation layer from the word line hole to form a second surrounding groove surrounding the word line hole, wherein the second surrounding groove exposes the first capacitor electrode;

[0023] forming a channel layer in the second surrounding groove;

[0024] A gate dielectric layer is formed on the sidewall of the word line hole, and a word line is formed on the surface of the gate dielectric layer.

[0025] A semiconductor structure comprising:

[0026] substrate;

[0027] A first isolation layer and a second isolation layer alternately stacked on the substrate;

[0028] A first capacitor electrode, comprising at least two annular portions arranged along a first direction, adjacent annular portions being connected to each other, and the first capacitor electrode being located between adjacent first isolation layers and being wrapped by the second isolation layer;

[0029] A second capacitor electrode, surrounded by the annular portion, passes through the alternately stacked first isolation layers and second isolation layers and extends to the substrate;

[0030] a capacitor dielectric layer, surrounded by the annular portion, located between the second capacitor electrode and the first capacitor electrode, and located on a side wall of the second capacitor electrode;

[0031] Among them, the shortest distance between adjacent capacitor dielectric layers in the first direction is H1, the width of the first capacitor electrode in the second direction is H2, H2>=0.5H1, the second direction intersects with the first direction, and the plane determined by the second direction and the first direction intersects with the extension direction of the capacitor sub-hole.

[0032] In one embodiment, the semiconductor structure includes a plurality of the first capacitor electrodes arranged at intervals along the second direction, and the shortest distance between the capacitor dielectric layers adjacent to each other along the second direction is H3, H3>2H2.

[0033] In one embodiment, H3>=3H2.

[0034] In one embodiment,

[0035] The substrate is provided with a capacitor region and a transistor region arranged along the first direction, the first capacitor electrode is located in the capacitor region, and the transistor region is provided with a transistor connected to the first capacitor electrode;

[0036] The transistor comprises:

[0037] a word line, penetrating the first isolation layer and the second isolation layer and extending to the substrate, and arranged opposite to the first capacitor electrode in the first direction;

[0038] A gate dielectric layer, located on a side wall of the word line;

[0039] The channel layer is located between adjacent first isolation layers, connected to the first capacitor electrode, and wrapped by the second isolation layer, and the channel layer surrounds the gate dielectric layer.

[0040] In one embodiment,

[0041] The substrate is further provided with a bit line region, the transistor region is located between the capacitor region and the bit line region in the first direction, and a bit line is provided in the bit line region.

[0042] The bit line is located between adjacent first isolation layers, and the bit line and the first capacitor electrode are respectively connected to two sides of the channel layer, and the bit line extends along the second direction.

[0043] The method for preparing the above-mentioned semiconductor structure first forms a capacitor sub-hole extending to the substrate in the alternately stacked first isolation layer and the second isolation layer, and then laterally etches the second isolation layer from the capacitor sub-hole, so that a capacitor (including a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode) can be directly formed. At the same time. The first isolation layer and the second isolation layer that are initially deposited can be used as isolation dielectric layers to insulate and isolate the capacitor, so that there is no need to etch to form isolation grooves. Therefore, this embodiment can effectively reduce the process difficulty of preparing storage devices, especially three-dimensional storage devices, and can effectively prevent capacitors from being connected incorrectly, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0046] Figures 2 to 14 Schematic diagram of the structure obtained in different orientations in each step of the preparation process of the semiconductor structure provided in an embodiment, wherein: Fig.14 Schematic diagram of the structure of a semiconductor structure provided in different orientations in an embodiment.

[0047] Description of reference numerals:

[0048] 100-substrate, 210-first isolation layer, 220-second isolation layer, 310-first capacitor electrode, 311-annular portion, 320-capacitor dielectric layer, 330-second capacitor electrode, 331-electrode layer, 332-filling conductive layer, 400-sacrificial layer, 500-transistor, 510-channel layer, 520-gate dielectric layer, 530-word line, 531-metal diffusion barrier layer, 532-metal layer, 600-bit line, 10-capacitor hole group, 11-capacitor sub-hole, 20-first surrounding groove, 30-word line hole, 40-second surrounding groove, 50-etched opening, 60-bit line groove. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0051] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] In one embodiment, see Figure 1 , a method for preparing a semiconductor structure is provided, comprising the following steps:

[0055] Step S100, see Figure 2 , providing a substrate 100, and forming a first isolation layer 210 and a second isolation layer 220 alternately stacked on the substrate 100;

[0056] Step S200, see Figure 3 , etching the first isolation layer 210 and the second isolation layer 220 to form a capacitor hole group 10, wherein the capacitor hole group 10 includes at least two capacitor sub-holes 11 arranged at intervals along the first direction and extending to the substrate 100;

[0057] Step S400, see Figure 6 , the second isolation layer 220 is laterally etched from the capacitor hole 11 to form a first surrounding groove 20 surrounding the capacitor hole 11;

[0058] Step S500, see Figure 7 , forming a first capacitor electrode 310 extending along the first direction and filling the first surrounding groove 20;

[0059] Step S600, see Figure 8 A capacitor dielectric layer 320 is formed on the sidewall and bottom of the capacitor hole 11 , and a second capacitor electrode 330 is formed on the surface of the capacitor dielectric layer 320 .

[0060] In step S100, refer to Figure 2 The substrate 100 may be made of semiconductor material, insulating material, conductive material or any combination thereof. For example, the substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may also include a substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0061] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0062] When the first isolation layer 210 and the second isolation layer 220 are alternately stacked on the substrate 100, the first isolation layer 210 and the second isolation layer 220 may be repeatedly alternately formed on the substrate 100 through a deposition process. The first isolation layer 210 and the second isolation layer 220 are made of different materials. The first isolation layer 210 may include, but is not limited to, silicon oxide. The second isolation layer 220 may include, but is not limited to, silicon nitride.

[0063] The deposition process may include but is not limited to one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0064] The number of layers of the second isolation layer 220 is at least one. As an example, a plurality of first isolation layers 210 and a plurality of second isolation layers 220 may be formed. A first isolation layer 210 may be formed on both sides of each second isolation layer 220. In this case, it is convenient to form a three-dimensional device.

[0065] In step S200, refer to Figure 3 , a first patterned photoresist may be first formed on the top first isolation layer 210. The first patterned photoresist may have a first opening. The first opening may define the size and position of the capacitor hole 11. Then, based on the first patterned photoresist, the first isolation layer 210 and the second isolation layer 220 are dry-etched, etc., so as to form a plurality of capacitor holes 11 that are spaced apart and extend to the substrate 100. Among them, at least two capacitor holes 11 spaced apart along the first direction form a capacitor hole group 10. As an example, each capacitor hole 11 in the same capacitor hole group 10 may be arranged at equal intervals along the first direction.

[0066] In step S400, refer to Figure 6 The second isolation layer 220 can be laterally etched back from the capacitor hole 11 by wet or dry etching, etc., so as to form a surrounding groove surrounding the capacitor hole 11.

[0067] In step S500, refer to Figure 7 , a first capacitor electrode material layer may be first deposited on the surface of the structure obtained after forming the first surrounding groove 20. Then, the first capacitor electrode material layer is etched to remove the first capacitor electrode material layer outside the first surrounding groove 20. The first capacitor electrode material layer remaining in the first surrounding groove 20 forms the first capacitor electrode 310.

[0068] The material of the first capacitor electrode 310 may include but is not limited to titanium nitride (TiN). For example, the material of the first capacitor electrode 310 may also include indium tin oxide (ITO). For another example, the material of the first capacitor electrode 310 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc.

[0069] In step S600, refer to Figure 8 , a capacitor dielectric material layer may be deposited on the surface of the structure obtained after forming the first capacitor electrode 310, and then a second capacitor electrode material layer may be deposited on the surface of the capacitor dielectric material layer. As an example, the second capacitor electrode material layer may include an electrode material layer and a filling material layer. The electrode material layer may be formed on the surface of the capacitor dielectric material layer. The filling material layer may be formed on the surface of the electrode material layer and fill the remaining space of the capacitor sub-hole 11.

[0070] Afterwards, the second capacitor electrode material layer and the capacitor dielectric material layer outside the capacitor hole 11 can be removed by a process such as chemical mechanical polishing (CMP). The remaining capacitor dielectric material layer forms the capacitor dielectric layer 320. The remaining second capacitor electrode material layer forms the second capacitor electrode 330. When the second capacitor electrode material layer can include an electrode material layer and a filling material layer, the remaining electrode material layer forms the electrode layer 331, and the remaining filling material layer forms the filling conductive layer 332. That is, at this time, the second capacitor electrode 330 includes the electrode layer 331 and the filling conductive layer 332.

[0071] The first capacitor electrode 310 , the capacitor dielectric layer 320 opposite thereto, and the second capacitor electrode 330 may form a capacitor 300 .

[0072] Among them, the material of the capacitor dielectric layer 320 may include but is not limited to high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The material of the electrode layer 331 may include but is not limited to titanium nitride (TiN). For example, the material of the electrode layer 331 may also include indium tin oxide (ITO). For another example, the material of the electrode layer 331 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc. The material of the filling conductive layer 332 may include but is not limited to silicon germanium (SiGe) or doped polycrystalline silicon, etc.

[0073] It is understandable that in order to make the image clear, Figures 8 to 14 In Figure (c), the capacitor dielectric layer 320 and the electrode layer 331 are omitted.

[0074] In this embodiment, by first forming a capacitor hole 11 extending to the substrate 100 in the alternately stacked first isolation layer 210 and the second isolation layer 220, and then laterally etching the second isolation layer 220 from the capacitor hole 11, the capacitor 300 (including the first capacitor electrode 310, the capacitor dielectric layer 320 and the second capacitor electrode 330) can be directly formed. At the same time. The first isolation layer 210 and the second isolation layer 220 that are initially deposited can be used as isolation dielectric layers to insulate and isolate the capacitor 300, so that there is no need to etch to form isolation grooves. Therefore, this embodiment can effectively reduce the process difficulty of preparing storage devices, especially three-dimensional storage devices, and can effectively prevent the capacitor 300 from being connected incorrectly, thereby improving device performance.

[0075] It is understandable that the size of the capacitor hole 11 is larger than that of the conventional isolation trench. Therefore, the capacitor hole 11 of this embodiment will not have the problem of being unable to complete etching when the number of stacked layers is large, as in the conventional isolation trench.

[0076] In one embodiment, see Figure 6 The shortest distance between adjacent capacitor holes 11 along the first direction in the same capacitor hole group 10 is H1. Meanwhile, in step S400, the etching depth of the second isolation layer 220 lateral-etched from the capacitor hole 11 is H2, and H2>=0.5H1.

[0077] At this time, after the lateral etching, the capacitor sub-holes 11 adjacent to each other along the first direction in the same capacitor hole group 10 are connected to each other.

[0078] Therefore, after the first surrounding groove 20 is filled to form the first capacitor electrode 310 in step S500, the first capacitor electrode 310 extending along the first direction and wrapping the plurality of capacitor sub-holes 11 in the same capacitor hole group 10 in the first direction can be formed. The width of the first capacitor electrode 310 in the second direction is H2. The plane defined by the second direction and the first direction intersects with the extension direction of the capacitor sub-hole 11.

[0079] As an example, the first direction may be perpendicular to the second direction. A plane defined by the second direction and the first direction may be perpendicular to an extension direction of the capacitor hole 11 .

[0080] At this time, the first capacitor electrode 310 may include at least two annular portions 311 arranged along the first direction. Each annular portion 311 may be formed in a first surrounding groove 20. Adjacent annular portions 311 are connected to each other. At the same time, the first capacitor electrode 310 and the second isolation layer 220 are both located between adjacent first isolation layers 210. And the first capacitor electrode 310 is wrapped by the second isolation layer 220.

[0081] After the capacitor dielectric layer 320 and the second capacitor electrode 330 are formed in step S600 , the shortest distance between adjacent capacitor dielectric layers 320 in the first direction is H1 .

[0082] In this embodiment, the first capacitor electrode 310 can form a capacitor 300 together with the capacitor dielectric layer 320 in the plurality of capacitor sub-holes 11 in the same capacitor hole group 10 and the second capacitor electrode 330 , thereby effectively improving the capacitance value of the capacitor 300 .

[0083] In one embodiment, see Figure 3 , step S200 includes:

[0084] Step S210 , forming a plurality of capacitor hole groups 10 arranged at intervals along a second direction, wherein the second direction intersects the first direction, and a plane defined by the second direction and the first direction intersects an extension direction of the capacitor sub-holes 11 .

[0085] As an example, the capacitor hole 11 may extend vertically, and a plane defined by the second direction and the first direction may be perpendicular to the extension direction of the capacitor hole 11 .

[0086] When the shortest distance between adjacent capacitor holes 11 along the first direction in the same capacitor hole group 10 is H1, and the etching depth of the second isolation layer 220 from the capacitor hole 11 is H2, and H2>=0.5H1, each of the multiple capacitor hole groups 10 arranged at intervals along the second direction can form a corresponding capacitor 300.

[0087] Also, see Figure 6 , the shortest distance between the capacitor sub-holes 11 adjacent to each other along the second direction is set to H3, H3>2H2.

[0088] At this time, after the lateral etching in step S400 , the second isolation layer 220 between the capacitor hole groups 10 adjacent in the second direction will not be etched through, so that the first surrounding grooves 20 adjacent in the second direction can be insulated and isolated by the second isolation layer 220 .

[0089] Therefore, after the first surrounding groove 20 is subsequently filled to form the first capacitor electrode 310, and the capacitor dielectric layer 320 and the second capacitor electrode 330 are formed, the first capacitor electrodes 310 adjacent in the second direction can be insulated and isolated by the second isolation layer 220. Therefore, the capacitors 300 adjacent in the second direction formed based on the capacitor hole groups 10 adjacent in the second direction can be effectively insulated and isolated by the second isolation layer 220.

[0090] Meanwhile, after the capacitor dielectric layers 320 are formed, the shortest distance between the capacitor dielectric layers 320 adjacent to each other in the second direction is H3.

[0091] As an example, H3>=3H2 can be set. At this time, after the lateral etching in step S400, in the second direction, the width of the second isolation layer 220 between adjacent capacitor hole groups 10 is theoretically greater than or equal to H2, thereby ensuring that the capacitors 300 adjacent to each other in the second direction are reliably isolated.

[0092] In one embodiment, see Figure 3 A capacitor region A1 and a transistor region A2 arranged along a first direction are provided on the substrate 100 , and the capacitor hole group 10 is located in the capacitor region A1 .

[0093] At the same time, in step S200 , the first isolation layer 210 and the second isolation layer 220 are etched to form the capacitor hole group 10 , and at the same time, a word line hole 30 arranged opposite to the capacitor hole group 10 in the first direction is formed. The word line hole 30 is located in the transistor region and extends to the substrate 100 .

[0094] At this time, in step S200, a first patterned photoresist may be first formed on the top first isolation layer 210. The first patterned photoresist may have a first opening and a second opening. The first opening is located in the capacitor area A1, and may define the size and position of the capacitor sub-hole 11. The second opening is located in the transistor area A2, and may define the size and position of the word line hole 30. Then, based on the first patterned photoresist, the first isolation layer 210 and the second isolation layer 220 are dry-etched, etc., so as to form the capacitor sub-hole 11 in the capacitor area A1 and the word line hole 30 in the transistor area A2.

[0095] At the same time, before step 400, the method further includes:

[0096] In step S300 , a sacrificial layer 400 is filled in the word line hole 30 .

[0097] At this time, see Figure 4 as well as Figure 5 , a sacrificial material layer can be first formed in the word line hole 30, in the capacitor hole 11, and on the upper surface of the top first isolation layer 210 by a chemical vapor deposition process or the like. Then, the sacrificial material layer located on the upper surface of the top first isolation layer 210 is removed by a chemical mechanical polishing (CMP) process to form a sacrificial layer 400. Thereafter, a second patterned photoresist can be formed. The second patterned photoresist can cover the sacrificial layer 400 located in the word line hole 30, while exposing the remaining sacrificial material layer located in the capacitor hole 11. Thereafter, the sacrificial layer 400 in the capacitor hole 11 can be etched away. At the same time, the sacrificial layer 400 in the word line hole 30 is retained.

[0098] The material of the sacrificial layer 400 may include, but is not limited to, polysilicon.

[0099] After the sacrificial layer 400 is filled in the word line hole 30 , the first capacitor electrode 310 , the capacitor dielectric layer 320 and the second capacitor electrode 330 formed in steps S400 to S600 will not be formed in the word line hole 30 , thereby not affecting the subsequent preparation of the transistor 500 .

[0100] Afterwards, after step S600, the method further includes:

[0101] Step S710, see Fig. 9 , removing the sacrificial layer 400 located in the word line hole 30;

[0102] Step S720, see Fig.10 , the second isolation layer 220 is laterally etched from the word line hole 30 to form a second surrounding groove 40 surrounding the word line hole 30 , wherein the second surrounding groove 40 exposes the first capacitor electrode 310 ;

[0103] Step S730, see Fig.11 , forming a channel layer 510 in the second surrounding groove 40;

[0104] Step S740, see Fig.12 , a gate dielectric layer 520 is formed on the sidewall of the word line hole 30 , and a word line 530 is formed on the surface of the gate dielectric layer 520 .

[0105] In step S710, refer to Fig. 9 The sacrificial layer 400 in the word line hole 30 may be removed by wet etching or the like.

[0106] In step S720, refer to Fig.10 The second isolation layer 220 between the first isolation layers 210 can be etched back from the word line hole 30 by wet etching, so as to form a second surrounding groove 40 surrounding the word line hole 30. The second surrounding groove 40 exposes the first capacitor electrode 310.

[0107] The etching depth of the second isolation layer 220 lateral etching from the capacitor hole 11 is H2, the etching depth of the second isolation layer 220 lateral etching from the word line hole 30 is H4, and the shortest distance between the word line hole 30 and the capacitor hole 11 adjacent thereto along the first direction is H5. (H2+H4)>=H5 can be set so that the second surrounding groove 40 exposes the first capacitor electrode 310.

[0108] In step S730, refer to Fig.11, a channel material layer may be first deposited on the surface of the structure obtained after forming the second surrounding groove 40. Then, the channel material layer is etched to remove the channel material layer outside the second surrounding groove 40. The channel material layer remaining in the second surrounding groove 40 forms a channel layer 510. The material of the channel layer 510 may include, but is not limited to, indium gallium zinc oxide (IGZO).

[0109] Since the second surrounding groove 40 surrounds the word line hole 30, the channel layer 510 surrounds the word line hole 30, so that it is easy to form a channel all around (CAA) type transistor 500. At the same time, since the second surrounding groove 40 exposes the first capacitor electrode 310 and the channel layer 510 fills the second surrounding groove 40, the channel layer 510 can be connected to the first capacitor electrode 310, and then one of the source region and the drain region of the transistor 500 can be connected to the first capacitor electrode 310 of the capacitor 300.

[0110] In step S740, refer to Fig.12 , a gate dielectric material layer may be formed on the sidewall of the wordline hole 30, the bottom of the wordline hole 30 and the upper surface of the top first isolation layer 210, and then a wordline material layer may be deposited on the surface of the gate dielectric material layer. The wordline material layer may fill the remaining space of the wordline hole 30. Afterwards, the gate dielectric material layer and the wordline material layer outside the wordline hole 30 may be removed by a process such as chemical mechanical polishing (CMP). The remaining gate dielectric material layer forms a gate dielectric layer 520. The remaining wordline material layer forms a wordline 530.

[0111] The material of the gate dielectric layer 520 may include but is not limited to a high dielectric constant material layer. The word line 530 may include a metal diffusion barrier layer 531 and a metal layer 532. The metal diffusion barrier layer 531 may include but is not limited to titanium nitride, etc. The material of the metal layer 532 may include but is not limited to metal tungsten (W), etc.

[0112] After the gate dielectric layer 520 and the word line 530 are formed, the word line 530 , the gate dielectric layer 520 and the channel layer 510 may form a CAA transistor 500 .

[0113] It is understandable that in order to make the image clear, Figure 12 to Figure 14 In FIG. 5( c ), the gate dielectric layer 520 and the metal diffusion barrier layer 531 are omitted.

[0114] In one embodiment, a bit line 600 region A3 is further provided on the substrate, and the transistor region A2 is located between the capacitor region A1 and the bit line 600 region A3 in the first direction.

[0115] After step S740, the method further includes:

[0116] Step S810, see Fig.13 , forming an etched opening 50 extending in a second direction and penetrating the substrate 100 in the bit line 600 region A3, the second direction intersects the first direction, and the plane determined by the second direction and the first direction intersects the extension direction of the capacitor hole 11;

[0117] Step S820, please continue to refer to Fig.13 , the second isolation layer 220 is laterally etched from the etched opening 50 to form a bit line groove 60 extending along the second direction and exposing the channel layer 510;

[0118] Step S830, see Fig.14 , a bit line 600 is formed in the bit line trench 60 .

[0119] In step S810, refer to Fig.13 A third patterned photoresist may be first formed on the upper surface of the structure obtained after forming the gate dielectric layer 520 and the word line 530. The third patterned photoresist may have a third opening, which may be located in the bit line 600 region A3 and extend along the second direction.

[0120] Then, etching may be performed based on the third patterned photoresist to form an etching opening 50 extending along the second direction and penetrating the substrate 100. Thereafter, the third patterned photoresist is removed.

[0121] In step S820, refer to Fig.13 , the second isolation layer 220 located between the first isolation layers 210 can be etched back from the self-etched opening 50 by wet etching or the like, thereby forming a bit line groove 60 extending along the second direction and exposing the channel layer 510 .

[0122] The etching depth of the second isolation layer 220 lateral etching from the word line hole 30 is H4, the etching depth of the second isolation layer 220 lateral etching from the etching opening 50 is H6, and the shortest distance between the etching opening 50 and the word line hole 30 along the first direction is H7. (H6+H4)>=H7 can be set so that the bit line groove 60 can expose the channel layer 510.

[0123] In step S830, refer to Fig.14 After the bit line 600 is formed in the bit line groove 60 , the bit line 600 extends along the second direction. Since the bit line groove 60 exposes the channel layer 510 , the bit line 600 can be connected to the channel layer 510 , and the other of the source region and the drain region of the transistor 500 can be connected to the bit line 600 .

[0124] As an example, after step S830, the method further includes:

[0125] Step S840 , filling the etched opening 50 with an insulating dielectric layer.

[0126] The insulating dielectric layer may be protected by, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), or a silicon oxynitride layer (SiON).

[0127] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0128] In one embodiment, see Fig.14 , and also provides a semiconductor structure. The semiconductor structure includes a substrate 100 , a first isolation layer 210 , a second isolation layer 220 , a first capacitor electrode 310 , a second capacitor electrode 330 , and a capacitor dielectric layer 320 .

[0129] The substrate 100 may be made of semiconductor material, insulating material, conductive material or any combination thereof. For example, the substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0130] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0131] The first isolation layer 210 and the second isolation layer 220 are alternately stacked and arranged on the substrate 100. The first isolation layer 210 and the second isolation layer 220 are made of different materials. The first isolation layer 210 may include but is not limited to silicon oxide. The second isolation layer 220 may include but is not limited to silicon nitride.

[0132] The number of layers of the second isolation layer 220 is at least one. As an example, the semiconductor structure may have a plurality of first isolation layers 210 and a plurality of second isolation layers 220. A first isolation layer 210 may be provided on both sides of each second isolation layer 220. In this case, it is convenient to form a three-dimensional device.

[0133] The first capacitor electrode 310 may include at least two annular portions 311 arranged along the first direction. Adjacent annular portions 311 are connected to each other. At the same time, the first capacitor electrode 310 and the second isolation layer 220 are both located between adjacent first isolation layers 210. The first capacitor electrode 310 is wrapped by the second isolation layer 220.

[0134] The material of the first capacitor electrode 310 may include but is not limited to titanium nitride (TiN). For example, the material of the first capacitor electrode 310 may also include indium tin oxide (ITO). For another example, the material of the first capacitor electrode 310 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc.

[0135] The second capacitor electrode 330 and the capacitor dielectric layer 320 are both surrounded by the annular portion 311. Each surrounding portion of the first capacitor electrode 310 may contain the second capacitor electrode 330 and the capacitor dielectric layer 320. The capacitor dielectric layer 320 is located between the second capacitor electrode 330 and the first capacitor electrode 310.

[0136] The second capacitor electrode 330 penetrates the alternately stacked first isolation layer 210 and the second isolation layer 220 and extends to the substrate 100. The capacitor dielectric layer 320 is located on the sidewall of the second capacitor electrode 330. Meanwhile, as an example, the capacitor dielectric layer 320 can also be located at the bottom of the second capacitor electrode 330. The first capacitor electrode 310 and the capacitor dielectric layer 320 and the second capacitor electrode 330 opposite thereto can form a capacitor 300.

[0137] As an example, the second capacitor electrode 330 may include an electrode layer 331 and a filling conductive layer 332. The material of the electrode layer 331 may include, but is not limited to, titanium nitride (TiN). For example, the material of the electrode layer 331 may also include indium tin oxide (ITO). For another example, the material of the electrode layer 331 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc. The material of the filling conductive layer 332 may include, but is not limited to, silicon germanium (SiGe) or doped polycrystalline silicon, etc.

[0138] At the same time, the shortest distance between adjacent capacitor dielectric layers 320 in the first direction is H1, the width of the first capacitor electrode 310 in the second direction is H2, H2>=0.5H1, the second direction intersects with the first direction, and the plane determined by the second direction and the first direction intersects with the extension direction of the capacitor sub-hole 11.

[0139] In this embodiment, the first capacitor electrode 310 and the second isolation layer 220 are both located between adjacent first isolation layers 210. And the first capacitor electrode 310 is wrapped by the second isolation layer 220. At this time, the first isolation layer 210 and the second isolation layer 220 can be used to insulate and isolate the capacitor. Therefore, in the preparation process of the semiconductor structure of this embodiment, it is no longer necessary to etch and form an isolation groove. Therefore, this embodiment can effectively reduce the process difficulty of preparing a memory device, especially a three-dimensional memory device, and can effectively prevent the capacitor from being connected incorrectly, thereby improving the device performance.

[0140] Furthermore, the first capacitor electrode 310 may include at least two annular portions 311 arranged along the first direction. Adjacent annular portions 311 are connected to each other. A second capacitor electrode 330 and a capacitor dielectric layer 320 may be disposed in each surrounding portion of the first capacitor electrode 310. Therefore, the first capacitor electrode 310 may form a capacitor together with a plurality of second capacitor electrodes 330 and a capacitor dielectric layer 320, thereby effectively increasing the capacitance value of the capacitor.

[0141] In one embodiment, the semiconductor structure includes a plurality of first capacitor electrodes 310 arranged at intervals along the second direction. A second capacitor electrode 330 and a capacitor dielectric layer 320 may be disposed in each surrounding portion of each first capacitor electrode 310 .

[0142] The shortest distance between the capacitor dielectric layers 320 adjacent to each other along the second direction is H3, and H3>2H2.

[0143] In one embodiment, H3>=3H2. In the second direction, the width of the second isolation layer 220 between adjacent first capacitor electrodes 310 is greater than or equal to H2, so that the capacitors adjacent to each other along the second direction can be reliably isolated.

[0144] In one embodiment, a capacitor region and a transistor region arranged along a first direction are disposed on the substrate 100 , the first capacitor electrode 310 is located in the capacitor region, and a transistor 500 connected to the first capacitor electrode 310 is disposed in the transistor region.

[0145] The transistor 500 includes a word line 530 , a gate dielectric layer 520 , and a channel layer 510 .

[0146] The word line 530 passes through the first isolation layer 210 and the second isolation layer 220 and extends to the substrate 100, and is disposed opposite to the first capacitor electrode 310 in the first direction. The gate dielectric layer 520 is located on the sidewall of the word line 530. As an example, the gate dielectric layer 520 can also be located at the bottom of the word line 530.

[0147] The word line 530 may include a metal diffusion barrier layer 531 and a metal layer 532. The metal diffusion barrier layer 531 may be located between the gate dielectric layer 520 and the metal layer 532. The metal diffusion barrier layer 531 may include but is not limited to ITO or titanium nitride. The material of the metal layer 532 may include but is not limited to metal tungsten (W).

[0148] The material of the gate dielectric layer 520 may include, but is not limited to, a high dielectric constant material layer.

[0149] The material of the channel layer 510 may include, but is not limited to, indium gallium zinc oxide (IGZO).

[0150] The channel layer 510 , the first capacitor electrode 310 and the second isolation layer 220 are simultaneously located between adjacent first isolation layers 210 . The channel layer 510 is connected to the first capacitor electrode 310 and is wrapped by the second isolation layer 220 . The channel layer 510 surrounds the gate dielectric layer 520 .

[0151] In one embodiment, a bit line 600 region is further disposed on the substrate 100 , the transistor region is located between the capacitor region and the bit line 600 region in the first direction, and a bit line 600 is disposed in the bit line 600 region.

[0152] The bit line 600, the channel layer 510, the first capacitor electrode 310 and the second isolation layer 220 are located between adjacent first isolation layers 210. The bit line 600 and the first capacitor electrode 310 are connected to two sides of the channel layer 510 respectively. Moreover, the bit line 600 extends along the second direction.

[0153] As an example, the semiconductor structure may further include an insulating dielectric layer. The insulating dielectric layer is located on a side of the bit line 600 away from the transistor region.

[0154] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming a first isolation layer and a second isolation layer stacked alternately on the substrate; Etching the first isolation layer and the second isolation layer to form a capacitor hole group, wherein the capacitor hole group includes at least two capacitor sub-holes arranged at intervals along a first direction and extending to the substrate; Laterally etching the second isolation layer from the capacitor hole to form a first surrounding groove surrounding the capacitor hole; forming a first capacitor electrode extending along the first direction and filling the first surrounding groove; A capacitor dielectric layer is formed on the sidewall and bottom of the capacitor hole, and a second capacitor electrode is formed on the surface of the capacitor dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The shortest distance between the capacitor sub-holes adjacent to each other along the first direction in the same capacitor sub-hole group is H1, and the etching depth of the second isolation layer lateral-etched from the capacitor sub-hole is H2, where H2>=0.5H1.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of the capacitor hole group penetrating the stacked structure comprises: Forming a plurality of capacitor hole groups spaced apart along a second direction, wherein the second direction intersects the first direction, and a plane defined by the second direction and the first direction intersects an extension direction of the capacitor sub-holes; Furthermore, the shortest distance between the capacitor subholes adjacent to each other along the second direction is H3, and H3>2H2.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: H3>=3H2.

5. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that: The substrate is provided with a capacitor region and a transistor region arranged along the first direction, and the capacitor hole group is located in the capacitor region. The etching of the first isolation layer and the second isolation layer to form a capacitor hole group also forms a word line hole arranged opposite to the capacitor hole group in the first direction, wherein the word line hole is located in the transistor region and extends to the substrate; Before the second isolation layer is laterally etched from the capacitor hole, the method further includes: filling a sacrificial layer in the word line hole; After forming a capacitor dielectric layer on the sidewall and bottom of the capacitor sub-hole and forming a second capacitor electrode on the surface of the capacitor dielectric layer, the method further includes: removing the sacrificial layer located in the word line hole; Laterally etching the second isolation layer from the word line hole to form a second surrounding groove surrounding the word line hole, wherein the second surrounding groove exposes the first capacitor electrode; forming a channel layer in the second surrounding groove; A gate dielectric layer is formed on the sidewall of the word line hole, and a word line is formed on the surface of the gate dielectric layer.

6. A semiconductor structure, characterized in that: include: substrate; A first isolation layer and a second isolation layer alternately stacked on the substrate; A first capacitor electrode, comprising at least two annular portions arranged along a first direction, adjacent annular portions being connected to each other, and the first capacitor electrode being located between adjacent first isolation layers and being wrapped by the second isolation layer; A second capacitor electrode, surrounded by the annular portion, passes through the alternately stacked first isolation layers and second isolation layers and extends to the substrate; a capacitor dielectric layer, surrounded by the annular portion, located between the second capacitor electrode and the first capacitor electrode, and located on a side wall of the second capacitor electrode; Among them, the shortest distance between adjacent capacitor dielectric layers in the first direction is H1, the width of the first capacitor electrode in the second direction is H2, H2>=0.5H1, the second direction intersects with the first direction, and the plane determined by the second direction and the first direction intersects with the extension direction of the capacitor sub-hole.

7. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure includes a plurality of the first capacitor electrodes arranged at intervals along the second direction, and the shortest distance between the capacitor dielectric layers adjacent to each other along the second direction is H3, H3>2H2.

8. The semiconductor structure according to claim 7, characterized in that: H3>=3H2.

9. The semiconductor structure according to claim 6, characterized in that: The substrate is provided with a capacitor region and a transistor region arranged along the first direction, the first capacitor electrode is located in the capacitor region, and the transistor region is provided with a transistor connected to the first capacitor electrode; The transistor comprises: a word line, penetrating the first isolation layer and the second isolation layer and extending to the substrate, and arranged opposite to the first capacitor electrode in the first direction; A gate dielectric layer, located on a side wall of the word line; The channel layer is located between adjacent first isolation layers, connected to the first capacitor electrode, and wrapped by the second isolation layer, and the channel layer surrounds the gate dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that: The substrate is further provided with a bit line region, the transistor region is located between the capacitor region and the bit line region in the first direction, and a bit line is provided in the bit line region. The bit line is located between adjacent first isolation layers, and the bit line and the first capacitor electrode are respectively connected to two sides of the channel layer, and the bit line extends along the second direction.

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