Semiconductor device, memory and method of manufacturing the same, electronic device

Abstract

The present disclosure relates to a semiconductor device, a memory and a preparation method thereof, and an electronic device, and relates to the technical field of storage, so as to improve the performance and reliability of the semiconductor device and the memory. The semiconductor device comprises a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line. The first semiconductor layer is insulatively surrounded around the side wall of the first gate. The second gate is located on the side of the first semiconductor layer away from the first gate, and comprises a first part electrically connected with the first semiconductor layer, and a second part located on the side of the first part away from the first semiconductor layer and electrically connected with the first part. The second semiconductor layer is insulatively surrounded around the side wall of the second part and the bottom wall of the second part away from the first part. The third gate and the common source line are insulatively spaced around the side of the second semiconductor layer away from the side wall of the second part.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of storage, and in particular, to a semiconductor device, a memory and a preparation method therefor, and an electronic device. BACKGROUND

[0002] With the development of communication technology and digital technology, people continue to pursue products with lower power consumption, lighter weight and better performance. Memory is easy to have higher integration density and larger storage capacity, and gradually becomes one of the important research directions in the current storage field. For example, in the example of dynamic random access memory (DRAM) using 2T0C semiconductor devices, problems such as read current multi-path and read current congestion are easily encountered during data reading, thereby adversely affecting the performance of the DRAM. SUMMARY

[0003] Based on this, the embodiments of the present disclosure provide a semiconductor device, a memory and a preparation method therefor, and an electronic device, which are beneficial to improve the performance and reliability of the semiconductor device and the memory.

[0004] According to some embodiments, the present disclosure provides a semiconductor device in one aspect, comprising: a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line. The first semiconductor layer is insulatively surrounded around the side wall of the first gate. The second gate is located on the side of the first semiconductor layer away from the first gate, and comprises: a first part electrically connected with the first semiconductor layer, and a second part located on the side of the first part away from the first semiconductor layer and electrically connected with the first part. The second semiconductor layer is insulatively surrounded around the side wall of the second part and the bottom wall of the second part away from the first part. The third gate and the common source line are spaced around the side of the second semiconductor layer away from the side wall of the second part, and the third gate is insulated from the second semiconductor layer.

[0005] According to some embodiments, the first semiconductor layer is electrically connected with the first bit line on the side away from the first gate and away from the first part. The second semiconductor layer is electrically connected with the second bit line on the side of the bottom wall of the second part away from the first part. The first bit line and the second bit line are arranged in parallel and spaced apart, and extend along the first direction.

[0006] According to some embodiments, the first gate and the first word line are electrically connected and extend along a third direction. The first semiconductor layer extends along the third direction around the center line. The second gate extends along a second direction, and the second semiconductor layer extends along the second direction around the center line. The second direction intersects the first direction. The third gate and the common source line extend along the second direction around the center line. The third gate and the second word line are electrically connected, and the second word line extends along the third direction. The common source line extends in a direction away from the second semiconductor layer. The third direction intersects the first direction and the second direction.

[0007] According to some embodiments, the semiconductor device further comprises a write transistor, a read transistor, and a read control transistor. The write transistor comprises a first gate, a first source-drain, and a second source-drain. The first source-drain is a portion of the first semiconductor layer away from the first gate and away from the first portion, and the second source-drain is a portion of the first semiconductor layer away from the first gate and in contact with the first portion. The read transistor comprises a second gate, a third source-drain, and a fourth source-drain. The read control transistor comprises a third gate, a fifth source-drain, and a sixth source-drain. The third source-drain and the fifth source-drain are portions of the second semiconductor layer around the periphery of the second portion and in contact with the common source line. The fourth source-drain and the sixth source-drain are portions of the second semiconductor layer away from the bottom wall of the second portion.

[0008] According to some embodiments, the semiconductor device further comprises a write transistor and a read transistor. The write transistor comprises a first gate, a first source-drain, and a second source-drain. The first source-drain is a portion of the first semiconductor layer away from the first gate and away from the first portion, and the second source-drain is a portion of the first semiconductor layer away from the first gate and in contact with the first portion. The read transistor comprises a second gate, a third gate, a third source-drain, and a fourth source-drain. The third source-drain is a portion of the second semiconductor layer around the periphery of the second portion and in contact with the common source line. The fourth source-drain is a portion of the second semiconductor layer away from the bottom wall of the second portion. The second gate is a storage gate of the read transistor, and the third gate is a control gate of the read transistor.

[0009] According to some embodiments, the semiconductor device further comprises a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer. The first gate dielectric layer is between the first gate and the first semiconductor layer. The second gate dielectric layer is between the second gate and the second semiconductor layer. The third gate dielectric layer is between the third gate and the second semiconductor layer.

[0010] According to some embodiments, there is a gap between the second semiconductor layer and the first semiconductor layer along the second direction. The semiconductor device further comprises a fourth gate dielectric layer in the gap between the first semiconductor layer and the second semiconductor layer and covering the sidewall of the first portion. The fourth gate dielectric layer is connected to the second gate dielectric layer.

[0011] According to some embodiments, the first portion has a dimension in the first direction that is greater than a dimension of the second portion in the first direction. The first portion has a dimension in the second direction that is less than a dimension of the second portion in the second direction.

[0012] According to some embodiments, the first semiconductor layer has a dimension in the first direction that is greater than a maximum dimension of the second gate in the first direction.

[0013] According to some embodiments, another aspect of the present disclosure also provides a memory including one or more semiconductor devices as described in any of the preceding embodiments.

[0014] According to some embodiments, yet another aspect of the present disclosure also provides a method for manufacturing a memory, including the following steps:

[0015] forming a first conductive material layer, and patterning the first conductive material layer to form a second bit line and a dummy first bit line arranged in parallel and spaced apart, and a dummy gate between the second bit line and the dummy first bit line and connecting the second bit line and the dummy first bit line. The second bit line and the dummy first bit line extend along a first direction, and the dummy gate extends along a second direction.

[0016] filling a dielectric material on both sides of the dummy gate in the first direction.

[0017] etching the dummy gate and the dielectric material in a first target region of the dummy gate close to the dummy first bit line to form an etching hole.

[0018] based on the etching hole, performing a wet etching process along the second direction and the first direction on the dummy first bit line and the remaining dummy gate to form a containing space. The containing space exposes a corresponding sidewall of the second bit line.

[0019] sequentially depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in the containing space.

[0020] removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the first target region, and the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the second target region and the third target region adjacent to the first target region along the second direction, so that the remaining semiconductor material layer constitutes a second semiconductor layer, the remaining gate dielectric material layer constitutes a second gate dielectric layer, the second conductive material layer remaining on the side of the second target region close to the second bit line is a second portion of a second gate, and the second conductive material layer remaining on the side of the third target region away from the second bit line is a first bit line.

[0021] forming a fourth gate dielectric layer on the sidewall of the second semiconductor layer and the second gate dielectric layer away from the second bit line. The fourth gate dielectric layer is connected with the second gate dielectric layer.

[0022] The first part of the second gate is formed on the second target region on the side wall of the second part and the fourth gate dielectric layer away from the second bit line.

[0023] The first semiconductor layer, the first gate dielectric layer and the first gate are sequentially formed on the hole wall of the hole etched between the first part and the first bit line.

[0024] According to some embodiments, the preparation method of the memory further comprises the following steps:

[0025] The third gate dielectric layer and the third gate are sequentially arranged around the fourth target region on the side wall of the second semiconductor layer extending in the second direction and away from the side wall of the second gate.

[0026] The first word line electrically connected with the first gate is formed.

[0027] The second word line electrically connected with the third gate is formed.

[0028] The common source line is formed in the fifth target region on the side of the second semiconductor layer close to the first part. The common source line is arranged around the side of the second semiconductor layer extending in the second direction and away from the side wall of the second gate. The fifth target region is located in the interval between the fourth target region and the first part.

[0029] According to some embodiments, the third gate dielectric layer and the third gate are sequentially arranged around the fourth target region on the side wall of the second semiconductor layer extending in the second direction and away from the side wall of the second gate comprises the following steps:

[0030] The dielectric material is etched in the third direction to expose the side wall of the second semiconductor layer in the fourth target region away from the second gate dielectric layer.

[0031] The third gate dielectric layer is deposited on the side wall surface of the second semiconductor layer in the fourth target region away from the second gate dielectric layer. The third gate is deposited on the side wall surface of the third gate dielectric layer away from the second semiconductor layer.

[0032] According to some embodiments, based on the etched hole, the virtual first bit line and the retained virtual gate are removed to form the accommodation space, further comprising the following steps:

[0033] The wet etching process in the second direction and the first direction is performed on the virtual first bit line and the retained virtual gate to form the accommodation space.

[0034] According to some embodiments, the disclosure further provides an electronic device comprising one or more memories as described in the foregoing embodiments.

[0035] The embodiments of the disclosure can / at least have the following advantages:

[0036] In the embodiments of the present disclosure, the second gate is arranged on the side of the first semiconductor layer away from the first gate, and the second gate includes a first part electrically connected with the first semiconductor layer and a second part arranged on the side of the first part away from the first semiconductor layer and electrically connected with the first part, and the second semiconductor layer is insulatively surrounded by the side wall of the second part and the bottom wall of the second part away from the first part. In this way, after the third gate and the common source line are insulatively surrounded by the side wall of the second part of the second gate away from the second semiconductor layer, data reading of the corresponding storage unit in the semiconductor device can be realized based on the control of the third gate. For example, when the read operation is performed, the third gate in the selected storage unit is set to a normal potential, and the third gate in the unselected storage unit is set to a low potential. In this way, for the unselected storage unit, the third gate with a low potential can attract more positive charges to ensure that no current passes through the second semiconductor layer in the unselected storage unit, thereby solving the multi-path problem caused by the read current bypassing the plurality of storage nodes when the read operation is performed, and avoiding the problem of interference between different storage units, thereby facilitating the improvement of the performance and reliability of the storage unit and the semiconductor device.

[0037] In addition, in the embodiments of the present disclosure, the fifth source / drain electrode and the common source line are electrically connected, which facilitates the connection of the corresponding adjacent plurality of storage units into a piece through the common source line, so as to solve the problem of current congestion and optimize the structure of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings of other embodiments can also be obtained by those skilled in the art without creative labor.

[0039] Figure 1 A structural schematic diagram of a semiconductor device provided in some embodiments of the present disclosure;

[0040] Figure 2 A structural schematic diagram of a semiconductor device provided in some embodiments of the present disclosure; Figure 1 A sectional schematic diagram of the structure shown in FIG. 1 on the M1 section;

[0041] Figure 3 An equivalent circuit schematic diagram of a semiconductor device provided in some embodiments of the present disclosure;

[0042] Figure 4 A sectional schematic diagram of the structure shown in FIG. 1 on the M1 section; Figure 1

[0043] A flowchart of a preparation method of a memory provided in some embodiments; Figure 5 Figure 5

[0044] Figure 6 Flowchart of another method of fabricating a memory provided in some embodiments;

[0045] Figure 7 Flowchart of step S100 in another method of fabricating a memory provided in some embodiments;

[0046] Figure 8 Cross-sectional view of a structure resulting from step S10 in a method of fabricating a memory provided in some embodiments;

[0047] Figure 9 Cross-sectional view of a structure resulting from step S20 in a method of fabricating a memory provided in some embodiments;

[0048] Figure 10 Cross-sectional view of a structure resulting from step S30 in a method of fabricating a memory provided in some embodiments;

[0049] Figure 11 Cross-sectional view of a structure resulting from step S40 in a method of fabricating a memory provided in some embodiments;

[0050] Figure 12 Cross-sectional view of a structure resulting from step S50 in a method of fabricating a memory provided in some embodiments;

[0051] Figure 13 Cross-sectional view of a structure resulting from step S60 in a method of fabricating a memory provided in some embodiments;

[0052] Figure 14 Cross-sectional view of a structure resulting from step S70 in a method of fabricating a memory provided in some embodiments;

[0053] Figure 15 Cross-sectional view of a structure resulting from step S80 in a method of fabricating a memory provided in some embodiments;

[0054] Figure 16 Cross-sectional view of a structure resulting from step S90 in a method of fabricating a memory provided in some embodiments;

[0055] Figure 17 Cross-sectional view of a structure resulting from step S101 in a method of fabricating a memory provided in some embodiments;

[0056] Figure 18 Cross-sectional view of a structure resulting from step S102 in a method of fabricating a memory provided in some embodiments;

[0057] Figure 19 A cross-sectional view of a structure obtained in step S130 of a method of manufacturing a memory according to some embodiments.

[0058] Reference signs:

[0059] 11 - first gate; 12 - first source / drain; 13 - second source / drain; 14 - first semiconductor layer; 15 - first gate dielectric layer;

[0060] 21 - second gate; 22 - third source / drain; 23 - fourth source / drain; 24 - second semiconductor layer; 25 - second gate dielectric layer;

[0061] 31 - third gate; 32 - fifth source / drain; 33 - sixth source / drain; 34 - third gate dielectric layer; 35 - fourth gate dielectric layer;

[0062] 1 - semiconductor material layer; 2 - gate dielectric material layer; 3 - second conductive material layer;

[0063] WL1 - first word line; WL2 - second word line; BL1 - first bit line; VBL1 - dummy first bit line; BL2 - second bit line; SL - common source line; A - first part; B - second part; G V - dummy gate; K1 - etching hole; C1 - accommodation space; L1 - dielectric material; R1 - first target region; R2 - second target region; R3 - third target region; R4 - fourth target region; R5 - fifth target region; T1 - write transistor; T2 - read transistor; T3 - read control transistor. DETAILED DESCRIPTION

[0064] For the purpose of promoting an understanding of the disclosure, the disclosure will now be described in greater detail with reference to the relevant drawings. The embodiments of the disclosure are shown in the drawings. However, the disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure will be more thoroughly and completely understood.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0066] The term "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0067] It is understood that the terms "first," "second," "third," "fourth," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0068] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0070] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0071] Currently, various 3D dynamic random access memories (DRAMs) are widely researched. Among them, the 3D-DRAM with a 2T0C structure. The principle is to use a write transistor to control the write operation, and the gate of the write transistor is connected to the write word line. After the write word line is set high, a certain voltage is input through the write bit line connected to the source and drain of the write transistor. This transistor usually uses a wide-bandgap oxide semiconductor to ensure that a small amount of charge can be locked on the gate of the read transistor and the wire connected thereto as a storage node after being turned off. Then data is read based on the read word line connected to the source and drain of the read transistor and the read bit line. However, the 3D-DRAM with a 2T0C structure is prone to problems such as multiple paths of read current and crowding of read current during data reading, thereby adversely affecting the performance of the DRAM.

[0072] Based on this, the semiconductor device, the memory and the preparation method thereof, and the electronic equipment provided by the embodiments of the present disclosure can be beneficial to improve the performance and reliability of the semiconductor device and the memory.

[0073] Please refer to Figure 1 and Figure 2 Some embodiments of the present disclosure provide a semiconductor device, comprising: a first gate 11, a second gate 21, a third gate 31, a first semiconductor layer 14, a second semiconductor layer 24, and a common source line SL. Wherein, the first semiconductor layer 14 is insulatively surrounded around the side wall of the first gate 11. The second gate 21 is located on the side of the first semiconductor layer 14 away from the first gate 11, and comprises: a first part A electrically connected with the first semiconductor layer 14, and a second part B located on the side of the first part A away from the first semiconductor layer 14 and electrically connected with the first part A. The second semiconductor layer 24 is insulatively surrounded around the side wall of the second part B and the bottom wall of the second part B away from the first part A. The third gate 31 and the common source line SL are spaced around the side of the second semiconductor layer 24 away from the side wall of the second part B, and the third gate 31 is insulated from the second semiconductor layer 24.

[0074] In some embodiments, please continue to refer to Figure 1 and Figure 2 The side of the first semiconductor layer 14 away from the first gate 11 and located away from the first part A is electrically connected with the first bit line BL1. The side of the second semiconductor layer 24 away from the bottom wall of the second part B is electrically connected with the second bit line BL2. Wherein, the first bit line BL1 and the second bit line BL2 are arranged in parallel and spaced apart, and extend along the first direction (for example, the X direction).

[0075] The first gate 11 and the first word line WL1 are electrically connected and extend along the third direction (for example, the Z direction). The center line of the surrounding of the first semiconductor layer 14 extends along the third direction (for example, the Z direction).

[0076] The second gate 21 extends along a second direction (e.g., Y direction), and the second semiconductor layer 24 extends along the second direction (e.g., Y direction) around the center line. The second direction (e.g., Y direction) intersects the first direction (e.g., X direction).

[0077] The third gate 31 and the center line of the common source line SL extend along the second direction (e.g., Y direction). The third gate 31 is electrically connected to the second word line WL2, and the second word line WL2 extends along a third direction (e.g., Z direction).

[0078] The common source line SL extends in a direction away from the second semiconductor layer 24. The third direction (e.g., Z direction) intersects the first direction (e.g., X direction) and the second direction (e.g., Y direction).

[0079] For example, the first word line WL1 and the first gate 11 can be formed synchronously. For example, the first word line WL1 and the first gate 11 can be an integrated structure formed synchronously by using a synchronous process.

[0080] In some embodiments, please refer to Figure 1 and Figure 2 The semiconductor device further includes a first gate dielectric layer 15, a second gate dielectric layer 25, and a third gate dielectric layer 34. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second gate 21 and the second semiconductor layer 24. The third gate dielectric layer 34 is located between the third gate 31 and the second semiconductor layer 24.

[0081] In some embodiments, please refer to Figure 1 and Figure 2 The second semiconductor layer 24 and the first semiconductor layer 14 have a spacing along the second direction (e.g., Y direction). The semiconductor device further includes a fourth gate dielectric layer 35 located in the spacing between the first semiconductor layer 14 and the second semiconductor layer 24 and covering the sidewall of the first portion A. The fourth gate dielectric layer 35 is connected to the second gate dielectric layer 25.

[0082] In some embodiments, please refer to Figure 1 and Figure 2 The size of the first portion A in the first direction (e.g., X direction) is greater than the size of the second portion B in the first direction (e.g., X direction). The size of the first portion A in the second direction (e.g., Y direction) is less than the size of the second portion B in the second direction (e.g., Y direction).

[0083] In some embodiments, the size of the first semiconductor layer 14 in the first direction (e.g., X direction) is greater than the maximum size of the second gate 21 in the first direction (e.g., X direction).

[0084] In some embodiments, please refer toFigure 2 and Figure 3 The semiconductor device further comprises a write transistor T1, a read transistor T2 and a read control transistor T3. The write transistor T1 comprises a first gate 11, a first source-drain 12 and a second source-drain 13. The first source-drain 12 is a part of the first semiconductor layer 14 facing away from the first gate 11 and located away from the first portion A, and the second source-drain 13 is a part of the first semiconductor layer 14 facing away from the first gate 11 and in contact with the first portion A. The read transistor T2 comprises a second gate 21, a third source-drain 22 and a fourth source-drain 23. The read control transistor T3 comprises a third gate 31, a fifth source-drain 32 and a sixth source-drain 33. The third source-drain 22 and the fifth source-drain 32 are parts of the second semiconductor layer 24 located around the second portion B and in contact with the common source line SL. The fourth source-drain 23 and the sixth source-drain 33 are parts of the second semiconductor layer 24 facing away from the bottom wall of the second portion B.

[0085] Here, it should be noted that Figure 2 understood that the fourth source-drain 23 and the sixth source-drain 33, as electrodes for connecting the second bit line BL2 in the corresponding transistors, can be composed of the same part or connected part of the second semiconductor layer 24; the third source-drain 22 and the fifth source-drain 32, as electrodes for connecting the common source line SL in the corresponding transistors, can be composed of the same part or connected part of the second semiconductor layer 24.

[0086] It can be understood that the semiconductor device can comprise one or more memory cells, each of which can comprise a write transistor T1, a read transistor T2 and a read control transistor T3. The first word line WL1 is electrically connected to the first gate 11 of the write transistor T1 and can serve as a write word line to control the write transistor T1 to be turned on in the write phase to realize data writing operation. The first bit line BL1 is in contact with the first source-drain 12 of the write transistor T1 and can serve as a write bit line to provide data to be written. The second word line WL2 is electrically connected to the third gate 31 of the read control transistor T3 and can serve as a read word line to control the read control transistor T3 to be turned on in the read phase to realize data reading operation. The second bit line BL2 is in contact with the fourth source-drain 23 of the read transistor T2 and can serve as a read bit line to provide data to be read.

[0087] In the embodiments of the present disclosure, a read control tube T3 is added in the storage unit, and the third gate 31 of the read control tube T3 is electrically connected with the second word line WL2 (i.e. the read word line). When the read operation is performed, the second word line WL2 in the selected storage unit is set to a normal potential, and the second word line WL2 in the unselected storage unit is set to a low potential. In this way, for the unselected storage unit, the low potential of the second word line WL2 can attract more positive charges from the channel of the read transistor connected to the third gate 31, so as to ensure that the read transistor in the unselected storage unit is in an electrically disconnected state, thereby solving the multi-path problem caused by the read current bypassing the storage nodes of multiple read transistors controlled by the same second word line WL2 during the read operation, and avoiding the problem of voltage drop of the target second bit line BL2 caused by the leakage current flowing out of each different second bit line BL2 (i.e. the read bit line) controlled by the same second word line WL2, and avoiding the interference problem between different storage units, thereby improving the performance and reliability of the storage unit and the memory.

[0088] In addition, in the embodiments of the present disclosure, the fifth source-drain electrode 32 of the read control tube T3 is electrically connected with the common source line SL, which is conducive to connecting the corresponding adjacent multiple storage units into a piece through the common source line SL, so as to solve the current congestion problem and optimize the structure of the memory.

[0089] In other embodiments, please refer to Figure 4 The semiconductor device further includes a write transistor T1 and a read transistor T2. The write transistor T1 includes a first gate 11, a first source-drain electrode 12, and a second source-drain electrode 13. The first source-drain electrode 12 is a part of the first semiconductor layer 14 away from the first gate 11 and located away from the first part A, and the second source-drain electrode 13 is a part of the first semiconductor layer 14 away from the first gate 11 and in contact with the first part A. The read transistor T2 includes a second gate 21, a third gate 31, a third source-drain electrode 22, and a fourth source-drain electrode 23. The third source-drain electrode 22 is a part of the second semiconductor layer 24 arranged on the circumferential side of the second part B and in contact with the common source line SL. The fourth source-drain electrode 23 is a part of the second semiconductor layer 24 away from the bottom wall of the second part B. The second gate 21 is the storage gate of the read transistor. The third gate 31 is the control gate of the read transistor.

[0090] It can be understood that the semiconductor device can include one or more memory cells, each of which can include a write transistor T1 and a read transistor T2. The first word line WL1 is electrically connected with the first gate 11 of the write transistor T1, and can serve as a write word line to control the write transistor T1 to be turned on in the write phase to realize the data write operation. The first bit line BL1 is in contact with the first source / drain 12 of the write transistor T1, and can serve as a write bit line to provide data to be written. The second word line WL2 is electrically connected with the third gate 31 of the read transistor T2, and can serve as a read word line to control the read transistor T2 to be turned on in the read phase to realize the data read operation. The second bit line BL2 is in contact with the fourth source / drain 23 of the read transistor T2, and can serve as a read bit line to provide data to be read.

[0091] In the embodiments of the present disclosure, the third gate 31 in the memory cell is electrically connected with the second word line WL2 (i.e., the read word line). When performing the read operation, the second word line WL2 in the selected memory cell is set to a normal potential, and the second word line WL2 in the unselected memory cell is set to a low potential. In this way, for the unselected memory cell, the low potential of the second word line WL2 corresponding to the connected third gate 31 can attract more positive charges away from the channel of the read transistor, to ensure that the read transistor in the unselected memory cell is in an electrically disconnected state, thereby solving the multi-path problem caused by the read current flowing through multiple storage nodes when the same second word line WL2 controls multiple read transistors during the read operation. In addition, the voltage drop problem of the target second bit line BL2 caused by the leakage current flowing out of each different second bit line BL2 (i.e., the read bit line) under the control of the same second word line WL2 can be avoided, and the interference problem between different memory cells can be avoided, thereby improving the performance and reliability of the memory cell and the memory.

[0092] In addition, in the embodiments of the present disclosure, the third source / drain 22 and the common source line SL are electrically connected, which is conducive to connecting the corresponding adjacent multiple memory cells into a piece through the common source line SL to solve the current congestion problem and optimize the structure of the memory.

[0093] According to some embodiments, another aspect of the present disclosure also provides a memory including the semiconductor device as described in any of the preceding embodiments. The semiconductor device has the technical advantages described above, and the memory also has the same advantages, which will not be described here in detail.

[0094] Some embodiments of the present disclosure also provide a preparation method of a memory for preparing the memory in some of the above embodiments. The memory has the technical advantages described above, and the preparation method also has the same advantages.

[0095] Please refer to Figure 5 and combine Figures 1-4 It should be understood that the preparation method includes steps S10-S90.

[0096] S10: Forming a first conductive material layer, and patterning the first conductive material layer to form a second bit line and a dummy first bit line arranged in parallel and spaced apart, and a dummy gate between the second bit line and the dummy first bit line and connecting the second bit line and the dummy first bit line. The second bit line and the dummy first bit line extend along a first direction, and the dummy gate extends along a second direction.

[0097] S20: Filling a dielectric material on both sides of the dummy gate opposite in the first direction.

[0098] S30: Etching the dummy gate and the dielectric material in a first target region of the dummy gate close to the dummy first bit line to form an etching hole.

[0099] S40: Based on the etching hole, performing a wet etching process along the second direction and the first direction on the dummy first bit line and the remaining dummy gate to form a containing space. The containing space exposes the corresponding sidewall of the second bit line.

[0100] S50: Depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in the containing space in sequence.

[0101] S60: Removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the first target region, and the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the second target region and the third target region adjacent to the first target region along the second direction, so that the remaining semiconductor material layer constitutes a second semiconductor layer, the remaining gate dielectric material layer constitutes a second gate dielectric layer, the second conductive material layer remaining on the side of the second target region close to the second bit line is a second part of a second gate, and the second conductive material layer remaining on the side of the third target region away from the second bit line is a first bit line.

[0102] S70: Forming a fourth gate dielectric layer on the sidewall of the second semiconductor layer and the second gate dielectric layer away from the second bit line. The fourth gate dielectric layer is connected with the second gate dielectric layer.

[0103] S80: Forming a first part of the second gate on the sidewall of the second target region between the second part and the fourth gate dielectric layer away from the second bit line.

[0104] S90: Etching the hole wall of the etching hole between the first part and the first bit line to form a first semiconductor layer, a first gate dielectric layer and a first gate in sequence.

[0105] In some embodiments, step S40 based on the etching hole, removing the dummy first bit line and the remaining dummy gate to form the containing space, further includes the following steps.

[0106] Performing a wet etching process in the second direction and the first direction on the dummy first bit line and the dummy gate reserved to form the accommodation space.

[0107] In some embodiments, referring to Figure 6 , the method for manufacturing the memory further comprises steps S100-S130.

[0108] S100: sequentially arranging a third gate dielectric layer and a third gate in a fourth target region on the side of the sidewall of the second semiconductor layer extending in the second direction and away from the second gate.

[0109] S110: forming a first word line electrically connected to the first gate.

[0110] S120: forming a second word line electrically connected to the third gate.

[0111] S130: forming a common source line in a fifth target region on the side of the first part of the second semiconductor layer. The common source line is arranged around the sidewall of the second semiconductor layer extending in the second direction and away from the second gate. The fifth target region is located in the interval between the fourth target region and the first part.

[0112] In some embodiments, referring to Figure 7 , the step S100 of sequentially arranging a third gate dielectric layer and a third gate in a fourth target region on the side of the sidewall of the second semiconductor layer extending in the second direction and away from the second gate comprises the following steps.

[0113] S101: etching the dielectric material in the third direction to expose the sidewall on the side of the second semiconductor layer in the fourth target region away from the second gate dielectric layer.

[0114] S102: depositing a third gate dielectric layer on the sidewall surface of the second semiconductor layer in the fourth target region away from the second gate dielectric layer. Depositing a third gate on the sidewall surface of the third gate dielectric layer away from the second semiconductor layer.

[0115] In order to more clearly illustrate the method for manufacturing the memory in some embodiments described above, some specific implementations of some steps are exemplarily given in some embodiments.

[0116] Figure 8 In step S10, referring to , a first conductive material layer (not shown) is formed, and the first conductive material layer is patterned to form a second bit line BL2 and a dummy first bit line VBL1 arranged in parallel and spaced apart, and a dummy gate GV located between the second bit line BL2 and the dummy first bit line VBL1 and connecting the second bit line BL2 and the dummy first bit line VBL1; wherein the second bit line BL2 and the dummy first bit line VBL1 extend in a first direction (for example, the X direction), and the dummy gate GV extends in a second direction (for example, the Y direction).

[0117] It is to be noted that, in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. That is, a plurality of first conductive material layers and a plurality of sacrificial layers are alternately stacked, and the sacrificial layers are removed according to requirements, so as to correspond to subsequent lateral etching of the first semiconductor material layers to obtain the first semiconductor layers of each transistor.

[0118] For example, the first conductive material layers include metal layers, such as tungsten metal layers.

[0119] For example, the sacrificial layers include, but are not limited to, silicon nitride layers.

[0120] Here, each first conductive material layer and each sacrificial layer can be formed by a deposition process, respectively.

[0121] In step S20, referring to Figure 9 , the virtual gate G V The opposite sides in the first direction (for example, the X direction) are filled with a dielectric material L1.

[0122] For example, the dielectric material L1 includes, but is not limited to, silicon oxide.

[0123] Here, the dielectric material L1 can be formed by a deposition process. After the dielectric material L1 is formed by the deposition process, a chemical mechanical polishing (CMP) process can be used to polish the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is flat.

[0124] In step S30, referring to Figure 10 , the virtual gate G V The virtual gate VG and the dielectric material L1 in the first target region R1 close to the virtual first bit line VBL1 are etched to form an etching hole K1.

[0125] Here, the etching hole K1 can be formed by dry etching.

[0126] In step S40, referring to Figure 11 , based on the etching hole K1, the virtual first bit line VBL1 and the retained virtual gate G V , a containing space C1 containing the etching hole K1 is formed; the containing space C1 exposes the corresponding sidewall of the second bit line BL2.

[0127] For example, based on the etching hole K1, the virtual first bit line VBL1 and the retained virtual gate G V , the containing space C1 is also formed by removing the virtual first bit line VBL1 and the retained virtual gate G VA wet etching process along the second direction (e.g., Y direction) and the first direction (e.g., X direction) is performed to form the accommodation space C1.

[0128] In step S50, referring to Figure 12 , the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 are sequentially deposited in the accommodation space C1.

[0129] For example, the semiconductor material layer 1 includes but is not limited to a metal oxide semiconductor layer, such as an Indium Gallium Zinc Oxide (IGZO) layer.

[0130] For example, the gate dielectric material layer 2 includes but is not limited to an HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, for example, greater than 3.9.

[0131] For example, the material of the second conductive material layer 3 includes but is not limited to tungsten.

[0132] Here, the ALD process can be used to sequentially deposit the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3.

[0133] In step S60, referring to Figure 13 , the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target region R1, and the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the second target region R2 and the third target region R3 adjacent to the first target region R1 along the second direction (e.g., Y direction) are removed, so that the remaining semiconductor material layer 1 constitutes the second semiconductor layer 24, the remaining gate dielectric material layer 2 constitutes the second gate dielectric layer 25, the second conductive material layer 3 remaining on the side of the second target region R2 close to the second bit line BL2 is the second part B of the second gate 21, and the second conductive material layer 3 remaining on the side of the third target region R3 away from the second bit line BL2 is the first bit line BL1.

[0134] Here, the dry etching can be used to remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target region R1, and then the wet etching is used to remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the second target region R2 and the third target region R3 along the second direction (e.g., Y direction), so that the second conductive material layer 3 remaining on the side of the second target region R2 close to the second bit line BL2 is the second part B of the second gate 21, and the second conductive material layer 3 remaining on the side of the third target region R3 away from the second bit line BL2 is the first bit line BL1.

[0135] In step S70, referring to Figure 14, the fourth gate dielectric layer 35 is connected with the second gate dielectric layer 25.

[0136] For example, the fourth gate dielectric layer 35 includes but is not limited to an HK dielectric layer.

[0137] In step S80, referring to Figure 15 , the first part A of the second gate 21 is formed on the second target region R2 between the second part B and the fourth gate dielectric layer 35 away from the sidewall of the read bit line BL2.

[0138] Here, the first part A of the second gate 21 is formed, and the second conductive material layer 3 is backfilled on the third target region R3.

[0139] In step S90, referring to Figure 16 , the first semiconductor layer 14, the first gate dielectric layer 15 and the first gate 11 are sequentially formed by etching the hole wall of the hole K1 between the first part A and the first bit line BL1.

[0140] For example, the first semiconductor layer 14 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0141] For example, the first gate dielectric layer 15 includes but is not limited to an HK dielectric layer.

[0142] For example, the material of the first gate 11 includes but is not limited to metal tungsten.

[0143] Here, the ALD process can be used to sequentially deposit the first semiconductor layer 14, the first gate dielectric layer 15 and the first gate 11.

[0144] In step S101, referring to Figure 17 , the dielectric material L1 is etched along the third direction (for example, the Z direction) to expose the circumferential sidewall of the second semiconductor layer 24 away from the second gate dielectric layer 25 on the fourth target region R4.

[0145] In step S102, referring to Figure 18 , the third gate dielectric layer 34 is deposited on the circumferential sidewall surface of the second semiconductor layer 24 away from the second gate dielectric layer 25 within the fourth target region R4, and the third gate 31 is deposited on the circumferential sidewall surface of the third gate dielectric layer 34 away from the second semiconductor layer 24.

[0146] For example, the third gate dielectric layer 34 includes but is not limited to an HK dielectric layer.

[0147] For example, the material of the third gate 31 includes but is not limited to metal tungsten.

[0148] The third gate dielectric layer 34 and the third gate 31 can be deposited by an ALD process.

[0149] In step S110, please refer to Figure 18 to form a first word line WL1 electrically connected to the first gate 11; the first word line WL1 extends along a third direction (for example, the Z direction).

[0150] For example, the material of the first word line WL1 includes but is not limited to tungsten.

[0151] Here, the first word line WL1 and the first gate 11 can be formed synchronously.

[0152] In step S120, please refer to Figure 18 to form a second word line WL2 electrically connected to the third gate 31; the second word line WL2 extends along the third direction (for example, the Z direction).

[0153] For example, the material of the second word line WL2 includes but is not limited to tungsten.

[0154] In step S130, please refer to Figure 19 to form a common source line SL in a fifth target region R5 near the write transistor T W on the side of the second semiconductor layer 24. The common source line SL surrounds the side wall on the side of the second semiconductor layer 24 extending along the second direction (for example, the Y direction) and away from the second gate 21. The fifth target region R5 is located in the interval between the fourth target region R4 and the write transistor T W .

[0155] Here, the common source line SL includes but is not limited to tungsten.

[0156] For example, forming the common source line SL in the fourth target region R4 near the write transistor T W on the side of the second semiconductor layer 24 includes: first etching the dielectric material L1 along the third direction (for example, the Z direction) to expose the side wall on the side of the second semiconductor layer 24 away from the second gate dielectric layer 25 in the fourth target region R4, and then backfilling the conductive material to form the common source line SL.

[0157] In which, please refer to Figure 19 in combination with Figure 2It is understood that, in some embodiments, the first gate 11, the first source / drain 12 and the second source / drain 13 constitute the write transistor T1. The first source / drain 12 is a portion of the first semiconductor layer 14 away from the first gate 11 and located away from the first part A, and the second source / drain 13 is a portion of the first semiconductor layer 14 away from the first gate 11 and in contact with the first part A. The second gate 21, the third source / drain 22 and the fourth source / drain 23 constitute the read transistor T2. The third gate 31, the fifth source / drain 32 and the sixth source / drain 33 constitute the read control transistor T3. Among them, the third source / drain 22 and the fifth source / drain 32 are portions of the second semiconductor layer 24 surrounding the second part B and in contact with the common source line SL. The fourth source / drain 23 and the sixth source / drain 33 are portions of the second semiconductor layer 24 away from the bottom wall of the second part B.

[0158] In other embodiments, please continue to refer to Figure 19 and in combination with Figure 4 It is understood that, in some embodiments, the first gate 11, the first source / drain 12 and the second source / drain 13 constitute the write transistor T1. The first source / drain 12 is a portion of the first semiconductor layer 14 away from the first gate 11 and located away from the first part A, and the second source / drain 13 is a portion of the first semiconductor layer 14 away from the first gate 11 and in contact with the first part A. The second gate 21, the third gate 31, the third source / drain 22 and the fourth source / drain 23 constitute the read transistor T2. The third source / drain 22 is a portion of the second semiconductor layer 24 surrounding the second part B and in contact with the common source line SL. The fourth source / drain 23 is a portion of the second semiconductor layer 24 away from the bottom wall of the second part B. Among them, the second gate 21 is the storage gate of the read transistor T1. The third gate 31 is the control gate of the read transistor T2.

[0159] Some embodiments of the present disclosure also provide an electronic device, comprising: one or more memories as described in the foregoing embodiments. For example, a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, etc. The electronic device can include a housing and a circuit board disposed in the housing, a memory or a data read / write circuit integrated on the circuit board. The structure of the memory can refer to the related description in some of the foregoing embodiments. The electronic device can also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0160] In some embodiments, the memory can be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory, and the processor can control the read / write operation of the memory.

[0161] In some embodiments, the memory is a 3D-DRAM.

[0162] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as there is no conflict, any combination of the technical features should be considered within the scope of the present disclosure.

[0163] The above-described embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these are within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line; wherein the first semiconductor layer is insulatively arranged around the side wall of the first gate; the second gate is located on the side of the first semiconductor layer away from the first gate, and comprises a first part electrically connected with the first semiconductor layer, and a second part located on the side of the first part away from the first semiconductor layer and electrically connected with the first part; the second semiconductor layer is insulatively arranged around the side wall of the second part and the bottom wall of the second part away from the first part; the third gate and the common source line are arranged around the side of the second semiconductor layer away from the side wall of the second part, and the third gate is insulated from the second semiconductor layer.

2. The semiconductor device according to claim 1, wherein the side of the first semiconductor layer away from the first gate and away from the first part is electrically connected with a first bit line; the side of the second semiconductor layer away from the bottom wall of the second part is electrically connected with a second bit line; wherein the first bit line and the second bit line are arranged in parallel and spaced apart, and extend along a first direction.

3. The semiconductor device according to claim 2, wherein the first gate is electrically connected with a first word line and extends along a third direction; the center line of the first semiconductor layer extends along the third direction; the second gate extends along a second direction, and the center line of the second semiconductor layer extends along the second direction; the second direction intersects the first direction; the center line of the third gate and the common source line extends along the second direction; the third gate is electrically connected with a second word line, and the second word line extends along the third direction; the common source line extends in a direction away from the second semiconductor layer; the third direction intersects the first direction and the second direction.

4. The semiconductor device according to claim 3, wherein The semiconductor device further comprises a write transistor, a read transistor and a read control transistor; wherein the write transistor comprises the first gate, a first source-drain electrode and a second source-drain electrode; the first source-drain electrode is a part of the first semiconductor layer away from the first gate and away from the first part, and the second source-drain electrode is a part of the first semiconductor layer away from the first gate and in contact with the first part; the read transistor comprises the second gate, a third source-drain electrode and a fourth source-drain electrode; the read control transistor comprises the third gate, a fifth source-drain electrode and a sixth source-drain electrode; wherein the third source-drain electrode and the fifth source-drain electrode are parts of the second semiconductor layer arranged around the second part and in contact with the common source line; and the fourth source-drain electrode and the sixth source-drain electrode are parts of the second semiconductor layer away from the bottom wall of the second part.

5. The semiconductor device of claim 3, wherein The semiconductor device further comprises a write transistor and a read transistor; wherein The write transistor comprises the first gate, a first source-drain electrode and a second source-drain electrode; the first source-drain electrode is a part of the first semiconductor layer away from the first gate and located away from the first part, and the second source-drain electrode is a part of the first semiconductor layer away from the first gate and in contact with the first part; The read transistor comprises the second gate, the third gate, a third source-drain electrode and a fourth source-drain electrode; the third source-drain electrode is a part of the second semiconductor layer arranged around the second part and in contact with the common source line; and the fourth source-drain electrode is a part of the second semiconductor layer away from the bottom wall of the second part; The second gate is a storage gate of the read transistor, and the third gate is a control gate of the read transistor.

6. The semiconductor device according to claim 4 or 5, wherein Further comprising a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer; wherein, The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second gate and the second semiconductor layer; The third gate dielectric layer is located between the third gate and the second semiconductor layer.

7. The semiconductor device of claim 6, wherein, The second semiconductor layer and the first semiconductor layer have a spacing along the second direction; the semiconductor device further comprises a fourth gate dielectric layer located in the spacing between the first semiconductor layer and the second semiconductor layer and covering the sidewall of the first part; The fourth gate dielectric layer is connected with the second gate dielectric layer.

8. The semiconductor device of claim 4 or 5, wherein, The size of the first part in the first direction is greater than the size of the second part in the first direction; The size of the first part in the second direction is less than the size of the second part in the second direction.

9. The semiconductor device according to claim 4 or 5, wherein The size of the first semiconductor layer in the first direction is greater than the maximum size of the second gate in the first direction.

10. A memory, comprising: The semiconductor device comprises: The semiconductor device of any one of claims 1-9.

11. A method of producing a memory, characterized by, The semiconductor device comprises: forming a first conductive material layer, and patterning the first conductive material layer to form a second bit line and a virtual first bit line arranged in parallel and spaced apart, and a virtual gate located between the second bit line and the virtual first bit line and connecting the second bit line and the virtual first bit line; wherein the second bit line and the virtual first bit line extend along a first direction, and the virtual gate extends along a second direction; the second direction intersects the first direction; filling a dielectric material on both sides of the virtual gate in the first direction; etching the virtual gate and the dielectric material in a first target area of the virtual gate close to the virtual first bit line to form an etching hole; based on the etching hole, performing a wet etching process along the second direction and the first direction on the virtual first bit line and the remaining virtual gate to form a containing space; the containing space exposes the corresponding sidewall of the second bit line; sequentially depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in the containing space; removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the first target region and the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the second target region and the third target region adjacent to the first target region along the second direction, so that the remaining semiconductor material layer forms a second semiconductor layer, the remaining gate dielectric material layer forms a second gate dielectric layer, the second conductive material layer remaining on the side of the second target region close to the second bit line forms a second part of a second gate, and the second conductive material layer remaining on the side of the third target region away from the second bit line forms the first bit line; forming a fourth gate dielectric layer on the sidewall of the second semiconductor layer and the second gate dielectric layer away from the second bit line; the fourth gate dielectric layer is connected with the second gate dielectric layer; forming a first part of the second gate on the sidewall of the second target region between the second part and the fourth gate dielectric layer away from the second bit line; forming a first semiconductor layer, a first gate dielectric layer and a first gate in sequence on the hole wall of the etching hole between the first part and the first bit line.

12. The method of claim 11, wherein the method further comprises: Further comprising: forming a third gate dielectric layer and a third gate in sequence around the fourth target region on the sidewall of the second semiconductor layer extending along the second direction and away from the second gate; forming a first word line electrically connected with the first gate; forming a second word line electrically connected with the third gate; forming a common source line in the fifth target region on the sidewall of the second semiconductor layer close to the first part; the common source line is arranged around the sidewall of the second semiconductor layer extending along the second direction and away from the second gate; the fifth target region is located in the interval between the fourth target region and the first part.

13. The method of claim 12, wherein the method further comprises: The forming a third gate dielectric layer and a third gate in sequence around the fourth target region on the sidewall of the second semiconductor layer extending along the second direction and away from the second gate comprises: etching the dielectric material along a third direction to expose the sidewall of the second semiconductor layer in the fourth target region away from the second gate dielectric layer; the third direction intersects with the first direction and the second direction; depositing a third gate dielectric layer on the sidewall surface of the second semiconductor layer in the fourth target region away from the second gate dielectric layer, and depositing a third gate on the sidewall surface of the third gate dielectric layer away from the second semiconductor layer.

14. The method of claim 11, wherein the method further comprises: The removing the virtual first bit line and the remaining virtual gate based on the etching hole to form a containing space further comprises: performing a wet etching process along the second direction and the first direction on the virtual first bit line and the remaining virtual gate to form the containing space.

15. An electronic device, comprising: Comprise: one or more memories as claimed in claim 10.

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