Method for manufacturing capacitor
By depositing an oxide layer on the lower electrode layer of the DRAM capacitor and replacing the oxygen-containing wet etching process with an oxygen-containing wet etching process, the problem of capacitance shaking and difficulty in reducing the thickness of the lower electrode is solved, and the good electrical properties and structural stability of the capacitor are achieved.
Patent Information
- Application Number
- CN202411933093.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-23
- Filing Date
- 2024-12-26
- Publication Date
- 2025-03-28
AI Technical Summary
In the prior art, the lower electrode of the DRAM capacitor is unevenly consumed by the oxygen-containing wet etching process, resulting in capacitance shaking problems, and at the same time, the lower electrode thickness is difficult to reduce to achieve an ideal capacitance value.
By depositing an oxide layer on the lower electrode layer and replacing the oxygen-containing wet etching process with an oxygen-free wet etching process, the consumption of the oxidized lower electrode is reduced and the lower electrode thickness is reduced to achieve an ideal capacitance value.
The capacitor shaking problem caused by uneven consumption of the capacitor under the oxidation of the capacitor is effectively reduced, and the capacitor achieves good electrical properties and structural stability by reducing the thickness of the lower electrode.
Smart Images
Figure CN119730239A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a capacitor. Background Art
[0002] Dynamic random access memory (DRAM) is a semiconductor device used to store data bits in cell capacitors within an integrated circuit. DRAM generally includes trench capacitor DRAM cells and / or stack capacitor DRAM cells. Summary of the invention
[0003] Some embodiments of the present invention provide a method for manufacturing a capacitor. This method allows the capacitor to be manufactured without increasing the thickness of the capacitor's lower electrode by depositing an oxide layer on the lower electrode layer and replacing the oxygen-containing wet etching process with an oxygen-free wet etching process. In this way, this method can reduce the problem of capacitor shaking caused by uneven consumption of the capacitor's oxidized lower electrode by the oxygen-containing wet etching process. Furthermore, this method can reduce the thickness of the capacitor's lower electrode to achieve an ideal capacitance value. This method can provide an effective solution to enable the capacitor to achieve good electrical performance and structural stability.
[0004] Some embodiments of the present invention provide a method for manufacturing a capacitor. The method includes: forming a mold on an inner connection layer; forming a groove in the mold; depositing a lower electrode layer on the mold and in the groove; disposing a metal oxide layer on the lower electrode layer and in the groove; forming a surface oxide layer on the metal oxide layer; and performing an oxygen-free wet etching process to remove the surface oxide layer, the metal oxide layer and the mold from the lower electrode layer.
[0005] According to some embodiments of the present invention, the method further includes: before depositing the lower electrode layer, lowering the upper surface of the mold.
[0006] According to some embodiments of the present invention, the method further includes: forming a dielectric layer on the lower electrode layer after the oxygen-free wet etching process.
[0007] According to some embodiments of the present invention, the method further includes: depositing a top electrode layer on the dielectric layer.
[0008] According to some embodiments of the present invention, the interconnect layer includes a metal feature, and the forming of the recess is performed such that the recess is directly above the metal feature.
[0009] According to some embodiments of the present invention, the depositing of the lower electrode layer is performed such that the lower electrode layer contacts the upper surface of the mold.
[0010] According to some embodiments of the present invention, the lower electrode layer includes a metal nitride layer.
[0011] According to some embodiments of the present invention, the thickness of the metal oxide layer is to
[0012] According to some embodiments of the present invention, the metal oxide layer comprises titanium oxide.
[0013] According to some embodiments of the present invention, the depositing of the lower electrode layer is performed so that a side surface of the lower electrode layer contacts the mold.
[0014] According to some embodiments of the present invention, the forming of the surface oxide layer is performed such that the metal oxide layer separates the surface oxide layer from the lower electrode layer.
[0015] Some embodiments of the present invention provide a method for manufacturing a capacitor, which includes: forming a mold on an inner connection layer; depositing a lower electrode layer on the mold; disposing a metal oxide layer on the upper surface of the lower electrode layer, wherein the metal oxide layer is in direct contact with the lower electrode layer; oxidizing the upper surface of the metal oxide layer; and etching the metal oxide layer and the mold from the lower electrode layer.
[0016] According to some embodiments of the present invention, the lower electrode layer includes a metal silicon nitride layer.
[0017] According to some embodiments of the present invention, etching the metal oxide layer is performed by using an oxygen-free etchant.
[0018] According to some embodiments of the present invention, the thickness of the metal oxide layer is to BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The present invention is in accordance with the attached Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
[0020] Figure 1 The figure is a flow chart of a method for manufacturing a capacitor according to some embodiments of the present invention.
[0021] Figures 2 to 7 2 are cross-sectional views of capacitors at various stages of the process according to some embodiments of the present invention.
[0022] Figure 8 According to some embodiments of the present invention, Figure 7 A cross-sectional view along line A-A'. DETAILED DESCRIPTION
[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific embodiments of the components and configurations described herein are to simplify the present invention. Of course, these are only embodiments and are not intended to be limiting. For example, the process accompanying the formation of a first feature above a second feature in the description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature formed between the first feature and the second feature makes it possible that the first feature and the second feature will not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in different embodiments. This repetition is for the purpose of simplification and clarity and this repetition itself does not specify the relationship between different embodiments and / or the configurations discussed.
[0024] Furthermore, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are also intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. As used herein, "approximately," "about," "approximately," or "substantially" shall generally refer to within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate, meaning that in the absence of explicit provisions, the terms "approximately," "about," "approximately," or "substantially" may be inferred.
[0025] Figure 1 FIG. 1 is a flow chart of a method 100 for manufacturing a capacitor 200 according to some embodiments of the present invention. Figures 2 to 7 2 is a cross-sectional view of a capacitor 200 at various stages of the process according to some embodiments of the present invention. This description is for illustrative purposes only and is not intended to further limit the contents of the appended claims. It should be understood that in Figure 1 Additional operations may be added before, during and after operations S1 to S6 in the above description, and some of the operations S1 to S6 mentioned below may be replaced or cancelled. The order of the steps / procedures may be changed.
[0026] Reference Figure 1 as well as Figure 2The method 100 begins with operations S1 and S2, wherein a semiconductor substrate (not shown) is provided and an interconnect layer 220 is formed on the semiconductor substrate (not shown). The interconnect layer 220 may include a dielectric material 222 and a metal feature 224 surrounded by the dielectric material 222. The interconnect layer 220 may be formed by etching a recess / opening in the dielectric material 222, depositing a conductive material of the metal feature 224 in the recess / opening, and then removing excess conductive material by a planarization process. In some embodiments, the dielectric material 222 may include silicon oxide. In some embodiments, the conductive material of the metal feature 224 may include a metal deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like or a combination thereof. A dielectric liner 226 may be disposed between the metal feature 224 and the dielectric material 222. The dielectric liner 226 may be a nitride, such as silicon nitride (SiN).
[0027] The method 100 proceeds to operation S3, where a mold 250 is formed on the interconnect layer 220. The mold 250 may be a material that can be easily removed by a wet etching process. For example, in other embodiments, the mold 250 may be an oxide, such as silicon oxide (SiO2), borophosphosilicate glass (BPSG), undoped silicon glass (USG), phosphosilicate glass (PSG), or a similar or combined material thereof. However, it should be noted that the mold 250 may be made of any appropriate material without limitation thereto.
[0028] The method 100 proceeds to operation S4, where the groove 270 is formed in the mold 250. For example, in some embodiments, a photolithography process is performed to form a photoresist layer on the mold 250. The photolithography process may include steps of coating light, exposing, developing, baking, the like, or a combination thereof. After the photolithography process, the mold 250 is etched through the photoresist layer. Furthermore, the groove 270 is formed in the mold 250 and is directly located on the metal feature 224.
[0029] The method 100 proceeds to operation S5, where a lower electrode layer 260 is conformally deposited on the mold 250 and in the groove 270. The lower electrode layer 260 may include a suitable conductive material. The lower electrode layer 260 may include a metal nitride layer or a metal silicon nitride layer, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), similar or combined materials thereof. The material of the lower electrode layer 260 may be selected for better etching resistance and high oxidation resistance. The lower electrode layer 260 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), similar or combined processes thereof. In the present embodiment, the lower electrode layer 260 contacts the upper surface of the mold 250, and the side surface of the lower electrode layer 260 contacts the mold 250. The thickness of the lower electrode layer 260 may be adjusted according to functional requirements. For example, in some embodiments, the thickness of the lower electrode layer 260 can be controlled by the number of ALD cycles.
[0030] In some embodiments, the method 100 further includes performing a planarization process on the upper surface of the mold 250 before depositing the lower electrode layer 260. The planarization process can lower the upper surface of the mold 250. For example, in some embodiments, the planarization process can be chemical-mechanical polishing (CMP). In other embodiments, the planarization process can be omitted.
[0031] Reference Figure 1 as well as Figure 3 The method 100 proceeds to operation S6, wherein after the lower electrode layer 260 is deposited, a metal oxide layer 280 is disposed on the lower electrode layer 260 and in the groove 270. The metal oxide layer 280 may include titanium oxide (TiO x ). The metal oxide layer 280 may be deposited by CVD, ALD, PVD, or similar or combined processes. In the present embodiment, the metal oxide layer 280 is conformally deposited on the upper surface of the lower electrode layer 260, wherein the metal oxide layer 280 is in direct contact with the lower electrode layer 260. Furthermore, the thickness of the metal oxide layer 280 may be changed according to functional requirements. For example, in some embodiments, the thickness of the metal oxide layer 280 may be controlled by the number of ALD cycles, and the thickness of the metal oxide layer 280 may be approximately to However, it should be noted that the metal oxide layer 280 may be formed using any appropriate process and is not limited thereto.
[0032] The configuration of the metal oxide layer 280 can prevent the lower electrode layer 260 from being oxidized.
[0033] Reference Figure 1 as well as Figure 4 , the method 100 proceeds to operation S7, wherein a surface oxide layer 290 is formed on the metal oxide layer 280. In detail, in this process, the upper surface of the metal oxide layer 280 is oxidized to form the surface oxide layer 290. Due to the presence of the metal oxide layer 280, the metal oxide layer 280 can separate the surface oxide layer 290 from the lower electrode layer 260. In this way, the surface oxide layer 290 can prevent the lower electrode layer 260 from being oxidized. In the present embodiment, the surface oxide layer 290 is conformally formed on the upper surface of the metal oxide layer 280, wherein the surface oxide layer 290 is in direct contact with the metal oxide layer 280.
[0034] Reference Figure 1 as well as Figure 5 , the method 100 may further include, after operation S7, patterning the lower electrode layer 260, the metal oxide layer 280, and the surface oxide layer 290 into a plurality of separate stacks. For example, a photolithography process is performed to form a photoresist layer on the surface oxide layer 290. The photolithography process may include the steps of coating light, exposing, developing, baking, the like, or a combination thereof. The photoresist layer may cover the surface oxide layer 290, the metal oxide layer 280, and a first portion of the lower electrode layer 260, and expose the surface oxide layer 290, the metal oxide layer 280, and a second portion of the lower electrode layer 260. After forming the photoresist layer, an etching process is performed to remove the surface oxide layer 290, the metal oxide layer 280, and the second portion of the lower electrode layer 260. The surface oxide layer 290, the metal oxide layer 280, and the first portion of the lower electrode layer 260 are retained.
[0035] In addition, in other embodiments, the method 100 may further include a planarization process or an etch-back process to remove the top portion of the lower electrode layer 260, the top portion of the metal oxide layer 280, and the top portion of the surface oxide layer 290 on the upper surface of the mold 250. For example, the planarization process may include a CMP process. The top portion of the lower electrode layer 260, the top portion of the metal oxide layer 280, and the top portion of the surface oxide layer 290 may be subjected to an etch-back process or a CMP process until the upper surface of the mold 250 is exposed.
[0036] Reference Figure 1 as well as Figure 6, the method 100 proceeds to operation S8, wherein an oxygen-free wet etching process is performed to remove the surface oxide layer 290, the metal oxide layer 280, and the mold 250 from the lower electrode layer 260, and expose the metal features 224 of the inner connection layer 220. In detail, the oxygen-free wet etching process may include an oxygen-free etchant, such as hydrofluoric acid, a hydrofluoric acid-based, an etchant similar to or in combination thereof. In the etching process, the oxygen-free wet etching process can avoid oxidation of the lower electrode layer 260, thereby reducing the problem of uneven consumption of the oxidized lower electrode layer 260 of the capacitor 200 by the oxygen-containing wet etching process. However, it should be noted that the oxygen-free wet etching process can use any appropriate oxygen-free etchant to remove the surface oxide layer 290, the metal oxide layer 280, and the mold 250.
[0037] Furthermore, after the oxygen-free wet etching process, due to the protection of the surface oxide layer 290 and the metal oxide layer 280, the lower electrode layer 260 can maintain good thickness uniformity. In this way, the method 100 can improve the capacitance swing problem of the capacitor 200 while maintaining the thickness of the lower electrode layer 260, and enable the capacitor 200 to achieve good electrical performance and structural stability. In other words, by performing the method 100 to maintain good thickness uniformity, the size of the lower electrode layer 260 can be reduced, so that the size of the capacitor 200 can be reduced while maintaining the capacitance value.
[0038] Figure 8 According to some embodiments of the present invention, Figure 7 A cross-sectional view of line A-A'. Figure 7 as well as Figure 8 The method 100 further includes forming a dielectric layer 700 on the lower electrode layer 260 after the oxygen-free wet etching process. For example, the dielectric layer 700 may be conformally disposed above and around the lower electrode layer 260. In other embodiments, the dielectric layer 700 also overlaps the metal features 224 of the interconnect layer 220. In some embodiments, the dielectric layer 700 may include a high-k material. In other embodiments, the dielectric layer 700 may include a low-k material.
[0039] The method 100 further includes disposing a top electrode layer 800 on the dielectric layer 700. For example, the top electrode layer 800 is conformally disposed on the dielectric layer 700 and surrounds the bottom electrode layer 260. In other embodiments, the top electrode layer 800 also overlaps the metal feature 224 of the interconnect layer 220. In some embodiments, the top electrode layer 800 may include the same material as the bottom electrode layer 260. Figure 8 As shown, the dielectric layer 700 surrounds the lower electrode layer 260 , and the upper electrode layer 800 surrounds the dielectric layer 700 , thereby forming the capacitor 200 .
[0040] Some embodiments of the present invention provide a method for manufacturing a capacitor. This method allows the capacitor to be manufactured without increasing the thickness of the capacitor's lower electrode by depositing an oxide layer on the lower electrode layer and replacing the oxygen-containing wet etching process with an oxygen-free wet etching process. In this way, this method can reduce the problem of capacitor shaking caused by uneven consumption of the capacitor's oxidized lower electrode by the oxygen-containing wet etching process. Furthermore, this method can reduce the thickness of the capacitor's lower electrode to achieve an ideal capacitance value. This method can provide an effective solution to enable the capacitor to achieve good electrical performance and structural stability.
[0041] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present application. Those skilled in the art will appreciate that they can easily use the present application as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present application, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present application.
[0042]
Explanation of symbols
[0043] 100: Methods
[0044] S1, S2, S3, S4, S5, S6, S7, S8: Operation
[0045] 200: Capacitor
[0046] 220: Inner connection layer
[0047] 222: Dielectric Materials
[0048] 224: Metal Characteristics
[0049] 226: Dielectric liner
[0050] 250: Mould
[0051] 260: Lower electrode layer
[0052] 270: Groove
[0053] 280: Metal oxide layer
[0054] 290: Surface oxide layer
[0055] 700: Dielectric layer
[0056] 800: upper electrode layer.
Claims
1. A method for manufacturing a capacitor, characterized in that: include: forming a mold on the inner connection layer; forming a groove in the mold; Depositing a lower electrode layer on the mold and in the groove; Disposing a metal oxide layer on the lower electrode layer and in the groove; forming a surface oxide layer on the metal oxide layer; as well as An oxygen-free wet etching process is performed to remove the surface oxide layer, the metal oxide layer and the mold from the lower electrode layer.
2. The method according to claim 1, characterized in that Also includes: Prior to depositing the lower electrode layer, the upper surface of the mold is lowered.
3. The method according to claim 1, characterized in that Also includes: After the oxygen-free wet etching process, a dielectric layer is formed on the lower electrode layer.
4. The method according to claim 3, characterized in that Also includes: A top electrode layer is deposited on the dielectric layer.
5. The method according to claim 1, characterized in that The interconnect layer includes a metal feature, and forming the recess is performed such that the recess is directly above the metal feature.
6. The method according to claim 1, characterized in that Depositing the lower electrode layer is performed such that the lower electrode layer contacts the upper surface of the mold.
7. The method according to claim 1, characterized in that The lower electrode layer includes a metal nitride layer.
8. The method according to claim 1, characterized in that The thickness of the metal oxide layer is to 9. The method according to claim 1, characterized in that: The metal oxide layer includes titanium oxide.
10. The method according to claim 1, characterized in that Depositing the lower electrode layer is performed such that a side surface of the lower electrode layer contacts the mold.
11. The method according to claim 10, characterized in that The forming of the surface oxide layer is performed such that the metal oxide layer separates the surface oxide layer from the lower electrode layer.
12. A method for manufacturing a capacitor, characterized in that: include: forming a mold on the inner connection layer; depositing a lower electrode layer on the mold; Disposing a metal oxide layer on the upper surface of the lower electrode layer, wherein the metal oxide layer is in direct contact with the lower electrode layer; oxidizing the upper surface of the metal oxide layer; as well as The metal oxide layer and the mold are etched away from the lower electrode layer.
13. The method according to claim 12, characterized in that The lower electrode layer includes a metal silicon nitride layer.
14. The method according to claim 12, characterized in that The metal oxide layer is etched using an oxygen-free etchant.
15. The method according to claim 12, characterized in that The thickness of the metal oxide layer is to