Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor device includes: a semiconductor layer; the first gate structure, the second gate structure and the third gate structure are located on the semiconductor layer; the doped region is located in the semiconductor layer; the first dielectric layer is at least located on the side wall of the first gate structure, and the second dielectric layer is at least located on the third gate structure; the side wall contact layer is located on the first dielectric layer, and the electrode layer is located on the second dielectric layer; wherein the electrode layer, the second dielectric layer and the third gate structure form a capacitor structure, and the electrode layer controls an electrode to be led out through the third gate structure; the first dielectric layer and the second dielectric layer are formed at the same time, and the side wall contact layer and the electrode layer are formed at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] OTP (One Time Programmable) device is a kind of storage device, which is relative to multiple-time programming (MTP). Its programming process is an irreversible activity. It is suitable for applications where the program is fixed and is widely used because of its low cost.

[0003] Existing OTP devices have the problem that the initial current is too high and cannot be removed. The initial current of the OTP device is too high, which will cause the problem of passive encoding of non-encoded bytes (bits) adjacent to the encoded bytes (bits) when the OTP device is programmed, which will cause confusion in the encoding and cause storage information errors.

[0004] The current method to solve the problem of too high initial current in OTP devices includes ultraviolet (UV) erasing, but its effect in erasing the initial current is not obvious. Summary of the invention

[0005] In view of the above problems, the purpose of the present application is to provide a semiconductor device and a method for preparing the same, wherein an electrode layer is formed on the third gate structure, and the electrode layer is led out through the third gate structure control electrode to achieve a limited number of erasing and writing of the OTP structure.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor layer; a first gate structure, a second gate structure and a third gate structure, which are located on the semiconductor layer; a doped region, which is located in the semiconductor layer; a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is at least located on the side wall of the first gate structure, and the second dielectric layer is at least located on the third gate structure; and a side wall contact layer and an electrode layer, wherein the side wall contact layer is located on the first dielectric layer, and the electrode layer is located on the second dielectric layer; wherein the electrode layer, the second dielectric layer and the third gate structure constitute a capacitor structure, and the electrode layer is led out via the third gate structure to control the electrode; the first dielectric layer and the second dielectric layer are formed simultaneously, and the side wall contact layer and the electrode layer are formed simultaneously.

[0007] Optionally, the semiconductor layer, the second gate structure and the doped regions on both sides of the second gate structure constitute a selection transistor of an OTP structure; the semiconductor layer, the third gate structure and the doped regions on both sides of the third gate structure constitute a floating gate transistor of an OTP structure, and the source region of the floating gate transistor is connected to the drain region of the selection transistor; before programming the OTP structure, the third gate structure controls the electrode to apply a positive voltage to clear the initial charge in the floating gate.

[0008] Optionally, the semiconductor layer, the second gate structure and the doped regions on both sides of the second gate structure constitute a selection transistor of an OTP structure; the semiconductor layer, the third gate structure and the doped regions on both sides of the third gate structure constitute a floating gate transistor of an OTP structure, and the source region of the floating gate transistor is connected to the drain region of the selection transistor; after the OTP structure is programmed, the third gate structure controls the electrode to apply a negative voltage to maintain the electrons in the floating gate.

[0009] Optionally, the semiconductor layer, the second gate structure and the doped regions on both sides of the second gate structure constitute a selection transistor of an OTP structure; the semiconductor layer, the third gate structure and the doped regions on both sides of the third gate structure constitute a floating gate transistor of an OTP structure, and the source region of the floating gate transistor is connected to the drain region of the selection transistor; the third gate structure controls the electrode to apply a positive voltage to clear electrons in the floating gate.

[0010] Optionally, the second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; the third gate structure control electrode contacts the electrode layer between the third gate structure and the second gate structure.

[0011] Optionally, the first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; and the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

[0012] According to another aspect of the present invention, a method for preparing a semiconductor device is provided, comprising: forming a first gate structure, a second gate structure and a third gate structure on a semiconductor layer; forming a doped region in the semiconductor layer; forming a first dielectric layer at least on a side wall of the first gate structure, and forming a second dielectric layer at least on the third gate structure, the first dielectric layer and the second dielectric layer being formed simultaneously; forming a side wall contact layer on the first dielectric layer, and forming an electrode layer on the second dielectric layer, the side wall contact layer and the electrode layer being formed simultaneously; wherein the electrode layer, the second dielectric layer and the third gate structure constitute a capacitor structure, and the electrode layer is led out via a control electrode of the third gate structure.

[0013] Optionally, the steps of forming the first dielectric layer, the second dielectric layer, the sidewall contact layer and the electrode layer include: forming a dielectric layer on the semiconductor layer and the first gate structure, the second gate structure and the third gate structure, the dielectric layer conformally covering the semiconductor layer and the first gate structure, the second gate structure and the third gate structure; forming a polysilicon layer on the dielectric layer; forming a patterned mask layer on the polysilicon layer; etching the polysilicon layer and the dielectric layer through the patterned mask layer to form a first dielectric layer, a polysilicon layer located on the first dielectric layer, a second dielectric layer and a polysilicon layer located on the second dielectric layer, wherein the first dielectric layer at least covers the sidewall of the first gate structure, and the second dielectric layer at least covers the third gate structure; alloying the polysilicon layer on the first dielectric layer and the polysilicon layer on the second dielectric layer to form a sidewall contact layer on the first dielectric layer and an electrode layer on the second dielectric layer.

[0014] Optionally, the second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; the third gate structure control electrode contacts the electrode layer between the third gate structure and the second gate structure.

[0015] Optionally, the first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; and the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

[0016] The unexpected technical effects of this application are: According to the semiconductor device and the preparation method thereof of the embodiments of the present invention, the electrode layer on the second dielectric layer and the third gate structure (floating gate) form upper and lower electrode plates, the electrode layer on the second dielectric layer, the second dielectric layer and the third gate structure (floating gate) form a capacitor structure, and the upper plate (electrode layer) of the capacitor structure is led out via the third gate structure control electrode.

[0017] Before the OTP structure is encoded, a positive voltage is applied to the control electrode of the third gate structure. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer, the second dielectric layer and the third gate structure (floating gate). The electrons in the third gate structure (floating gate) move upward, and the electrons break through the potential barrier of the third gate structure (floating gate) / second dielectric layer (especially SiON) and are lost in large quantities, thereby achieving the effect of clearing the charge in the third gate structure (floating gate).

[0018] After the OTP structure is encoded, due to the high-k nature of the second dielectric layer (especially the dielectric layer SiON), it is difficult for the electrons in the third gate structure (floating gate) to break through the second dielectric layer, especially the potential barrier of the dielectric layer (SiON). Further, after the OTP structure is encoded, a negative voltage can be applied to the control electrode of the third gate structure, and an upward electric field is formed in the capacitor structure formed by the electrode layer on the second dielectric layer, the second dielectric layer and the third gate structure (floating gate), thereby suppressing the loss of electrons in the third gate structure (floating gate) and further improving the reliability of the data retention capability of the OTP structure.

[0019] In this embodiment, since an electrode layer is provided above the third gate structure (floating gate), and a third gate structure control electrode connected to the electrode layer above the third gate structure (floating gate) is provided, the OTP structure can achieve a limited number of erasures and writes, further greatly improving the fault tolerance of the OTP structure. Specifically, when the OTP structure is coded incorrectly, a positive voltage is applied to the third gate structure control electrode. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer, the second dielectric layer, and the third gate structure (floating gate). The electrons introduced by programming in the third gate structure (floating gate) move upward, and the electrons break through the third gate structure (floating gate) / second dielectric layer (especially dielectric layer SiON) potential barrier and flow out, achieving the effect of electronic erasure, further enabling the OTP structure to achieve a limited number of repeated programming.

[0020] Furthermore, the electrode layer covers the top and side walls of the third gate structure (floating gate), that is, the electrode layer completely covers the third gate structure (floating gate), so that the third gate structure can control the electrode to apply a small voltage to erase the charge in the third gate structure (floating gate) and maintain the stored charge.

[0021] Furthermore, the electrode layer on the top of the third gate structure (floating gate) extends to above the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), and above the second gate structure (select gate). The third gate structure control electrode can be arranged between the second gate structure (select gate) and the third gate structure (floating gate). On the one hand, the arrangement of the third gate structure control electrode will not affect the lead-out of other electrodes (such as the select gate electrode, the second source electrode and the second drain electrode), and the overall area and the overall structure of the electrode structure of the OTP structure will not be affected. On the other hand, the third gate structure control electrode is arranged between the second gate structure (select gate) and the third gate structure (floating gate), so that the bottom of the third gate structure control electrode is connected to the planar electrode layer, which is more conducive to the etching of the third gate structure control electrode.

[0022] Furthermore, the second dielectric layer is located on the third gate structure (floating gate) and extends to the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), thereby preventing the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate) from forming silicide, thereby affecting the conduction of the channel between the second gate structure (select gate) and the third gate structure (floating gate), and effectively preventing the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate) from forming silicide and introducing a path that causes electron leakage in the third gate structure (floating gate), thereby further preventing the loss of charge stored in the third gate structure (floating gate).

[0023] In the present embodiment, while forming the first dielectric layer on the side wall of the first gate structure in the LDMOS structure, the second dielectric layer on the third gate structure in the OTP structure is formed, thereby achieving compatibility between the LDMOS structure and the OTP structure processes. Compared with forming the first dielectric layer and the second dielectric layer separately, the present embodiment saves at least one photolithography step.

[0024] Furthermore, in order to achieve compatibility between the LDMOS structure and the OTP structure processes and save the steps of photolithography, the present application introduces a parasitic polysilicon layer above the third gate structure in the OTP structure. The present embodiment retains the parasitic polysilicon layer and converts it into an electrode layer. A capacitor is formed between the electrode layer and the floating gate, and the capacitor is led out through the third gate structure control electrode. By providing different voltages to the third gate structure control electrode, the initial charge in the floating gate is erased, and the traditional OTP structure does not have the functions of limited erase and write, stronger data retention capability, and longer time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which: Figure 1a A schematic cross-sectional view of a conventional OTP structure is shown; Figure 1b The circuit schematic diagram of the traditional OTP structure is shown; Figure 2a A schematic cross-sectional view of a semiconductor device according to an embodiment of the present application is shown; Figure 2b A schematic cross-sectional view of an LDMOS structure according to an embodiment of the present application is shown; Figure 2c A schematic cross-sectional view of an OTP structure according to an embodiment of the present application is shown; Figure 2d A schematic top view of an OTP structure according to an embodiment of the present application is shown; Figures 3a to 3iThe cross-sectional views at various stages of the semiconductor device manufacturing process according to the embodiment of the present application are shown, wherein: Figure 3a A schematic diagram showing a structure in which a first gate structure to a third gate structure are formed on a semiconductor layer, and a doped region is formed in the semiconductor layer; Figure 3b A schematic diagram of the structure of forming a dielectric layer and a polysilicon layer is shown; Figure 3c A schematic structural diagram showing a process of forming a first mask layer on a polysilicon layer and patterning the first mask layer using a photolithography process; Figure 3d A schematic diagram of the structure of etching a polysilicon layer and a dielectric layer via a patterned first mask layer is shown; Figure 3e A schematic diagram of the structure for forming a contact layer is shown; Figure 3f A schematic diagram of the structure of forming an etch stop layer and an interlayer dielectric layer is shown; Figure 3g A schematic structural diagram showing a method of forming a second mask layer on an interlayer dielectric layer and patterning the second mask layer using a photolithography process; Figure 3h A schematic structural diagram of etching an interlayer dielectric layer via a patterned second mask layer is shown; Figure 3i A schematic diagram of the structure for forming an electrode structure is shown. DETAILED DESCRIPTION

[0026] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0027] This application may be presented in a variety of forms, some examples of which are described below.

[0028] Figure 1a A cross-sectional schematic diagram of a conventional OTP structure is shown. Figure 1b The schematic diagram of the traditional OTP structure is shown in FIG. Figure 1a and Figure 1bAs shown, the OTP structure includes a first semiconductor layer 110, a first doped region 120 located in the first semiconductor layer 110, and a selection gate 130a and a floating gate 130b located on the first semiconductor layer 110. The first semiconductor layer 110, the selection gate 130a, and the first doped regions 120 on both sides of the selection gate 130a constitute a selection transistor, and the first doped regions 120 on both sides of the selection gate 130a respectively constitute the source region and the drain region of the selection transistor. The first semiconductor layer 110, the floating gate 130b, and the first doped regions 120 on both sides of the floating gate 130b constitute a floating gate transistor, and the first doped regions 120 on both sides of the floating gate 130b constitute the source region and the drain region of the floating gate transistor.

[0029] The selection gate 130a of the selection transistor is connected to the word line SG via the first electrode 151, the source region of the selection transistor is connected to the source line SL via the second electrode 152, the drain region of the selection transistor is connected to the source region of the floating gate transistor, the floating gate 130b of the floating gate transistor covers the dielectric layer 140, and the drain region of the floating gate transistor is connected to the bit line BL via the third electrode 152.

[0030] In the process of manufacturing the OTP structure, charges will be introduced into the floating gate 130b. Currently, ultraviolet (UV) erasing is used to remove the charges in the floating gate 130b. The ultraviolet (UV) erasing step is performed before forming the dielectric layer 140. In the subsequent process of depositing the dielectric layer 140 and etching the dielectric layer 140 using photolithography and etching processes, charges will be introduced into the floating gate 130b to varying degrees. Therefore, it is necessary to perform ultraviolet (UV) erasing steps before forming the first electrode 151 to the third electrode 152. However, the dielectric layer 140 is usually a nitride layer (for example, SiN), and ultraviolet light cannot penetrate the dielectric layer 140 to reach the floating gate 130b, and thus cannot effectively remove the charges in the floating gate 130b.

[0031] Furthermore, the traditional OTP structure cannot be changed a second time after being programmed once, and the initial coding has poor fault tolerance. After a batch of products are burned and coded once, if there is an error, there is no chance to correct it, which will lead to unnecessary product scrapping due to minor software problems such as programming errors.

[0032] Furthermore, traditional OTP structures have a certain service life. After being encoded, data storage will be lost due to the limitation of its data retention capability after a certain period of time, resulting in the inability to normally obtain data information related to the OTP structure after a certain period of time.

[0033] Figure 2a A schematic cross-sectional view of a semiconductor device according to an embodiment of the present application is shown; Figure 2b A schematic cross-sectional view of an LDMOS structure according to an embodiment of the present application is shown; Figure 2cA schematic cross-sectional view of an OTP structure according to an embodiment of the present application is shown; Figure 2d FIG. 2 shows a schematic top view of the OTP structure of an embodiment of the present application. Figure 2a to Figure 2d As shown, the semiconductor device includes an LDMOS structure and an OTP structure.

[0034] Specifically, the semiconductor device includes a second semiconductor layer 210, a second doped region 220 in the second semiconductor layer 210, and a first gate structure 231, a second gate structure 232, and a third gate structure 233 on the second semiconductor layer 210. The second semiconductor layer 210 may be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer.

[0035] The second semiconductor layer 210 , the first gate structure 231 and the second doping regions 220 on both sides of the first gate structure 231 constitute an LDMOS structure. The second doping regions 220 on both sides of the first gate structure 231 respectively constitute a source region and a drain region of the LDMOS structure.

[0036] The second semiconductor layer 210, the second gate structure 232, and the second doped regions 220 on both sides of the second gate structure 232 constitute a selection transistor of an OTP structure, and the second doped regions 220 on both sides of the second gate structure 232 constitute the source region and the drain region of the selection transistor. The second semiconductor layer 210, the third gate structure 233, and the second doped regions 220 on both sides of the third gate structure 233 constitute a floating gate transistor of an OTP structure, and the second doped regions 220 on both sides of the third gate structure 233 constitute the source region and the drain region of the floating gate transistor. Further, the drain region of the selection transistor is connected to the source region of the floating gate transistor.

[0037] The first gate structure 231 includes a gate dielectric layer 230a, a gate conductor 230b located on the gate dielectric layer 230a, and sidewalls 230c located on both sides of the gate conductor 230b, and the sidewalls 230c include an oxide layer and / or a nitride layer. The structures of the second gate structure 232 and the third gate structure 233 are the same as those of the first gate structure 231, and are not described in detail in this embodiment.

[0038] The semiconductor device includes a first dielectric layer 241 and a second dielectric layer 242. The first dielectric layer 241 is at least located on one side wall of the first gate structure 231. In this embodiment, the first dielectric layer 241 covers one side wall of the first gate structure 231 and extends to the top of the first gate structure 231. The first dielectric layer 241 exposes at least a portion of the surface of the top of the first gate structure 231. The second dielectric layer 242 is at least located on the third gate structure 233. In this embodiment, the second dielectric layer 242 is located on the third gate structure 233, on the second semiconductor layer 210 between the third gate structure 233 and the second gate structure 232, and extends to the second gate structure 232. Specifically, the second dielectric layer 242 covers the top and side wall of the third gate structure 233, the surface of the second semiconductor layer 210 between the second gate structure 232 and the third gate structure 233, the side wall of the second gate structure 232 close to the third gate structure 233, and a portion of the surface of the top of the second gate structure 232.

[0039] The first dielectric layer 241 and the second dielectric layer 242 include one or more dielectric layers. In this embodiment, the first dielectric layer 241 and the second dielectric layer 242 include a stacked bottom dielectric layer 240a and a top dielectric layer 240b, wherein the bottom dielectric layer 240a is, for example, a nitride layer (for example, a SiON layer), and the top dielectric layer 240b is, for example, an oxide layer (for example, a SiO 2 layer).

[0040] The semiconductor device includes a contact layer, specifically including a sidewall contact layer 250a, an electrode layer 250b, a gate contact layer 250c and a doped region contact layer 250d. The sidewall contact layer 250a is located on the first dielectric layer 241, the electrode layer 250b is located on the second dielectric layer 242, the gate contact layer 250c is located on the top of the first gate structure 231 and the top of the second gate structure 232, and the doped region contact layer 250d is located on the top of the second doped region 220.

[0041] The semiconductor device includes an etch stop layer 260, an interlayer dielectric layer 270, and an electrode structure. The etch stop layer 260 conformally covers the exposed surface of the second semiconductor layer 210, the surface of the sidewall contact layer 250a on the first dielectric layer 241, the surface of the electrode layer 250b on the second dielectric layer 242, and the exposed surfaces of the first gate structure 231 and the second gate structure 232. The interlayer dielectric layer 270 is located on the etch stop layer 260 and covers the surface of the etch stop layer 260.

[0042] The electrode structure includes a first gate electrode 281, a first source electrode 282, and a first drain electrode 283. The first gate electrode 281 reaches the top of the first gate structure 231 and contacts the gate contact layer 250c at the top of the first gate structure 231. The first source electrode 282 and the first drain electrode 283 respectively reach the second doping regions 220 on both sides of the first gate structure 231 and contact the doping region contact layer 250d at the top of the second doping region 220. In this embodiment, the electrode structure also includes a sidewall electrode 284 that reaches the sidewall of the first gate structure 231, and the sidewall electrode 284 contacts the sidewall contact layer 250a on the sidewall.

[0043] The electrode structure includes a selection gate electrode 285, a second source electrode 286, and a second drain electrode 287. The selection gate electrode 285 reaches the top of the second gate structure (selection gate) 232, and contacts the gate contact layer 250c of the second gate structure (selection gate) 232. The second source electrode 286 reaches the second doping region 220 on the side of the second gate structure (selection gate) 232 away from the third gate structure (floating gate) 233, and contacts the doping region contact layer 250d on the top of the second doping region 220. The second drain electrode 287 reaches the surface of the second doping region 220 on the side of the third gate structure (floating gate) 233 away from the second gate structure (selection gate) 232, and contacts the doping region contact layer 250d on the top of the second doping region 220.

[0044] Furthermore, the electrode structure further includes a third gate structure control electrode 288, and the third gate structure control electrode 288 is in contact with the electrode layer 250b. Since the electrode layer 250b is located above the top and sidewall of the third gate structure (floating gate) 233 and extends above the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, the third gate structure control electrode 288 can be arranged at any one of the top of the third gate structure (floating gate) 233, the sidewall of the third gate structure (floating gate) 233, and between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233.

[0045] In this embodiment, the third gate structure control electrode 288 is arranged between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233. When the third gate structure control electrode 288 is located on the top and sidewall of the third gate structure (floating gate) 233, over-etching is likely to occur during the process of forming the contact hole of the third gate structure control electrode 288, so that the contact hole of the third gate structure control electrode 288 extends into the second dielectric layer 242, or even passes through the second dielectric layer 242 and extends to the top or sidewall of the third gate structure (floating gate) 233, further making the third gate structure control electrode 288 contact the third gate structure (floating gate) 233, introducing unnecessary leakage risk. In this embodiment, the third gate structure control electrode 288 is arranged between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233 to avoid short circuit between the third gate structure control electrode 288 and the third gate structure (floating gate) 233, thereby increasing the reliability of the device and not affecting the layout of other electrodes.

[0046] Among them, the electrode layer 250b on the second dielectric layer 242 and the third gate structure (floating gate) 233 form upper and lower electrode plates, the electrode layer 250b on the second dielectric layer 242, the second dielectric layer 242 and the third gate structure (floating gate) 233 form a capacitor structure, and the upper plate (electrode layer 250b) of the capacitor structure is led out through the third gate structure control electrode 288.

[0047] Before the OTP structure is encoded, the third gate structure controls the electrode 288 to apply a first voltage, and the first voltage is, for example, a positive voltage. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer 250b, the second dielectric layer 242 and the third gate structure (floating gate) 233, and the electrons in the third gate structure (floating gate) 233 move upward. The electrons break through the potential barrier of the third gate structure (floating gate) 233 / the second dielectric layer 242 (especially the SiON layer) and are lost in large quantities, thereby achieving the effect of clearing the charge in the third gate structure (floating gate) 233.

[0048] After the OTP structure encoding is completed, due to the high-k property of the second dielectric layer 242 (especially the dielectric layer SiON), it is difficult for the electrons in the third gate structure (floating gate) 233 to break through the second dielectric layer 242, especially the potential barrier of the bottom dielectric layer 240a (SiON). Further, after the OTP structure encoding is completed, a second voltage can be applied to the third gate structure control electrode 288, and the second voltage is, for example, a negative voltage, so that an upward electric field is formed in the capacitor structure formed by the electrode layer 250b, the dielectric stack 240 and the third gate structure (floating gate) 233, thereby suppressing the loss of electrons in the third gate structure (floating gate) 233 and further improving the reliability of the data retention capability of the OTP structure.

[0049] The traditional OTP structure has a very low fault tolerance due to its one-time programming characteristics. Usually, if the coding is wrong once, the secondary coding cannot be achieved. In this embodiment, since the electrode layer 250b is arranged above the third gate structure (floating gate) 233, and the third gate structure control electrode 288 connected to the electrode layer 250b above the third gate structure (floating gate) 233 is arranged, the OTP structure can achieve a limited number of erasures and writes, further greatly improving the fault tolerance of the OTP structure. Specifically, when the OTP structure is coded incorrectly, the third gate structure controls the electrode 288 to apply a third voltage, and the third voltage is, for example, a positive voltage. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer 250b, the second dielectric layer 242 and the third gate structure (floating gate) 233. The electrons introduced by programming in the third gate structure (floating gate) 233 move upward, and the electrons break through the potential barrier of the third gate structure (floating gate) 233 / second dielectric layer 242 (especially the dielectric layer SiON) and flow out, thereby achieving the effect of electronic erasure, and further enabling the OTP structure to achieve a limited number of repeated programming.

[0050] Furthermore, the electrode layer 250b covers the top and side walls of the third gate structure (floating gate) 233, that is, the electrode layer 250b completely covers the third gate structure (floating gate) 233, so that the third gate structure control electrode 288 can apply a small voltage to erase the charge in the third gate structure (floating gate) 233 and maintain the stored charge.

[0051] Furthermore, the electrode layer 250b on the top of the third gate structure (floating gate) 233 extends to above the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, and above the second gate structure (select gate) 232. The third gate structure control electrode 288 is arranged between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233. On the one hand, the arrangement of the third gate structure control electrode 288 will not affect the lead-out of other electrodes (such as the select gate electrode 285, the second source electrode 286 and the second drain electrode 287), and the overall area and overall structure of the electrode structure of the OTP structure will not be affected. On the other hand, the third gate structure control electrode 288 is arranged between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, so that the bottom of the third gate structure control electrode 288 is connected to the planar electrode layer 250b, which is more conducive to the etching of the third gate structure control electrode 288.

[0052] Furthermore, the second dielectric layer is located on the third gate structure (floating gate) 233 and extends to the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, thereby preventing the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233 from forming silicide, thereby affecting the conduction of the channel between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, and effectively preventing the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233 from forming silicide, thereby introducing a path that causes electron leakage in the third gate structure (floating gate) 233, thereby further preventing the loss of the charge stored in the third gate structure (floating gate) 233.

[0053] Figures 3a to 3i The cross-sectional views at various stages in the process of preparing the semiconductor device according to the embodiment of the present application are shown.

[0054] like Figure 3a As shown, a first gate structure 231 , a second gate structure 232 and a third gate structure 233 are formed on the second semiconductor layer 210 , and a second doping region 220 is formed in the second semiconductor layer 210 .

[0055] The second semiconductor layer 210 may be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. The second semiconductor layer 210, the first gate structure 231, and the second doped regions 220 on both sides of the first gate structure 231 constitute an LDMOS structure, and the second doped regions 220 on both sides of the first gate structure 231 respectively constitute a source region and a drain region of the LDMOS structure.

[0056] The second semiconductor layer 210, the second gate structure 232, and the second doped regions 220 on both sides of the second gate structure 232 constitute a selection transistor of an OTP structure, and the second doped regions 220 on both sides of the second gate structure 232 constitute the source region and the drain region of the selection transistor. The second semiconductor layer 210, the third gate structure 233, and the second doped regions 220 on both sides of the third gate structure 233 constitute a floating gate transistor of an OTP structure, and the second doped regions 220 on both sides of the third gate structure 233 constitute the source region and the drain region of the floating gate transistor.

[0057] The first gate structure 231 includes a gate dielectric layer 230a, a gate conductor 230b located on the gate dielectric layer 230a, and sidewalls 230c located on both sides of the gate conductor 230b, and the sidewalls 230c include an oxide layer and / or a nitride layer. The structures of the second gate structure 232 and the third gate structure 233 are the same as those of the first gate structure 231, and are not described in detail in this embodiment.

[0058] like Figure 3bAs shown, a dielectric stack 240 and a polysilicon layer 2501 are sequentially formed on the second semiconductor layer 210, the first gate structure 231, the second gate structure 232, and the third gate structure 233. The dielectric stack 240 conformally covers the surfaces of the second semiconductor layer 210, the first gate structure 231, the second gate structure 232, and the third gate structure 233, and the polysilicon layer 2501 conformally covers the surface of the dielectric stack 240. In this embodiment, the dielectric stack 240 includes a stacked bottom dielectric layer 240a and a top dielectric layer 240b. The bottom dielectric layer 240a is, for example, a nitride layer (for example, a SiON layer), and the top dielectric layer 240b is, for example, an oxide layer (for example, a SiO 2 layer).

[0059] like Figure 3c As shown, a first mask layer PR1 is formed on the polysilicon layer 2501, and the first mask layer PR1 is patterned by a photolithography process.

[0060] like Figure 3d As shown, the polysilicon layer 2501 and the dielectric stack 240 are etched through the patterned first mask layer PR1 to form a first dielectric layer 241 , a polysilicon layer 2501 on the first dielectric layer 241 , a second dielectric layer 242 , and a polysilicon layer 2501 on the second dielectric layer 242 .

[0061] The first dielectric layer 241 at least covers the sidewall of the first gate structure 231. In this embodiment, the first dielectric layer 241 covers at least a portion of the surface of the top of the first gate structure 231 and the sidewall of the first gate structure 231. At least a portion of the surface of the top of the first gate structure 231 and the sidewall of the other side of the first gate structure 231 are exposed. The second dielectric layer 242 at least covers the third gate structure 233. In this embodiment, the second dielectric layer 242 covers the third gate structure 233 (including the top and sidewall of the third gate structure 233) and the surface of the second semiconductor layer 210 between the second gate structure 232 and the third gate structure 233, and extends to at least a portion of the surface of the second gate structure 232, for example, extends to the sidewall of the second gate structure 232 close to the third gate structure 233 and at least a portion of the surface of the top of the second gate structure 232. At least a portion of the surface of the top of the second gate structure 232 and the sidewall of the second gate structure 232 away from the third gate structure 233 are exposed.

[0062] in, Figure 3c and Figure 3dIn the steps shown, the dielectric stack 240 and the polysilicon layer 2501 are etched using the same mask, and the first dielectric layer 241 is formed at least on the sidewall of the first gate structure 231 of the LDMOS structure, and the second dielectric layer 242 is formed at least on the third gate structure of the OTP structure, that is, the first dielectric layer 241 and the second dielectric layer 242 are formed simultaneously. Compared with separately forming the first dielectric layer 241 in the LDMOS structure and the second dielectric layer 242 in the OTP structure, this embodiment omits a mask. However, it should be found that compared with Figure 1a In the embodiment shown, in order to be compatible with the polysilicon layer 2501 on the first dielectric layer 241 in the LDMOS structure, a polysilicon layer 2501 is also parasitically grown on the second dielectric layer 242 in the OTP structure.

[0063] like Figure 3e As shown, a contact layer is formed.

[0064] A metal layer is formed on the surface of the exposed second doping region 220, the surface exposed on the top of the first gate structure 231, the surface exposed on the top of the second gate structure 232, and the surface of the polysilicon layer 2501 above the first dielectric layer 241 and the second dielectric layer 242. The metal layer is, for example, a nickel (Ni) layer, a platinum (Pt) layer, a cobalt (Co) layer, a nickel-platinum alloy layer, a nickel-cobalt alloy layer, a platinum-cobalt alloy layer, a nickel-platinum-cobalt ternary alloy layer, etc. Then, for example, by an annealing process, the metal layer reacts with the exposed silicon surface to form a sidewall contact layer 250a on the first dielectric layer 241, an electrode layer 250b on the second dielectric layer 242, a gate contact layer 250c on the surface exposed on the top of the first gate structure 231 and the surface exposed on the top of the second gate structure 232, and a doping region contact layer 250d on the surface of the second doping region 220.

[0065] In this step, the polysilicon layer 2501 on the first dielectric layer 241 forms a sidewall contact layer 250a to facilitate the lead-out of the sidewall electrode formed subsequently; at the same time, the parasitic polysilicon layer 2501 on the second dielectric layer 242 forms an electrode layer 250b, and the electrode layer 250b and the third gate structure (floating gate) 233 form upper and lower electrode plates, and the electrode layer 250b on the second dielectric layer 242, the second dielectric layer 242 and the third gate structure (floating gate) 233 form a capacitor structure.

[0066] like Figure 3f As shown, an etch stop layer 260 and an interlayer dielectric layer 270 are formed.

[0067] For example, the etch stop layer 260 and the interlayer dielectric layer 270 are formed by a deposition process. The etch stop layer 260 conformally covers the surface of the sidewall contact layer 250a, the surface of the electrode layer 250b, the surface of the gate contact layer 250c, the surface of the doped region contact layer 250d, and the exposed surface of the first gate structure 231 and the second gate structure 232. The interlayer dielectric layer 270 covers the surface of the etch stop layer 260. Then, for example, the interlayer dielectric layer 270 is planarized by a CMP process so that the interlayer dielectric layer 270 has a flat surface. The etch stop layer 260 is, for example, a silicon nitride layer (SiN) and / or a silicon oxide layer (SiO 2 The interlayer dielectric layer 270 is, for example, a silicon oxide layer (SiO 2 layer).

[0068] like Figure 3g As shown, a second mask layer PR2 is formed on the interlayer dielectric layer 270, and the second mask layer PR2 is patterned by a photolithography process.

[0069] like Figure 3h As shown, the interlayer dielectric layer 270 and the etch stop layer 260 are etched through the patterned second mask layer PR2 to form a through hole penetrating the interlayer dielectric layer 270 and the etch stop layer 260 .

[0070] like Figure 3i As shown, an electrode structure is formed.

[0071] In this step, a conductive layer is formed by, for example, a deposition process, and the conductive layer covers the surface of the interlayer dielectric layer 270 and fills the through hole in the interlayer dielectric layer 270. Then, the conductive layer is planarized by, for example, a CMP process so that the conductive layer has a flat surface. Then, the conductive layer is etched by photolithography and etching processes to form an electrode structure.

[0072] The electrode structure includes a first gate electrode 281, a first source electrode 282, and a first drain electrode 283. The first gate electrode 281 reaches the top of the first gate structure 231 and contacts the gate contact layer 250c at the top of the first gate structure 231. The first source electrode 282 and the first drain electrode 283 respectively reach the surface of the second doping region 220 and contact the doping region contact layer 250d at the top of the second doping region 220. In this embodiment, the electrode structure also includes a sidewall electrode 284 that reaches the sidewall of the first gate structure 231, and the sidewall electrode 284 contacts the sidewall contact layer 250a on the sidewall.

[0073] The electrode structure includes a selection gate electrode 285, a second source electrode 286, and a second drain electrode 287. The selection gate electrode 285 reaches the top of the second gate structure (selection gate) 232 and contacts the gate contact layer 250c of the second gate structure (selection gate) 232. The second source electrode 286 and the second drain electrode 287 respectively reach the surface of the second doping region 220 and contact the doping region contact layer 250d at the top of the second doping region 220.

[0074] Furthermore, the electrode structure further includes a third gate structure control electrode 288, and the third gate structure control electrode 288 contacts the electrode layer 250b at any one of the electrode layer 250b at the top of the third gate structure (floating gate) 233, the electrode layer 250b at the sidewall of the third gate structure (floating gate) 233, and the electrode layer 250b between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233. In this embodiment, the third gate structure control electrode 288 contacts the electrode layer 250b between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233.

[0075] The unexpected technical effects of this application are: According to the semiconductor device and the preparation method thereof of the embodiments of the present invention, the electrode layer on the second dielectric layer and the third gate structure (floating gate) form upper and lower electrode plates, the electrode layer on the second dielectric layer, the second dielectric layer and the third gate structure (floating gate) form a capacitor structure, and the upper plate (electrode layer) of the capacitor structure is led out via the third gate structure control electrode.

[0076] Before the OTP structure is encoded, a positive voltage is applied to the control electrode of the third gate structure. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer, the second dielectric layer and the third gate structure (floating gate). The electrons in the third gate structure (floating gate) move upward, and the electrons break through the potential barrier of the third gate structure (floating gate) / second dielectric layer (especially SiON) and are lost in large quantities, thereby achieving the effect of clearing the charge in the third gate structure (floating gate).

[0077] After the OTP structure is encoded, due to the high-k nature of the second dielectric layer (especially the dielectric layer SiON), it is difficult for the electrons in the third gate structure (floating gate) to break through the second dielectric layer, especially the potential barrier of the dielectric layer (SiON). Further, after the OTP structure is encoded, a negative voltage can be applied to the control electrode of the third gate structure, and an upward electric field is formed in the capacitor structure formed by the electrode layer on the second dielectric layer, the second dielectric layer and the third gate structure (floating gate), thereby suppressing the loss of electrons in the third gate structure (floating gate) and further improving the reliability of the data retention capability of the OTP structure.

[0078] In this embodiment, since an electrode layer is provided above the third gate structure (floating gate), and a third gate structure control electrode connected to the electrode layer above the third gate structure (floating gate) is provided, the OTP structure can achieve a limited number of erasures and writes, further greatly improving the fault tolerance of the OTP structure. Specifically, when the OTP structure is coded incorrectly, a positive voltage is applied to the third gate structure control electrode. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer, the second dielectric layer, and the third gate structure (floating gate). The electrons introduced by programming in the third gate structure (floating gate) move upward, and the electrons break through the third gate structure (floating gate) / second dielectric layer (especially dielectric layer SiON) potential barrier and flow out, achieving the effect of electronic erasure, further enabling the OTP structure to achieve a limited number of repeated programming.

[0079] Furthermore, the electrode layer covers the top and side walls of the third gate structure (floating gate), that is, the electrode layer completely covers the third gate structure (floating gate), so that the third gate structure can control the electrode to apply a small voltage to erase the charge in the third gate structure (floating gate) and maintain the stored charge.

[0080] Furthermore, the electrode layer on the top of the third gate structure (floating gate) extends to above the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), and above the second gate structure (select gate). The third gate structure control electrode can be arranged between the second gate structure (select gate) and the third gate structure (floating gate). On the one hand, the arrangement of the third gate structure control electrode will not affect the lead-out of other electrodes (such as the select gate electrode, the second source electrode and the second drain electrode), and the overall area and the overall structure of the electrode structure of the OTP structure will not be affected. On the other hand, the third gate structure control electrode is arranged between the second gate structure (select gate) and the third gate structure (floating gate), so that the bottom of the third gate structure control electrode is connected to the planar electrode layer, which is more conducive to the etching of the third gate structure control electrode.

[0081] Furthermore, the second dielectric layer is located on the third gate structure (floating gate) and extends to the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), thereby preventing the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate) from forming silicide, thereby affecting the conduction of the channel between the second gate structure (select gate) and the third gate structure (floating gate), and effectively preventing the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate) from forming silicide and introducing a path that causes electron leakage in the third gate structure (floating gate), thereby further preventing the loss of charge stored in the third gate structure (floating gate).

[0082] In the present embodiment, while forming the first dielectric layer on the side wall of the first gate structure in the LDMOS structure, the second dielectric layer on the third gate structure in the OTP structure is formed, thereby achieving compatibility between the LDMOS structure and the OTP structure processes. Compared with forming the first dielectric layer and the second dielectric layer separately, the present embodiment saves at least one photolithography step.

[0083] Furthermore, in order to achieve compatibility between the LDMOS structure and the OTP structure processes and save the steps of photolithography, the present application introduces a parasitic polysilicon layer above the third gate structure in the OTP structure. The present embodiment retains the parasitic polysilicon layer and converts it into an electrode layer. A capacitor is formed between the electrode layer and the floating gate, and the capacitor is led out through the third gate structure control electrode. By providing different voltages to the third gate structure control electrode, the initial charge in the floating gate is erased, and the traditional OTP structure does not have the functions of limited erase and write, stronger data retention capability, and longer time.

[0084] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor layer; A first gate structure, a second gate structure and a third gate structure are located on the semiconductor layer; a doped region located in the semiconductor layer; a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is at least located on a side wall of the first gate structure, and the second dielectric layer is at least located on the third gate structure; as well as A sidewall contact layer and an electrode layer, wherein the sidewall contact layer is located on the first dielectric layer, and the electrode layer is located on the second dielectric layer; The electrode layer, the second dielectric layer and the third gate structure constitute a capacitor structure, and the electrode layer is led out through the third gate structure to control the electrode; the first dielectric layer and the second dielectric layer are formed simultaneously, and the sidewall contact layer and the electrode layer are formed simultaneously.

2. The semiconductor device according to claim 1, wherein: The semiconductor layer, the second gate structure and the doped regions on both sides of the second gate structure constitute a selection transistor of an OTP structure; the semiconductor layer, the third gate structure and the doped regions on both sides of the third gate structure constitute a floating gate transistor of an OTP structure, and the source region of the floating gate transistor is connected to the drain region of the selection transistor; Before programming the OTP structure, the third gate structure controls the electrode to apply a positive voltage to clear the initial charge in the floating gate.

3. The semiconductor device according to claim 1, wherein: The semiconductor layer, the second gate structure and the doped regions on both sides of the second gate structure constitute a selection transistor of an OTP structure; the semiconductor layer, the third gate structure and the doped regions on both sides of the third gate structure constitute a floating gate transistor of an OTP structure, and the source region of the floating gate transistor is connected to the drain region of the selection transistor; After the OTP structure is programmed, the third gate structure controls the electrode to apply a negative voltage to retain electrons in the floating gate.

4. The semiconductor device according to claim 1, wherein: The semiconductor layer, the second gate structure and the doped regions on both sides of the second gate structure constitute a selection transistor of an OTP structure; the semiconductor layer, the third gate structure and the doped regions on both sides of the third gate structure constitute a floating gate transistor of an OTP structure, and the source region of the floating gate transistor is connected to the drain region of the selection transistor; The third gate structure controls the electrode to apply a positive voltage to clear electrons in the floating gate.

5. The semiconductor device according to claim 1, wherein: The second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; The third gate structure control electrode contacts the electrode layer between the third gate structure and the second gate structure.

6. The semiconductor device according to claim 1, wherein: The first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

7. A method for preparing a semiconductor device, characterized in that: include: forming a first gate structure, a second gate structure and a third gate structure on the semiconductor layer; forming a doped region in the semiconductor layer; forming a first dielectric layer at least on the sidewall of the first gate structure, and forming a second dielectric layer at least on the third gate structure, wherein the first dielectric layer and the second dielectric layer are formed simultaneously; forming a sidewall contact layer on the first dielectric layer, and forming an electrode layer on the second dielectric layer, wherein the sidewall contact layer and the electrode layer are formed simultaneously; The electrode layer, the second dielectric layer and the third gate structure form a capacitor structure, and the electrode layer is led out through the third gate structure to control the electrode.

8. The method according to claim 7, characterized in that The steps of forming the first dielectric layer, the second dielectric layer, the sidewall contact layer and the electrode layer include: forming a dielectric layer on the semiconductor layer and the first gate structure, the second gate structure, and the third gate structure, wherein the dielectric layer conformally covers the semiconductor layer and the first gate structure, the second gate structure, and the third gate structure; forming a polysilicon layer on the dielectric layer; forming a patterned mask layer on the polysilicon layer; Etching the polysilicon layer and the dielectric layer through the patterned mask layer to form a first dielectric layer, a polysilicon layer located on the first dielectric layer, a second dielectric layer, and a polysilicon layer located on the second dielectric layer, wherein the first dielectric layer at least covers the sidewalls of the first gate structure, and the second dielectric layer at least covers the third gate structure; The polysilicon layer on the first dielectric layer and the polysilicon layer on the second dielectric layer are alloyed to form a sidewall contact layer on the first dielectric layer and an electrode layer on the second dielectric layer.

9. The method according to claim 7, characterized in that: The second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; The third gate structure control electrode contacts the electrode layer between the third gate structure and the second gate structure.

10. The method according to claim 7, characterized in that The first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

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