Memory element

Abstract

The invention relates to a memory element, which comprises a stacking structure, a stop layer, a dielectric layer, at least one partition wall and a conductor plug, the stack structure is over the substrate. The stacking structure is provided with an opening, and the step structure of the stacking structure is exposed. The first stop layer at least covers the stepped structure and at least a portion of a plurality of sidewalls of the opening. The dielectric layer is filled in the opening and covers the first stop layer. At least one partition wall extends through the dielectric layer in the opening and the first stop layer. The conductor plug extends through the dielectric layer and the first stop layer and is electrically connected with the stepped structure. The memory element may be a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a memory device. Background Art

[0002] Non-volatile memory elements (eg, flash memory) have become a widely used memory element in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.

[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory.

[0004] For example, multiple word lines of a three-dimensional NAND flash memory are electrically connected through conductor plugs. However, since the conductor plugs have various depths, it is difficult to control the process, so that some conductor plugs cannot land on the word lines, or some conductor plugs pass through the word lines, resulting in short circuits with multiple word lines, thereby causing poor process yield problems. Summary of the invention

[0005] The present invention provides a memory element which can enable conductor plugs of various depths to land on a word line of a ladder structure and can improve the yield of the process.

[0006] A memory element according to an embodiment of the present invention comprises a stacking structure, a first stop layer, a dielectric layer, at least one partition wall and a conductor plug. The stacking structure is located above the substrate, wherein the stacking structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening, exposing a step structure of the stacking structure. The first stop layer covers the step structure and at least a portion of a plurality of side walls of the opening. The dielectric layer is filled in the opening, covering the first stop layer. At least one partition wall extends through the dielectric layer and the first stop layer in the opening. The conductor plug extends through the dielectric layer and the first stop layer, and is electrically connected to the step structure.

[0007] A memory element according to an embodiment of the present invention comprises a substrate, a stacking structure, a first stop layer, a dielectric layer, at least one partition wall and a conductor plug. The stacking structure is located above the substrate, wherein the stacking structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening, exposing a step structure of the stacking structure, wherein the opening comprises a first side wall, a second side wall, a third side wall, a fourth side wall and a bottom. The second side wall is connected to the first side wall. The third side wall is connected to the second side wall, wherein the first side wall is opposite to the third side wall. The fourth side wall is connected to the third side wall, wherein the second side wall is opposite to the fourth side wall. The bottom is connected to the first side wall, the second side wall, the third side wall and the fourth side wall. The first stop layer comprises a first part and a second part. The first part covers the step structure. The second part covers at least the first side wall and the third side wall. The dielectric layer is filled in the opening and covers the first stop layer. At least one partition wall extends through the dielectric layer in the opening and the first part and the second part of the first stop layer. The conductor plug extends through the dielectric layer and the first portion of the first stop layer and is electrically connected to the stepped structure.

[0008] Based on the above, the memory element of the embodiment of the present invention can allow conductor plugs of various depths to land on the word line of the stepped structure, and can improve the process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1D is a top view of an intermediate stage of a method for manufacturing a memory device according to an embodiment of the present invention.

[0010] Figures 2A to 2R It is a cross-sectional schematic diagram of a method for manufacturing a memory element according to an embodiment of the present invention.

[0011] Figure 3A and Figure 3B The conductor plugs are shown at different depths.

[0012] Figure 4A and Figure 4B A partial cross-sectional schematic diagram of a plurality of stop layers and liner layers according to an embodiment of the present invention is shown.

[0013] Figure 4C and Figure 4D A partial cross-sectional schematic diagram showing a conductor plug extending through a plurality of stop layers and liner layers according to an embodiment of the present invention.

[0014] FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6B as well as FIG. 7A to FIG. 7C Schematic cross-sectional views showing intermediate stages of various memory elements according to embodiments of the present invention.

[0015] FIG. 8A to FIG. 8D is a top view of an intermediate stage of a method for manufacturing a memory device according to another embodiment of the present invention.

[0016] FIG. 9A to FIG. 9E is a cross-sectional schematic diagram of a method for manufacturing a memory element according to another embodiment of the present invention.

[0017] Fig. 10A and Fig. 10B The conductor plugs are shown at different depths.

[0018] Fig.11A and Fig. 11B A partial cross-sectional schematic diagram of a plurality of stop layers and liner layers according to an embodiment of the present invention is shown.

[0019] Fig. 11C and Fig.11D A partial cross-sectional schematic diagram showing a conductor plug extending through a plurality of stop layers and liner layers according to an embodiment of the present invention.

[0020] FIG. 12A to FIG. 12D It is a cross-sectional schematic diagram of a manufacturing process of stacked wafers according to an embodiment of the present invention.

[0021] Fig.13 A cross-sectional schematic diagram of a packaging structure is shown.

[0022] Description of reference numerals:

[0023] 10, 100, 300: base

[0024] 10W, 100W, 300W: Chip

[0025] 14, 44, 150, 150a, 150b: Lining

[0026] 16, 316: Semiconductor perforation

[0027] 20, 320: Component layer

[0028] 30, 40, 130, 330: Internal connection structure

[0029] 32, 132: Joint structure

[0030] 43: Conductor plug opening

[0031] 46. ​​COA, COA': conductor plug

[0032] 48: Wire

[0033] 50, 51, 107, 115, 128, 131: Dielectric layer

[0034] 52, 52', 352, 352': Connectors

[0035] 92, 101, 102: Insulation layer

[0036] 93, 94, 126: Conductor layer

[0037] 103: Stop Structure

[0038] 129, 152, 154, 154b', 154': Stop layer

[0039] 103a: Insulation structure

[0040] 104: Middle layer

[0041] 105, 105A, 106: Open

[0042] 108: Charge storage structure

[0043] 110: Channel layer

[0044] 112: Insulation column

[0045] 114: Channel plug

[0046] 116: Separation channel

[0047] 118: Filling layer

[0048] 121a, 123: Horizontal opening

[0049] 121b: U-shaped tunnel

[0050] 150a, 150b: Lining / part

[0051] 152a, 152b: Stop layer / part

[0052] 154I: Interface

[0053] 154: Stop layer

[0054] 156: Conductor material

[0055] 1561: Barrier layer

[0056] 1562: Conductor filling layer

[0057] 1563: Lining material

[0058] 200W, 400W, 500W: stacked chips

[0059] 402, 404: Fill with bottom filler

[0060] 406: Encapsulation layer

[0061] 500: Application-Specific Integrated Circuits

[0062] 600: Intermediary layer

[0063] 700: Packaging structure

[0064] 154 1 , 154 2 , 154 3 : Material layer

[0065] ARR: Memory Array Region

[0066] ARY: memory array

[0067] BL: Bit Line

[0068] CSL: Common Source Line

[0069] D1: Direction

[0070] D2: Direction

[0071] d3, d4, d5, d6: distance

[0072] DVC: Dummy Column

[0073] F1, F2: Subsections

[0074] HM: Hard Mask Layer

[0075] L1, L1': length

[0076] LP: Lower

[0077] MC: Memory Cell

[0078] OP1: Conductor plug hole

[0079] OP2: Perforated opening

[0080] P1: Distance

[0081] PIC: Support structure

[0082] PRR: Peripheral Region

[0083] RSC: Anti-step structure

[0084] SC: Ladder structure

[0085] SC1, SC2: Partial

[0086] SCR: Step Area

[0087] SK1, SK2: stacked structure

[0088] SLT, SLT 1 , SLT 2: Partition wall

[0089] SM1, SM1', SM2: memory chips

[0090] T1, T2, T3, T4: thickness

[0091] TV: Perforation

[0092] UP: upper part

[0093] VC: Channel Column

[0094] W1: Width

[0095] W2: Width

[0096] W3: Minimum width / bottom width

[0097] WL: Word Line

[0098] d3, d4: distance

[0099] sw1, sw2, sw3, sw4: side wall

[0100] I-I': line

[0101] II-II': Line

[0102] IV-IV': Line

[0103] VI-VI': Line

[0104] VII-VII': Line

[0105] VIII-VIII': Line

[0106] S1~S10: Stairs DETAILED DESCRIPTION

[0107] Figure 1D and Fig.8D is a top view of several memory devices at intermediate stages according to embodiments of the present invention. Figure 2R and Fig.9E Schematic cross-sectional views of various memory elements according to embodiments of the present invention are shown. Figure 3A and Figure 3B as well as Fig. 10A and Fig. 10B The conductor plugs are shown at different depths.

[0108] Refer to Figure 2R and Fig.9EThe memory chips SM1 and SM2 of the embodiments of the present invention each include a memory array region ARR, a step region SCR, and a peripheral region PRR. The memory array region ARR includes a stacked structure SK2. The stacked structure SK2 includes a plurality of insulating layers 102 and a plurality of conductor layers 126 that are alternately stacked. The plurality of conductor layers 126 can serve as a plurality of word lines WL. A plurality of channel pillars VC extend through the stacked structure SK2. A plurality of charge storage structures 108 surround the vertical outer surface of the channel pillars VC. And between the plurality of conductor layers 126 and the plurality of channel pillars VC. A plurality of word lines WL, a plurality of channel pillars VC, and a plurality of charge storage structures 108 sandwiched therebetween form a plurality of memory cells MC. A plurality of memory cells MC form a memory array ARY. In other words, the stacked structure SK2 has a memory array ARY.

[0109] Reference Figure 2R and Fig.9E The stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked alternately. The stepped region SCR includes a plurality of stepped structures SC exposed by the openings 105 or 105A, such as Figure 2Q and Fig.9D As shown. Figure 2R and Fig.9E In the structure, the ladder structure SC is reversed, so it can also be called the anti-ladder structure RSC.

[0110] Reference Figure 2R as well as Fig.9E , the memory chips SM1 and SM2 also include a plurality of conductor plugs COA', COA and a through-hole TV. The conductor plug COA' is located in the memory array region ARR, and electrically connects the plurality of channel pillars VC to the bit lines BL. The conductor plug COA is located in the ladder region SCR, and extends through the dielectric layer 107 in the opening 105, and electrically connects one of the plurality of conductor layers 126 (that is, a plurality of word lines WL) of the step structure SC to the underlying internal connection structure 130. The through-hole TV is located in the peripheral region PRR, and is electrically connected to the conductor plug 46 and the wire 48 of the upper internal connection structure 40. The through-hole TV extends through the dielectric layer 107 in the opening 105 and is electrically connected to the underlying internal connection structure 130. Since the conductor plug COA is connected to the conductor layers 126 of the plurality of steps of different heights of the step structure SC, the plurality of conductor plugs COA have various depths. For example, in Figure 3A Or the depth of the conductor plug COA in 10A is shallow, Figure 3B or Fig. 10B The depth of the conductor plug COA is deeper.

[0111] Reference Figure 2R and Fig.9E, the multiple conductor plugs COA and the multiple through-holes TV have different depths. In particular, the depths of the through-holes TV and some conductor plugs COA connected to the lower steps are quite deep, which is very difficult to control in terms of process. In the embodiment of the present invention, after the step structure SC is formed and before the multiple conductor plugs COA and the multiple through-holes TV are formed, the liner 150 and the stop layers 152 and 154 (such as the bottom layer 154) are first covered on the surface of the step structure SC. Figure 1D , Figure 2D , Fig.8D as well as Fig.9E As shown in Figure 2R and Fig.9E As shown, the multiple conductor plug holes OP1 and the multiple perforation openings OP2 of the multiple conductor plugs COA and the multiple perforations TV are formed by a multi-stage etching process. In the multi-stage etching process, the stop layers 152 and 154 can be used as etching stop layers in the first stage etching process. The liner 150 can be used as an etching stop layer in the second stage etching process. Therefore, the embodiment of the present invention helps to form multiple conductor plug holes OP1 and multiple perforation openings OP2 of various depths through the arrangement of the liner 150 and the stop layers 152 and 154. A more detailed method for manufacturing the memory element will be described in the subsequent description.

[0112] The embodiments of the present invention can be applied to memory devices of various architectures. The following is an explanation of the manufacturing method of a memory device with a CMOS-Bonded-Array (CbA) structure. However, the embodiments of the present invention are not limited thereto. The embodiments of the present invention can also be used for a memory device with a CMOS-Under-Array (CUA) structure.

[0113] Figures 1A to 1D is a top view of an intermediate stage of a method for manufacturing a memory device according to an embodiment of the present invention. Figures 2A to 2R FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing a memory element according to an embodiment of the present invention. Figure 1A and Figure 1D It is shown as Figure 2A and Figure 2Q A top view of the line III-III' and IV-IV' of the mid-step region SCR. Figure 2A and Figure 2Q The step area SCR (including Figures 1A to 1D 2 different directions D1 and D2 of the line II' and II-II') and a schematic cross-sectional view of the memory array region ARR. Direction D1 is, for example, a direction parallel to the bit line. Direction D2 is, for example, a direction parallel to the word line. Figure 2RSchematic cross-sectional view of the step region SCR, the memory array region ARR and the peripheral region PRR is shown in FIG.

[0114] Reference Figure 2A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. An insulating layer 101 and a stop structure 103 are formed on the substrate 100. The insulating layer 101 is, for example, silicon oxide. The stop structure 103 is formed on the insulating layer 101. The stop structure 103 may include a plurality of insulating layers 92 and a plurality of conductive layers 94 alternately stacked with each other. The insulating layer 92 is, for example, silicon oxide, and the conductive layer 94 is, for example, polysilicon. An insulating structure 103a has been formed in the stop structure 103.

[0115] Reference Figure 2A , a lower portion LP of a stacked structure (or first stacked structure) SK1 is formed on the surface of the stop structure 103. The lower portion LP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 that are alternately stacked. In some embodiments, the material of the insulating layer 102 includes silicon oxide, and the material of the intermediate layer 104 includes silicon nitride. The intermediate layer 104 can be used as a sacrificial layer, which will be partially removed in a subsequent process.

[0116] Reference Figure 2A , then, a plurality of dummy columns DVC are formed, extending through the lower LP of the stacked structure SK1. The plurality of dummy columns DVC can be formed into openings (not shown) by a single-stage photolithography and etching process or a multi-stage photolithography and etching process. The opening extends through the lower LP of the stacked structure SK1 to the stop structure 103, and even to the insulating layer 101. Then, a filling material (or self-aligned material) is filled into the opening to form. The profile of the sidewall of the opening formed by the multi-stage photolithography and etching process is, for example, bamboo-shaped.

[0117] Reference Figure 2A , an upper portion UP of the stacked structure SK1 is formed above the substrate 100. The upper portion UP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked on each other. The materials of the insulating layers 102 and the intermediate layers 104 of the upper portion UP of the stacked structure SK1 are the same as the materials of the insulating layers 102 and the intermediate layers 104 of the lower portion LP of the stacked structure SK1. Afterwards, a hard mask layer HM is formed on the upper portion UP of the stacked structure SK1. The hard mask layer HM is, for example, polysilicon.

[0118] Reference Figure 2BThen, the hard mask layer HM is patterned. The hard mask layer HM is used as a mask to pattern the middle layer 104 and the insulating layer 102 of the stacked structure SK1 to form an opening 105 and a stepped structure SC. In some embodiments, the opening 105 and the stepped structure SC can be formed by a multi-stage patterning process. The patterning process can include processes such as photolithography, etching, and trimming.

[0119] Figure 1A It is along FIG. 2B to FIG. 2D Top view of lines III-III' and -IV-IV'.

[0120] Reference Figure 1A and Figure 2B , the opening 105 is, for example, rectangular. For example, the opening 105 has four side walls sw1, sw2, sw3, and sw4. The side wall sw1 is connected to the side wall sw2, the side wall sw2 is connected to the side wall sw3, the side wall sw3 is connected to the side wall sw4, and the side wall sw4 is connected to the side wall sw2. The side walls sw1 and sw3 are arranged opposite to each other, and the side walls sw2 and sw4 are arranged opposite to each other. The bottom ends of the side walls sw1, sw2, sw3, and sw4 are connected to the step structure SC at the bottom of the opening 105.

[0121] Reference Figure 1A and Figure 2B A liner 150 and a stop layer 152 are formed on the hard mask layer HM and on the multiple steps S1 to S10 of the step structure SC in the opening 105. The liner 150 is a conformal layer, covering the upper surface of the hard mask layer HM and the surface of the step structure SC at the bottom of the opening 105, as well as the side walls sw1, sw2, sw3 and sw4. The stop layer 152 covers the surface of the liner 150. The material of the liner 150 includes silicon oxide. The material of the stop layer 152 can be the same as or similar to the material of the intermediate layer 104. The material of the stop layer 152 includes silicon nitride. In an embodiment of the present invention, the thickness T1 of the stop layer 152 is greater than the thickness T2 of the intermediate layer 104. The thickness T1 is, for example, more than twice the thickness T2.

[0122] Reference Figure 2C , a dielectric material (not shown) is formed on the stacked structure SKI and fills the opening 105. The dielectric material is, for example, silicon oxide. A planarization process is then performed, such as a chemical mechanical polishing process, using the hard mask layer HM as a polishing stop layer to remove excess insulating material, so as to form dielectric layers 107 in the openings 105.

[0123] Reference Figure 2D , the hard mask layer HM and the liner 150 and the stop layer 152 thereon are removed, leaving the liner 150 and the stop layer 152 filling the opening 105 .

[0124] Reference Figure 1A and Figure 2C , the liner 150 remaining in the opening 105 includes a plurality of portions 150a and 150b. The stop layer 152 remaining in the opening 105 includes a plurality of portions 152a and 152b. The portions 150a and 152a cover the surface of the step structure SC. The portions 150b and 152b cover the sidewalls of the stacked structure SK1 exposed in the opening 105. For simplicity, the plurality of portions 150a of the liner 150 are also referred to as the liner 150a. The plurality of portions 150b of the liner 150 are also referred to as the liner 150b. The plurality of portions 152a of the stop layer 152 are also referred to as the stop layer 152a. The plurality of portions 152b of the stop layer 152 are also referred to as the stop layer 152b.

[0125] Reference Figure 2D and Figure 2E , after which a patterning process is performed to remove part of the stacked structure SK1 to form an opening (not shown) and expose the dummy column DVC. Next, the dummy column DVC exposed by the opening is removed to form one or more openings 106 extending through the stacked structure SK1. In one embodiment, the opening 106 may have a slightly inclined sidewall. In another embodiment, the opening 106 may have a substantially vertical sidewall (not shown). In one embodiment, the opening 106 is also referred to as a vertical channel hole. In one embodiment, the opening 106 can be formed via a single-stage photolithography and etching process. In another embodiment, the opening 106 is formed by multiple stages of photolithography and etching processes. The profile of the sidewall of the opening 106 formed by multiple stages of photolithography and etching processes is, for example, bamboo-shaped.

[0126] Reference Figure 2E Then, a charge storage structure 108 is formed in the opening 106. The charge storage structure 108 is in contact with the insulating layer 102 and the intermediate layer 104. In one embodiment, the charge storage structure 108 is an oxide / nitride / oxide (ONO) composite layer. The charge storage structure 108 is, for example, a conformal layer, which is formed on the sidewalls and the bottom of the opening 106. Then, a channel column VC is formed in the remaining space of the opening 106. The channel column VC can be formed by the following method.

[0127] Continue to refer to Figure 2E, a channel layer 110 is formed on the inner sidewall and bottom surface of the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes undoped polysilicon. Next, an insulating column (or core insulating column) 112 is formed on the inner surface of the channel layer 110. In one embodiment, the material of the insulating column 112 includes silicon oxide. Thereafter, a channel plug 114 is formed in the opening 106, and the channel plug 114 contacts the channel layer 110. The channel plug 114 extends from the top surface of the uppermost insulating layer 102 to a certain depth of the opening 106. In one embodiment, the material of the channel plug 114 includes a semiconductor material with doping, such as doped polysilicon. The channel layer 110, the insulating column 112, and the channel plug 114 can be collectively referred to as a channel column VC. The channel column VC passes through the stacked structure SK1 and extends to the stop structure 103, and even extends to the insulating layer 101. The charge storage structure 108 surrounds the vertical outer surface of the channel column VC.

[0128] Continue to refer to Figure 2E , and then, a dielectric layer 115 is formed on the stacked structure SK1. Next, a plurality of support pillars PIC are formed. The plurality of support structures PIC may extend from the top surface of the dielectric layer 115 through the stacked structure SK1 and the stop layer 103 to prevent the step structure SC from collapsing during the subsequent removal of the intermediate layer 104. The support structure PIC may include an insulating material or an insulating material and a conductive material. In other embodiments, the support structure PIC may be formed at the same time as the charge storage structure 108 and the channel pillar VC are formed. The plurality of support structures PIC respectively have the same structure as the structure formed by the charge storage structure 108 and the channel pillar VC, but the present invention is not limited thereto. For simplicity, the plurality of support structures PIC will not be shown later.

[0129] Reference Figure 2F , a dielectric layer 128 is formed on the stacked structure SK1. The dielectric layer 128 is, for example, silicon oxide. A patterning process is performed to form one or more separation trenches 116. The separation trenches 116 may have wavy sidewalls, vertical sidewalls (not shown), or slightly inclined sidewalls (not shown). The separation trenches 116 may include the separation trenches 116 1 With 116 2 .

[0130] Reference Figure 2F , separation channel 116 1 The topmost conductor layer 94 extends through dielectric layers 128, 115, 107, portion 152a of stop layer 152, portion 150a of liner layer 150, and stop layer 103. Separation trench 116 2 The dielectric layer 128 , 115 and the stack structure SK1 and the stop layer 103 are extended to divide the stack structure SK1 into a plurality of blocks (not shown).

[0131] Figure 1B It is along Figure 2F Top view of lines III-III' and -IV-IV'.

[0132] Reference Figure 1B , separation channel 116 1 With 116 2 Extending along the direction D2 and arranged along the direction D1. Separation channel 116 1 With 116 2 Substantially parallel. Separating channel 116 1 In the separation channel 116 2 Separating channel 116 1 The separation channel 116 extends through the step structure SC and divides the step structure SC into two parts SC1 and SC2. 2 Between two step structures SC, or between two openings 105 .

[0133] Reference Figure 1B , separation channel 116 1 The separation channel 116 extends through the side walls sw1 and sw3 of the opening 105. That is, the separation channel 116 intersects the side walls sw1 and sw3. 1 The stop layer 152b is located between the sidewalls sw2 and sw4 of the same opening 105 and is separated from the stop layer 152b on the sidewalls sw2 and sw4 by distances d3 and d4. 1 The intersecting side walls sw1 and sw3 may also be referred to as intersecting side walls. 1 The intersecting sidewalls sw2 and sw4 may also be referred to as non-intersecting sidewalls or parallel sidewalls. The parallel sidewalls described herein may not actually be completely parallel, but only represent non-intersecting sidewalls. 1 In an embodiment of the present invention, the sidewalls of the separation channel 116 1 The stop layer 152b and the liner 150b on the intersecting sidewalls sw1 and sw3 and the stop layer 152a and the liner 150a on the bottom surface are exposed by the separation channel 116. 1 The stop layer 152b and the liner 150b on the intersecting sidewalls sw2 and sw4 are not separated from the channel 116. 1 Exposed. Separating channel 116 2 It is located between the sidewalls sw2 and sw4 of two adjacent openings 105 and does not intersect with any sidewall of the opening 105. It is separated from the stop layer 152b on the sidewalls sw2 and sw4 by distances d5 and d6. The distances d5 and d6 are smaller than the distances d3 and d4.

[0134] Continue to refer to Figures 2F to 2H , a gate replacement process is performed to replace part of the intermediate layer 104 with the conductor layer 126, and part of the stop layer 152 is replaced with the conductor layer 126. First, referring to Figure 2F and Figure 2G , a selective etching process is performed to allow the etchant to contact the middle layer 104 of the stacked structure SK1 on both sides through the separation channel 116. In this way, a portion of the middle layer 104 is removed to form a plurality of horizontal openings 121a, leaving the middle layer 104 in the peripheral area (shown in FIG. Figure 2R The selective etching process may be an isotropic etching process, such as a wet etching process. The etchant used in the wet etching process may be hot phosphoric acid.

[0135] Figure 1C It is along Figure 2G Top view of lines III-III' and IV-IV'.

[0136] Reference Figure 1B , 1C and Figure 2G , during the selective etching process, the separation channel 116 is exposed 1 In the example of the present invention, the stop layer 152b on the sidewalls sw1 and sw3 of the opening 105 and the stop layer 152a on the bottom surface of the opening 105 are partially removed by contact with the etchant, thereby forming a U-shaped tunnel 121b (shown in FIG. Figure 2G The stop layer 152b on the sidewalls sw2 and sw4 of the opening 105 is not separated from the channel 116. 1 and 116 2 Exposed, and 116 meters from the separation channel 1 The distances d3 and d4 are far away, and the etchant cannot flow through the self-isolation channel 116 due to the limited flow path of the etchant. 1 On the other hand, the stop layer 152b on the sidewalls sw2 and sw4 of the opening 105 is in contact with the separation channel 116. 2 The distances are relatively close (distances d5 and d6), but due to the blocking of the liner 150b, they cannot be connected to the separation channel 116. 2 Therefore, the stop layer 152b on the sidewalls sw2 and sw4 of the opening 105 will be left. Figure 2R As shown, the stop layer 152 in the peripheral region PRR is further away from the separation trench 116 and is retained because it cannot contact the etchant. The stop layer 152 will be used as an etching stop layer in the subsequent process of forming the through-hole opening OP2, which will be described in detail later.

[0137] Reference Figure 2GIn the embodiment of the present invention, since the thickness T1 of the stop layer 152 is greater than the thickness T2 of the intermediate layer 104, after the stop layer 152 and the intermediate layer 104 are partially removed, the width W1 of the U-shaped tunnel 121b at the bottom of the opening 105 is greater than the width W2 of the horizontal opening 121a. In some embodiments, the width W1 of the open U-shaped tunnel 121b is, for example, more than twice the width of the horizontal opening 121a. The width W1 of the U-shaped tunnel 121b is less than the minimum width (e.g., bottom width) W3 of the separation channel 116.

[0138] Continue to refer to Figure 2G and Figure 2H , a conductor layer 126 is formed on the dielectric layer 128. The conductor layer 126 is also filled into the separation trench 116, the horizontal opening 121a and the U-shaped tunnel 121b. The conductor layer 126, for example, includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W). Part of the intermediate layer 104 is replaced by the conductor layer 126, thereby forming a stacked structure (also referred to as a second stacked structure) SK2. Another part of the intermediate layer 104 is retained in the peripheral region PRR, such as Figure 2R shown.

[0139] In the embodiment of the present invention, the thickness T3 of the conductive layer 126 is smaller than the width W1 of the U-shaped tunnel 121b at the bottom of the opening 105 (below the dielectric layer 107) and the bottom width W3 of the separation channel 116. The conductive layer 126 can fill the horizontal opening 121a, but cannot fill the U-shaped tunnel 121b and the separation channel 116.

[0140] Reference Fig.2I , an etching process is performed to remove the conductor layer 126 in the U-shaped tunnel 121b and the separation channel 116. When performing the etching process, the etchant can contact the conductor layer 126 through the remaining space between the separation channel 116 and the U-shaped tunnel 121b, so that the conductor layer 126 in the U-shaped tunnel 121b and the separation channel 116 can be completely removed. The conductor layer 126 in the horizontal opening 121a is left as a gate layer or a word line WL. A plurality of conductor layers 126 and a plurality of insulating layers 102 are alternately stacked to form a stacked structure SK2.

[0141] Reference Figure 2J, a stop layer 154 is formed on the dielectric layer 128. The stop layer 154 also fills the U-shaped tunnel 121b and the separation trench 116. The stop layer 154 may fill the U-shaped tunnel 121b, but not the separation trench 116. The stop layer 154 includes a material different from that of the dielectric layer 107. The stop layer 154 may be a single layer or a multilayer. The stop layer 154 may be an insulating material, a conductive material, or a combination thereof, which will be described in detail later.

[0142] Reference Figure 2K , an etching process is performed to remove all the stop layer 154 on the dielectric layer 128 and in the separation trench 116, exposing the top surface of the dielectric layer 128 and the sidewalls and bottom surface of the separation trench 116. The stop layer 154 in the U-shaped tunnel 121b is left. The stop layer 154 is located between the dielectric layer 107 and the liner 150.

[0143] The stop layer 154 remaining in the U-shaped tunnel 121b includes a plurality of portions 154a and 154b. For simplicity, the plurality of portions 154a of the stop layer 154 are also referred to as the stop layer 154a. The plurality of portions 154b of the stop layer 154 are also referred to as the stop layer 154b. The stop layer 154a covers the surface of the step structure SC. The stop layer 154b covers the sidewall of the dielectric layer 107. The sidewall of the stop layer 154a below the dielectric layer 107 is connected to the stop layer 152b. The liner 150a and the stop layer 154a extend continuously to cover the plurality of steps of the step structure SC.

[0144] Figure 1D It is along Fig.2I , Figure 2K , Figures 2L to 2O Top view of lines III-III' and IV-IV'.

[0145] Reference Figure 1D and Figure 2K , including a dielectric layer 107, a liner 150, a stop layer 152b and a stop layer 154 in the opening 105. The stop layer 152b is between the side wall sw2 of the opening 105 and the side wall of the dielectric layer 107. The stop layer 154b is between the side wall sw1 of the opening 105 and the side wall of the dielectric layer 107. The stop layer 154b is also between the side wall sw3 of the opening 105 and the side wall of the dielectric layer 107. The stop layer 154a is between the bottom of the opening 105 and the stepped structure SC. The liner 150b is on the side walls sw1 to sw4 of the opening 105 and surrounds the stop layer 152b and the side wall of the stop layer 154b. The liner 150a is located at the bottom of the opening 105 and between the stop layer 154a and the stepped structure SC.

[0146] Reference Figure 2KNext, an etching process is performed to deepen the separation trench 116 and partially remove the middle conductor layer 94 and the upper and lower insulating layers 92 in the stop structure 103 to form a horizontal opening 123 .

[0147] Reference Figure 2L , a conductor layer 93 is formed in the horizontal opening 123. The conductor layer 93 in the horizontal opening 123 may form a common source line CSL with the conductor layer 94. The common source line CSL is electrically connected to a plurality of channel pillars VC. The conductor layer 93 is, for example, doped polysilicon. Next, a filling layer 118 is formed in the space separating the channel 116 to form a partition wall SLT. The filling layer 118 may include a material different from that of the stop layers 152 and 154. The filling layer 118 includes an insulating material, for example, silicon oxide. The partition wall SLT may include a partition wall SLT 1 With SLT 2 . Partition Wall SLT 1 With SLT 2 are electrically isolated from each other.

[0148] Reference Figure 1D and Figure 2L , partition wall SLT 1 The step structure SC extends through the opening 105. The partition wall SLT 1 Located between two rows (C1 and C2) of conductor plugs COA to be formed subsequently, it extends through the dielectric layer 107, the portion 154a4 of the stop layer 154, the liner 150 and the stepped structure SC, and divides the stop layer 154a into a plurality of sub-portions F1 and F2.

[0149] Reference Figure 1D , partition wall SLT 2 Between two step structures SC, or between two openings 105. Partition wall SLT 2 Extending through the stack structure SK2. The two portions 152b of the stop layer 152, the stop layer 154, the two rows (C1 and C2) of conductor plugs COA formed subsequently, and the partition wall SLT 1 Located between two dividing walls SLT 2 between.

[0150] Reference Figure 2L Then, a stop layer 129 and a dielectric layer 131 are formed on the dielectric layer 128. The stop layer 129 is, for example, silicon nitride, and the dielectric layer 131 is, for example, silicon oxide.

[0151] Reference Figure 2M to Figure 2O Then, a plurality of conductor plugs COA are formed in the step region SCR to electrically connect the conductor layer 126 and the channel column VC respectively. Figure 2R, a plurality of perforations TV are formed in the peripheral region PRR. Figure 2M The method for forming the conductor plug COA and the through hole TV can first perform a photolithography and etching process to form a plurality of conductor plug holes OP1 and a plurality of through hole openings OP2. In an embodiment of the present invention, the etching process is a multi-stage etching process. First, the stop layer 154a in the step region SCR and the stop layer 152a in the peripheral region PRR are used as etching stop layers, and a first-stage etching process is performed to form a plurality of conductor plug holes OP1 exposing the stop layer 154a in the dielectric layer 131 to the dielectric layer 107, and to form a plurality of through hole openings OP2 exposing the stop layer 152a. Since the stop layers 154a and 152a have sufficient thickness and a sufficient etching selectivity with the dielectric layer 107, even if the thickness of the dielectric layer 107 in different areas of the substrate 100 (the step area SCR and the peripheral area PRR) or on each step of the step structure SC is quite different, the multiple conductor plug holes OP1 and the through-hole openings OP2 with a considerable depth difference can still be effectively controlled to stop on the stop layer 154a and the stop layer 152a respectively.

[0152] Reference Figure 2N and Figure 2R , a second stage etching process is performed, and the liner 150a can be used as an etching stop layer to remove the stop layers 152a and 154a. Then, a third stage etching process is performed to remove the liner 150, so that the depth of the conductor plug hole OP1 and the through-hole opening OP2 is deepened until the conductor layer 126 and the conductor layer 93 of the stop structure 103 are exposed. Due to the second and third stage etching processes, the stop layers 154a and 152a are removed first, and then the liner 150a is removed. Compared to the first stage etching process that removes the relatively thick dielectric layer 107, the thickness of the stop layers 154a and 152a and the liner 150a in each area of ​​the substrate 100 (the step area SCR and the peripheral area PRR) or each step of the step structure SC is relatively thin. Therefore, the second and third stage etching processes can more easily control the depth of the conductor plug hole OP1 and the through-hole opening OP2, thereby exposing the conductor layer 126 and the conductor layer 93 respectively without etching through the conductor layer 126 or 93.

[0153] Reference Fig.2O and Figure 2R, a conductor material is formed on the dielectric layer 131, and the conductor material is also filled into the conductor plug hole OP1 and the through-hole opening OP2. Afterwards, a back etch or chemical mechanical polishing process is performed to remove the conductor material on the dielectric layer 131, and a plurality of conductor plugs COA and a plurality of through-holes TV are formed in the conductor plug hole OP1 and the through-hole opening OP2. The conductor material includes, for example, a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W). Referring to Figure 3A , Figure 3B as well as Figure 2R By using the method of the embodiment of the present invention, a plurality of conductor plugs COA and a plurality of through holes TV with different depths can be formed.

[0154] Reference Figure 2P and Figure 2R , an internal connection structure 130 is formed above the substrate 100. The internal connection structure 130 may include multiple dielectric layers (not shown) and internal connections (not shown) formed in the multiple dielectric layers. The internal connections include multiple plugs (not shown) and multiple wires (not shown). The dielectric layer separates adjacent wires. The wires can be connected through plugs, and the wires can be connected to multiple conductor plugs COA and multiple through-holes TV through multiple plugs. The internal connection structure 130 can be formed in a single metal damascene process, a dual metal damascene process, or in any known manner. The internal connection structure 130 may include multiple bit lines BL. Multiple bit lines BL can be electrically connected to the channel column VC via multiple conductor plugs COA'. The conductor plug COA' can be formed simultaneously when forming multiple conductor plugs COA and multiple through-holes TV, or can be formed at different times.

[0155] Reference Figure 2Q , a bonding structure 132 is formed on the inner connection structure 130. The bonding structure 132 includes a bonding dielectric layer (not shown) and a bonding plug (not shown) and a bonding pad (not shown) buried in the bonding dielectric layer. The bonding pad can be connected to the wire of the inner connection structure 130 via the bonding plug. The bonding dielectric layer, the bonding plug and the bonding pad can be formed by any known method. At this point, the production of the wafer 100W is completed.

[0156] Reference Figure 2R , the wafer 100W is turned over. After the wafer 100W is turned over, the step structure SC on the substrate 100 becomes an inverted step structure RSC. The conductor plug COA is below the inverted step structure RSC.

[0157] Next, a bonding process is performed, such as a hybrid bonding process. The bonding structure 132 is bonded to the bonding structure 32 of another chip 10W. The chip 10W may include a substrate 10, a component layer 20, an internal wiring structure 30 and a bonding structure 32. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor device (CMOS). The component layer 20 may include a page buffer, a peripheral circuit, and a row decoder and a column decoder. The internal wiring structure 30 and the bonding structure 32 may have the same or similar components as the internal wiring structure 130 and the bonding structure 132, respectively. In the embodiment of the present invention, the device layer 20 having complementary metal oxide semiconductor devices (CMOS) and the memory array ARY originally belong to different chips 10W and 100W, but are bonded together with the memory array ARY in a bonding manner. This structure can also be called a CMOS-Bonded-Array (CbA) structure.

[0158] In some embodiments, a semiconductor through-hole (or silicon through-hole via) 16 is further formed in the substrate 100 of the wafer 10W. The semiconductor through-hole (or silicon through-hole via) 16 is electrically isolated from the substrate 10 by the liner 14. The semiconductor through-hole 46 is electrically connected to the through-hole TV via the interconnect structure 30, the bonding structure 32, 132 and the interconnect structure 130. The liner 14 is, for example, silicon oxide. The material of the semiconductor through-hole (or silicon through-hole via) 16 is, for example, copper or tungsten.

[0159] Reference Figure 2R After the bonding process, the substrate 100 is removed to expose the insulating layer 101. The substrate 100 can be removed by polishing, polishing or etching. In other embodiments, the substrate 100 is thinned, and a portion is still retained (not shown) and connected to the interconnect structure 130 through a semiconductor through hole (or silicon through hole) formed in the substrate 100.

[0160] Reference Figure 2R, and perform the back-end process. A liner 44, a conductor plug 46, a wire 48, and a dielectric layer 50 of the interconnect structure 40 are formed on the insulating layer 101. The conductor plug 46 electrically connects the through-hole TV and the wire 48. The conductor plug 46 is electrically isolated from the conductor layer 94 of the stop structure 103 by the liner 44. The method for forming the interconnect structure 40 is described as follows. First, a photolithography and etching process is performed to form a conductor plug opening 43 in the insulating layer 101 and the stop structure 103. Next, a liner 44 and a conductor plug 46 are formed in the conductor plug opening 43. The method for forming the liner 44 is, for example, to form a dielectric material on the insulating layer 101 and in the conductor plug opening 43, and then perform anisotropic etching. The method for forming the conductor plug 46 is, for example, to form a conductor material on the insulating layer 101 and in the conductor plug opening 43, and then perform a chemical mechanical polishing process or back etching. The dielectric material is, for example, silicon nitride or a silicon oxide / silicon nitride / silicon oxide composite layer. The conductor material is, for example, doped polysilicon. Afterwards, a conductor 48 and a dielectric layer 50 are formed on the insulating layer 101. The material of the conductor 48 is, for example, copper or tungsten. The dielectric layer 50 can be a single layer or a multilayer. The material of the dielectric layer 50 can be silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. The interconnect structure 40 can be electrically connected to the interconnect structures 130 and 30 via the through-hole TV. In addition to being connected to the through-hole TV, the interconnect structure 130 can also be electrically connected to the channel column VC or the conductor layer 126 (for example, the word line WL) via the conductor plug COA'.

[0161] Afterwards, connectors 52 are formed on the wires 48. The connectors 52 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, C2 bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or similar components. At this point, the fabrication of the memory chip SM1 is completed.

[0162] Reference Figure 1D and Figure 2R In this embodiment, multiple conductor layers 126 and multiple insulating layers 102 are alternately stacked between two adjacent openings 105 in the step region SCR. The liner 150 and the stop layer 154 in the step region SCR are not only left at the bottom of the opening 105 as an etching stop layer, but also on the sidewalls sw1 and sw3 of the opening 105 (such as Figure 1D The liner 150 and the stop layer 152 in the step region SCR remain on the sidewalls sw2 and sw4 of the opening 105 (as shown in FIG. Figure 1D The liner 150 and the stop layer 152 in the peripheral region PRR remain at the bottom of the opening 105 as an etching stop layer, and also remain on the sidewalls of the opening 105 (as shown). Figure 2R shown).

[0163] Figure 4A and Figure 4B A partial cross-sectional schematic diagram of a plurality of stop layers and liner layers according to an embodiment of the present invention is shown.

[0164] Reference Figure 4A and Figure 4B , the stop layers 154 and 152b, the liner 150 and the dielectric layer 107 of the embodiment of the present invention are located in the opening 105. The stop layers 154 and 152b are located between the liner 150 and the dielectric layer 107. The stop layer 152b is located between the sidewall of the opening 105 and the sidewall of the dielectric layer 107. The stop layer 154a located at the bottom of the opening 105 is buried under the dielectric layer 107, covers the conductor layer 126 of the step structure SC, and is laterally adjacent to and connected to the stop layer 152b. The partition wall SLT 1 The dielectric layer 107, the stop layer 154, the liner 150 and the step structure SC are extended through the opening 105. The stop layer 154a at the bottom of the opening 105 is separated by the partition wall SLT. 1 Extends through and is divided into two sub-portions F1 and F2.

[0165] Reference Figure 4A and Figure 4B , the width T4 of the stop layer 154a at the bottom of the opening 105 (below the dielectric layer 107) is greater than the width T3 of the conductor layer 126. In some embodiments, the thickness T4 of the stop layer 154a at the bottom of the opening 105 (below the dielectric layer 107) is more than twice the thickness T3 of the conductor layer 126. The thickness T4 of the stop layer 154a is less than the bottom width W3 of the partition wall SLT. Therefore, during the process of forming the stop layer 154, the stop layer 154 cannot fill the partition trench 116 (shown in FIG. Figure 2J ) to facilitate the subsequent removal process. The length L1 of the sub-portion F1 (or F2) of the stop layer 154a at the bottom of the opening 105 (below the dielectric layer 107) is less than the length of the partition wall SLT 1 With SLT 2 of the distance P1 and is greater than half of the distance P1.

[0166] Reference Figure 4A and Figure 4BThe stop layer 154 may be a single layer or a multilayer. The material of the stop layer 154 may include an insulating layer, a conductive layer, or a combination thereof. The insulating layer may include SIN, SiCN, SiCON, a high dielectric constant material (e.g., Al2O3, Hf2O5), or a combination thereof. The conductive layer may include polysilicon, tungsten, cobalt, copper, tantalum, titanium, tantalum nitride, titanium nitride, metal silicide, or a combination thereof.

[0167] Reference Figure 4A For example, the stop layer 154 may include a material layer 154 1 With 154 2 . Material layer 154 1 Wrapped in material layer 154 2 The material layer 154 1 For example, it is a high dielectric constant material layer. The high dielectric constant material layer can be formed before forming the conductor layer 126, so it can also extend to cover the upper and lower surfaces of the conductor layer 126 and the sidewalls of the separation trench 116. 2 It can be an insulating filling layer, such as silicon nitride, or a conductive filling layer, such as polysilicon. 2 It can be formed by deposition method, and in the material layer 154 2 An interface 154I is formed.

[0168] Reference Figure 4B For example, the stop layer 154 may include a material layer 154 1 , 154 2 With 154 3 . Material layer 154 1 Coating material layer 154 2 Outer wall. Material layer 154 2 Between the material layer 154 1 With 154 3 Material layer 154 1 For example, it is a high dielectric constant material layer. The high dielectric constant material layer can be formed before forming the conductor layer 126, so it can also extend to cover the upper and lower surfaces of the conductor layer 126 and the sidewalls of the separation trench 116. 1 The layer 114 may remain in the separation trench 116 and form a separation wall SLT together with the filling layer 118 .

[0169] Material layer 154 2The barrier layer may be a barrier layer, such as tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. The barrier layer may be formed before forming the conductor layer 126, so that it also extends to cover the upper and lower surfaces of the conductor layer 126 and the sidewalls of the separation wall SLT. The barrier layer covering the upper and lower surfaces of the conductor layer 126 may be retained, while the barrier layer on the sidewalls of the separation trench 116 is removed. The material layer 154 3 It can be a conductor filling layer. The conductor filling layer includes a metal layer, such as tungsten. Material layer 154 3 It can be formed by deposition method, and in the material layer 154 3 An interface 154I is formed.

[0170] Figure 4C and Figure 4D A partial cross-sectional schematic diagram showing a conductor plug extending through a plurality of stop layers and liner layers according to an embodiment of the present invention.

[0171] Reference Figure 4C and Figure 4D The conductor plug COA of the embodiment of the present invention is located at the partition wall SLT 1 With SLT 2 The conductor plug COA extends through the dielectric layer 107, the stop layer 154 and the liner 150, and lands on the conductor layer 126 of the step structure SC, and is electrically connected to the conductor layer 126. The conductor plug COA may include a single layer or multiple layers. The conductor plug COA may include an insulating material, a conductive material or a combination thereof. The insulating material is, for example, silicon oxide, and the conductive material is, for example, polysilicon, tungsten, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof.

[0172] Reference Figure 4C When the stop layer 154 is an insulating material, the conductor plug COA can be a conductor material 156, for example, including a barrier layer 1561 and a conductor filling layer 1562. The barrier layer 1561 is on the sidewall and bottom surface of the conductor filling layer 1562, for example, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. The conductor filling layer 1562 includes a metal layer, for example, tungsten.

[0173] Reference Figure 4D , the stop layer 154 includes a conductor material (ie, the material layer 154 2 is a barrier layer, material layer 154 3 When the conductor plug COA is a conductor filling layer, the conductor plug COA may include a lining material 157 and a conductor material 156. The conductor material 156 may include a barrier layer 1561 and a conductor filling layer 1562. The lining material 157 surrounds the sidewall of the barrier layer 1561 to electrically isolate the barrier layer 1561 from the material layer 154. 2 (barrier layer), and electrically isolates the barrier layer 1561 from the material layer 154 3(Conductor filling layer) The liner material 157 is, for example, silicon oxide or silicon nitride or a combination thereof. The barrier layer 1561 is on the sidewall and bottom surface of the conductor filling layer 1562, for example, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. The conductor filling layer 1562 includes a metal layer, for example, tungsten.

[0174] In the above embodiments, referring to Figure 2J and Figure 2K , the stop layer 154 on the dielectric layer 128 and in the separation trench 116 is completely removed, however, the embodiment of the present invention is not limited thereto. The stop layer 154 may be thinned or not thinned and remain on the sidewall and bottom of the separation trench 116, or the stop layer 154 at the bottom of the separation trench 116 may be partially removed, respectively. FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6B as well as FIG. 7A to FIG. 7C shown.

[0175] exist FIG. 5A to FIG. 5C In the process of FIG. 1 , a stop layer 154 (shown in FIG. 1 ) is formed on the dielectric layer 128 and in the separation trench 116. Figure 5A ) is thinned to a stop layer 154' (shown in Figure 5B ). Then, the stop layer 154' on the dielectric layer 128 is removed by an anisotropic etching process, leaving the stop layer 154' on the sidewall and bottom surface of the separation trench 116. The stop layer 154' and the subsequently formed filling layer 118 together form the separation wall SLT 1 With SLT 2 (Shown in Figure 5C ).

[0176] exist FIG. 6A to FIG. 6B In the process of Fig. 6A ), the stop layer 154 is not thinned, but directly subjected to an anisotropic etching process to remove the stop layer 154 on the dielectric layer 128, leaving the stop layer 154 on the sidewall and bottom surface of the separation trench 116. The stop layer 154 and the subsequently formed filling layer 118 together form the separation wall SLT 1 With SLT 2 (Shown in Figure 6B ).

[0177] exist FIG. 7A to FIG. 7C In the process of Fig. 7A ), the stop layer 154 is not thinned, but directly subjected to an anisotropic etching process to remove the stop layer 154 on the dielectric layer 128 and the bottom of the separation trench 116, leaving the stop layer 154 on the sidewall of the separation trench 116 (shown in Figure 7B The stop layer 154 and the subsequently formed filling layer 118 together form a partition wall SLT. 1 With SLT 2(Shown in Figure 7C ).

[0178] FIG. 8A to FIG. 8D is a top view of an intermediate stage of a method for manufacturing a memory device according to another embodiment of the present invention. FIG. 9A to FIG. 9E FIG. 1 is a cross-sectional view of a method for manufacturing a memory element according to another embodiment of the present invention. Fig. 8A and Fig.8D It is shown as Fig. 9A and Fig.9D A top view of the line VIII-VIII' and IX-IX' in the middle step area. Fig. 9A and Fig.9D Shown as a step area (including FIG. 8A to FIG. 8D 2. The cross-section of the line VI-I' and the line VII-VII' in two different directions D1 and D2) and the cross-section diagram of the memory array area ARR. The direction D1 is, for example, a direction parallel to the bit line. The direction D2 is, for example, a direction parallel to the word line. Fig.9E Schematic cross-sectional view of the step region SCR, the memory array region ARR and the peripheral region PRR is shown in FIG.

[0179] Reference Fig. 9A According to the above method, an insulating layer 101, a stop structure 103 and a lower portion LP of a stacked structure (or first stacked structure) SK1 are formed on a substrate 100. Then, a plurality of dummy columns DVC are formed in the lower portion LP of the stacked structure SK1. After that, an upper portion UP of the stacked structure SK1 and a hard mask layer HM are formed above the substrate 100. Then, the hard mask layer HM is patterned. Using the hard mask layer HM as a mask, the intermediate layer 104 and the insulating layer 102 of the stacked structure SK1 are patterned to form an opening 105A and a stepped structure SC.

[0180] Fig. 8A It is along FIG. 9A to FIG. 9B Top view of lines VIII-VIII' and -IX-IX'.

[0181] Reference Fig. 8A and Fig. 9A The opening 105A is, for example, rectangular. The range of the opening 105A is quite large, covering Figure 1A The two adjacent openings 105 and the area between them and the surrounding area. Figure 1A In the embodiment, the step structures SC exposed by the two openings 105 are independent and separate. Fig. 8A In FIG. 1 , the step structure SC exposed by the opening 105A extends continuously. The opening 105A extends in the direction D1 , and therefore, only the sidewalls sw1 and sw3 are shown.

[0182] Reference Fig. 8Aand Fig. 9B According to the above method, a liner 150, a stop layer 152 and a dielectric layer 107 are formed in the opening 105A, and after the liner 150, the stop layer 152 and the dielectric layer 107 on the hard mask layer HM are removed according to the above method, the hard mask layer HM is removed.

[0183] Reference Fig. 8A and Fig. 9B The liner 150 remaining in the opening 105A includes a plurality of portions 150a and 150b. The stop layer 152 remaining in the opening 105A includes a plurality of portions 152a and 152b. The portions 150a and 152a cover the surface of the step structure SC. The portions 150b and 152b cover the sidewalls sw1 and sw3 of the stack structure SK1 exposed in the opening 105A.

[0184] Reference Fig. 9C According to the above method, a charge storage structure 108, a channel column VC, a dielectric layer 115, a plurality of support columns (not shown), a dielectric layer 128 and a separation channel 116 are formed. Figure 8B and Fig. 9C , the separation channel 116 may include the separation channel 116 1 With 116 2 .

[0185] Next, refer to Figure 8C and Fig. 9C , a selective etching process is performed to separate the channel 116 1 With 116 2 The intermediate layer 104 and part of the stop layer 152 on both sides are removed to form the horizontal opening 121a as described above. Then, the conductive layer 126 is refilled in the horizontal opening 121a (shown in FIG. Fig.8D and Fig. 9C In this embodiment, when performing the selective etching process, the etchant can pass through the separation channels 116 on both sides. 1 With 116 2 The stop layer 152 contacts the stop layer 152, so the stop layer 152b on the sidewalls sw1 and sw3 of the opening 105A and the stop layer 152a on the bottom surface of the opening 105A contact the etchant and are removed, thereby forming a U-shaped tunnel 121b (shown in FIG. Fig. 9C ).

[0186] It is worth noting that in the above embodiments, referring to Figure 1B , the stop layer 152b on the side walls sw2 and sw4 will be left. The stop layer 152b covers the liner 150b on the side walls sw2 and sw4. Figure 8C , except for the sidewalls sw1 and sw3 of the opening 105A, the separation channel 1161 With 116 2 There is no stop layer 152b between the two sides, and the stop layer 152a on the bottom surface of the opening 105A is left. Similarly, the stop layer 152 in the peripheral region PRR only leaves the stop layer 152a on the bottom surface of the opening 105A. Fig.9E As described in the above embodiment, when the conductor layer 126 is formed, the conductor layer 126 is also formed in the U-shaped tunnel 121b. Thereafter, an etching process is performed to remove the conductor layer 126 in the U-shaped tunnel 121b and the separation channel 116, so that the U-shaped tunnel 121b and the separation channel 116 are exposed.

[0187] Reference Fig.9D and Fig.9E According to the method of the above embodiment, a stop layer 154 is formed in the U-shaped tunnel 121b. After that, the depth of the separation channel 116 is deepened, and the middle conductor layer 94 and the insulating layers 92 above and below the stop structure 103 are replaced by a conductor layer 93. The conductor layer 93 can form a common source line CSL with the conductor layer 94. The separation wall SLT is formed according to the method of the above embodiment. 1 With SLT 2 Next, a plurality of conductor plugs COA are formed to electrically connect the conductor layer 126 respectively. Fig.9E , forming a plurality of through-holes TV. In the first stage etching process of forming a plurality of conductor plugs COA and a plurality of conductor plug holes OP1 and a plurality of through-hole openings OP2 of a plurality of through-holes TV, the stop layers 154a and 152a can be used as etching stop layers. Since the stop layers 154a and 152a have sufficient thickness and have a sufficient etching selectivity with the dielectric layer 107, even if the thickness difference of the dielectric layer 107 in each region of the substrate 100 (the step region SCR and the peripheral region PRR) or each step of the step structure SC is quite large, the plurality of conductor plug holes OP1 and the through-hole openings OP2 with a considerable depth difference can still be effectively controlled to stop on the stop layer 154a and the stop layer 152a respectively, without etching through the conductor layer 126 or 93. Refer to Fig. 10A , Fig. 10B as well as Fig.9E By using the method of the embodiment of the present invention, a plurality of conductor plugs COA and a plurality of through holes TV with different depths can be formed.

[0188] Reference Fig.9E According to the method of the above embodiment, an interconnect structure 130 and a bonding structure 132 are formed on the substrate 100. Then, the bonding structure 132 is bonded to the bonding structure 32 of another chip 10W until a connection member 52 is formed on the conductive line 48. Thus, the memory element SM2 is formed.

[0189] Reference Fig.8D and Fig.9E In this embodiment, the opening 105A is different from Figure 1D and Figure 2R The opening 105 is shown. Figure 1D and Figure 2R The alternately stacked plurality of conductor layers 126 and the plurality of insulating layers 102 between two adjacent openings 105 are removed, thereby forming an opening 105A. Fig.8D and Fig.9E In this embodiment, the liner 150 and the stop layer 154 in the step region SCR remain at the bottom of the opening 105A as an etching stop layer, and the liner 150 and the stop layer 154 also remain on the sidewalls sw1 and sw3 of the opening 105A (as shown in FIG. Fig.8D The liner 150 and the stop layer 152 in the peripheral region PRR are left at the bottom of the opening 105A as an etching stop layer (as shown in FIG. Fig.9E shown).

[0190] Fig.11A and Fig. 11B A partial cross-sectional schematic diagram of a plurality of stop layers and liner layers according to an embodiment of the present invention is shown.

[0191] Reference Fig.11A and Fig. 11B In this embodiment, the stop layer 154, the liner 150 and the dielectric layer 107 are located in the opening 105A. The stop layer 154 is located between the liner 150 and the dielectric layer 107. Different from the above-mentioned embodiment, in this embodiment, there is no stop layer 152b located between the sidewall of the opening 105A and the sidewall of the dielectric layer 107, so the length L1' of the sub-portion F1 (or F2) of the stop layer 154a is longer. Similarly, the stop layer 154 can be a single layer or a multilayer. The material of the stop layer 154 may include an insulating layer, a conductor layer or a combination thereof. The insulating layer may include silicon nitride, a high dielectric constant material or a combination thereof. The conductor layer may include polysilicon, tungsten, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof.

[0192] Reference Fig.11A For example, the stop layer 154 may include the material layer 154 described in the above embodiment. 1 With 154 2 , and the material layer 154 2 There is an interface 154I. Fig. 11B For example, the stop layer 154 may include the material layer 154 described in the above embodiment. 1 , 154 2 With 154 3 . Material layer 154 3 There is an interface 154I.

[0193] Fig. 11C and Fig.11D A partial cross-sectional schematic diagram showing a conductor plug extending through a plurality of stop layers and liner layers according to an embodiment of the present invention.

[0194] Reference Fig. 11C and Fig.11D The conductor plug COA of the embodiment of the present invention is located at the partition wall SLT 1 With SLT 2 The conductor plug COA extends through the dielectric layer 107, the stop layer 154 and the liner 150, and lands on the conductor layer 126 of the stepped structure SC. The conductor plug COA may include a single layer or multiple layers. The conductor plug COA may include an insulating material, a conductive material or a combination thereof. The insulating material is, for example, silicon oxide, and the conductive material is, for example, polysilicon, tungsten, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof.

[0195] Reference Fig. 11C When the stop layer 154 is an insulating material, the conductor plug COA may be a conductor material 156, for example, including a barrier layer 1561 and a conductor filling layer 1562. The relative positions and materials of the barrier layer 1561 and the conductor filling layer 1562 are as described in the above embodiment.

[0196] Reference Fig. 11C , the stop layer 154 includes a conductor material (ie, the material layer 154 2 is a barrier layer, material layer 154 3 When the conductor plug COA is a conductor filling layer, the conductor plug COA may include a lining material 157 and a conductor material 156. The conductor material 156 may include a barrier layer 1561 and a conductor filling layer 1562. The relative positions and materials of the lining material 1563 and the conductor material 156 are as described in the above embodiment.

[0197] In the above embodiment, the stop layer 154 on the dielectric layer 128 and in the separation trench 116 is completely removed, however, the embodiment of the present invention is not limited thereto. The stop layer 154 may be thinned or not thinned and remain on the sidewall and bottom of the separation trench 116, or the stop layer 154 at the bottom of the separation trench 116 may be partially removed (not shown).

[0198] FIG. 12A to FIG. 12C It is a cross-sectional schematic diagram of a manufacturing process of stacked wafers according to an embodiment of the present invention.

[0199] The present invention can stack the above-mentioned multiple memory chips SM1, multiple memory chips SM2, or memory chips SM1 and memory chips SM2 into a stacked chip. For simplicity, multiple memory chips SM1 are stacked into a stacked chip 200W as an example for description.

[0200] Reference Fig. 12A The substrate 10 of the memory chip SM1 is thinned to expose the semiconductor through-holes (or silicon vias) 16. Then, a dielectric layer 51 and a connector 52' ​​connected to the semiconductor through-holes (or silicon vias) 16 are formed on the semiconductor through-holes (or silicon vias) 16 to form the memory chip SM1'.

[0201] Reference Fig. 12B , thereafter, the connector 52 of the memory chip SM1 is bonded to the connector 52' ​​of the memory chip SM1' to form a stacked chip 200W.

[0202] Reference Fig. 12C , providing a chip 300W. The chip 300W may be a logic chip. The chip 300W may have a substrate 300, a semiconductor through-hole (or silicon via) 316, a component layer 320, an internal connection structure 330, and a connector 352. The substrate 300, the semiconductor through-hole (or silicon via) 316, the component layer 320, the internal connection structure 330, and the connector 352 may be the same, similar, or different from the substrate 10, the semiconductor through-hole (or silicon via) 16, the component layer 20, the internal connection structure 30, and the connector 52 described above.

[0203] Reference Fig.12D , the stacked wafer 200W is bonded to the wafer 300W to form the stacked wafer 400W. Before the bonding process, the substrate 300 of the wafer 300W may be thinned to expose the semiconductor through-via (or silicon through-via) 316. Thereafter, a dielectric layer 351 and a connector 352' connected to the semiconductor through-via (or silicon through-via) 316 are formed on the semiconductor through-via (or silicon through-via) 316.

[0204] The stacked chip 200W can be bonded to the connector 352' of the chip 300W through the connector 52. Underfills 402 and 404 can be filled between the connectors 52 and 52' and between the connectors 52 and 352'. The stacked chip 200W can be covered with an encapsulation layer 406.

[0205] The stacked wafer 400W of the embodiment of the present invention includes two memory wafers SM1 and SM1' in the vertical direction. However, the embodiment of the present invention is not limited thereto. The stacked wafer 500W may include more memory wafers SM1 and SM1' in the vertical direction.

[0206] Fig.13 A cross-sectional schematic diagram of a packaging structure is shown.

[0207] Reference Fig.13The stacked chip 400W can be connected to a controller or directly to a host through semiconductor vias to provide wide channel width and high speed per channel, so it can be used as a high-bandwidth NAND flash memory.

[0208] The stacked wafer 400W may be bonded to the interposer 600 together with an application specific integrated circuit (ASIC) 500 to form a package structure 700. However, the application of the stacked wafer 400W is not limited thereto.

[0209] The above description is based on 3D NAND flash memory as an example, however, the present invention is not limited thereto and can also be applied to other 3D flash memories, such as 3D NOR flash memory.

[0210] The embodiments of the present invention can precisely control the formation of contact holes and perforation openings of different depths by setting a stop layer, so as to avoid the contact holes and perforation openings having different depths, which may cause some contact holes and perforation openings to fail to land on the word line or conductor layer of the correct step. Therefore, the embodiments of the present invention can prevent the conductor plug from failing to land on the word line and avoid abnormal short circuit of the conductor plug by setting a stop layer. Therefore, the embodiments of the present invention can improve the yield of the process.

Claims

1. A memory element, characterized in that: include: substrate; A stacking structure, located above the substrate, wherein the stacking structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening to expose a stepped structure of the stacking structure; a first stop layer covering the step structure and at least a portion of a plurality of side walls of the opening; a dielectric layer, filling the opening and covering the first stop layer; at least one partition wall extending through the dielectric layer and the first stop layer in the opening; as well as The conductor plug extends through the dielectric layer and the first stop layer and is electrically connected to the stepped structure.

2. The memory element according to claim 1, further comprising: A second stop layer covers the step structure and remaining portions of the plurality of sidewalls of the opening, wherein the remaining portions of the plurality of sidewalls are different from the at least a portion of the plurality of sidewalls of the opening. 3 . The memory device according to claim 1 , wherein the first stop layer is located at a bottom of the opening, and the first stop layer has an interface therein. The memory element according to claim 1 , wherein the first stop layer comprises an insulating filling layer. 5 . The memory element according to claim 1 , wherein the plurality of conductor layers have a first thickness, and the first stop layer located at the bottom of the opening has a second thickness, and the second thickness is more than twice the first thickness. 6 . The memory device according to claim 3 , wherein the bottom width of the at least one partition wall is such that the first stop layer located at the bottom of the opening has a second thickness, and the second thickness is smaller than the bottom width. 7 . The memory element according to claim 1 , wherein the first stop layer comprises a conductor filling layer, the conductor plug comprises a conductor material and a lining material surrounding a sidewall of the conductor material, the lining material separating the conductor material from the conductor filling layer.

8. A memory element, characterized in that: include: substrate; A stacking structure is located above the substrate, wherein the stacking structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately, and the stacking structure has an opening to expose the stepped structure of the stacking structure, wherein the opening includes: a first side wall; a second side wall connected to the first side wall; a third side wall connected to the second side wall, wherein the first side wall is opposite to the third side wall; a fourth side wall connected to the third side wall, wherein the second side wall is opposite to the fourth side wall; and A bottom portion connected to the first side wall, the second side wall, the third side wall and the fourth side wall; The first stop layer includes: A first part covering the stepped structure; and A second portion at least covers the first side wall and the third side wall; a dielectric layer, filling the opening and covering the first stop layer; At least one partition wall extends through the dielectric layer in the opening and the first portion and the second portion of the first stop layer; and A conductor plug extends through the dielectric layer and the first portion of the first stop layer and is electrically connected to the stepped structure. 9 . The memory device according to claim 8 , wherein the at least one partition wall extends along a direction and is parallel to the second sidewall and the fourth sidewall.

10. The memory element of claim 8, wherein the first portion of the first stop layer has an interface therein. 11 . The memory element according to claim 8 , wherein the first stop layer comprises a high dielectric constant material layer and an insulating filling layer covered by the high dielectric constant material layer. 12 . The memory element according to claim 8 , wherein the first stop layer comprises a conductor filling layer.

13. The memory element according to claim 8, further comprising: a first partition wall extending through the dielectric layer, the first portion of the first stop layer, and the stepped structure, and dividing the first portion of the first stop layer into a plurality of sub-portions; as well as A plurality of second partition walls extend through the stack structure, wherein the second portion of the first stop layer and the first partition wall are located between the plurality of second partition walls. 14 . The memory element according to claim 13 , wherein the first partition wall and the plurality of second partition walls include a material different from that of the first stop layer. 15 . The memory device according to claim 13 , further comprising a second stop layer covering the second sidewall and the fourth sidewall. 16 . The memory element according to claim 15 , wherein the first partition wall and the plurality of second partition walls include a material different from that of the second stop layer.

17. The memory element according to claim 13, wherein at least one partition wall comprises a first partition wall and a second partition wall, the first partition wall and the second partition wall are separated by a first distance, the multiple sub-portions of the first portion of the first stop layer are located between the first partition wall and the second partition wall, and the length of the sub-portion is greater than half of the first distance.

18. The memory device according to claim 13, wherein the first partition wall is electrically insulated from the second partition wall.

19. The memory device according to claim 8, wherein a thickness of the first portion of the first stop layer is smaller than a bottom width of the at least one separation wall. 20 . The memory element of claim 8 , wherein the plurality of conductor layers have a first thickness, the first portion of the first stop layer has a second thickness, and the second thickness is greater than twice the first thickness.

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