Three-dimensional memory structure

Abstract

The invention provides a three-dimensional storage structure. The three-dimensional storage structure comprises a substrate which comprises a first functional area; the first conductive structure is arranged on the substrate, is electrically connected with the first functional area and is used for realizing the use function of the three-dimensional storage structure; the first vertical interconnection channel is arranged on the first conductive structure in an electric connection manner; and a second vertical interconnection channel having the same potential as the first vertical interconnection channel in the electrochemical reaction.

Description

[0001] This application is a divisional application for a patent with an application date of September 6, 2021, application number 202111046537.8, and invention name “Three-dimensional storage structure”. Technical Field

[0002] The present application relates to the field of semiconductors, and more specifically, to a three-dimensional storage structure. Background Art

[0003] People are pursuing memories with larger storage capacity and higher storage density, so three-dimensional memories have been developed. Three-dimensional memories usually include a three-dimensional storage structure (stacked storage cells) and peripheral circuits for controlling the storage cells. In order to further increase the proportion of storage cells and reduce the proportion of peripheral circuits, X-stacking technology can be used to bond the peripheral circuits to the stacked storage cells.

[0004] In X-stacking technology, the upper wafer including the peripheral circuit and the lower wafer including the three-dimensional storage structure need to be bonded together. The top layer of the three-dimensional storage structure includes vertical interconnection channels (VIAs), and the bottom layer of the peripheral circuit also includes vertical interconnection channels. Then the three-dimensional storage structure and the peripheral circuit are electrically connected through the bonding between the vertical interconnection channels. Therefore, the performance of the VIA is very important.

[0005] In a three-dimensional storage structure, a vertical interconnect channel may be connected to a substrate through a conductive structure. For example, a first vertical conductive channel may be electrically connected to a P-well region through a conductive structure, and a second vertical interconnect channel may be electrically connected to an N-well region through another conductive structure. A virtual vertical interconnect channel may be in a floating state that is not electrically connected to other structures. Since many VIAs in some areas may be in different environments, when the three-dimensional storage structure is subjected to mechanical chemical polishing, plasma treatment during bonding, cleaning with deionized water, etc., some VIAs have a lower potential and are then corroded as negative electrodes during the electrochemical reaction process. For example, the first vertical interconnect channel may be electrochemically corroded.

[0006] refer to Figure 1 The corroded VIA may lose more conductive materials to form holes, and the corroded conductive materials or external substances contacted by the three-dimensional storage structure may be deposited in other locations. Such three-dimensional storage may have problems such as abnormal bonding, defective products, or reliability of use. Summary of the invention

[0007] An embodiment of the present application provides a three-dimensional storage structure, which includes: a substrate, including a first functional area and a protection area, the conductive property of the first functional area is the same as the conductive property of the protection area; a first conductive path, arranged on the substrate and its top surface is exposed to the surface of the three-dimensional storage structure, the first conductive path is electrically connected to the first functional area; and a second conductive path, arranged on the substrate and its top surface is exposed to the surface of the three-dimensional storage structure, the second conductive path is electrically connected to the protection area.

[0008] In one embodiment, the first conductive path includes: a first conductive structure, which is disposed on the substrate; a first vertical interconnection channel, which is disposed on the first conductive structure and electrically connected to the first functional area through the first conductive structure; the second conductive path includes: a second conductive structure, which is disposed on the substrate; and a second vertical interconnection channel, which is disposed on the second conductive structure and electrically connected to the protection area through the second conductive structure; wherein a plurality of the second vertical interconnection channels are arranged to surround a plurality of the first vertical interconnection channels.

[0009] In one embodiment, the first conductive structure includes: a first conductive channel, a lower contact, a lower interconnect, an upper contact and an upper interconnect arranged in sequence in a direction away from the substrate; and wherein at least two of the first vertical interconnect channels are electrically connected to the same upper interconnect of the first interconnect structure.

[0010] In one embodiment, the substrate also includes a second functional area, and the electrical properties of the second functional area are different from the electrical properties of the first functional area; the three-dimensional storage structure also includes: a third conductive structure, arranged on the substrate and electrically connected to the second functional area; and a third vertical interconnection channel, arranged on the third conductive structure and electrically connected to the third conductive structure, wherein the plurality of second vertical interconnection channels are located between the plurality of first vertical interconnection channels and the third vertical interconnection channels.

[0011] In one embodiment, the diameter of the top surface of the first vertical interconnect channel is between 500 nm and 2000 nm.

[0012] In one embodiment, the material of the first vertical interconnect channel includes copper.

[0013] In one embodiment, the first functional region includes a P-well region; and the first conductive structure is electrically connected to the P-well region.

[0014] In one embodiment, the three-dimensional storage structure further includes: a through silicon contact disposed between the first vertical interconnection channel and the first conductive structure and electrically connected to the first vertical interconnection channel and the first conductive structure respectively.

[0015] The three-dimensional storage structure provided in the embodiment of the present application is provided with a second vertical interconnection channel similar to the first vertical interconnection channel. In fact, the overall top surface area of ​​the two vertical interconnection channels is larger than the top surface area of ​​the first vertical interconnection channel, and the second vertical interconnection channel can be arranged closer to the outside in terms of the arrangement position. The corrosion amount of the electrochemical reaction is shared by the second vertical interconnection channel to ensure the reliability of the first vertical interconnection channel used to realize the preset function of the three-dimensional storage structure.

[0016] In addition, by increasing the overall top surface area of ​​at least one first vertical interconnection channel electrically connected to the same conductive structure, specifically by increasing the proportion of the overall top surface of at least one first vertical interconnection channel electrically connected to the same conductive structure to the first region, at least the remaining portion of the first vertical interconnection channel after electrochemical corrosion occurs is increased. In particular, a large number of large-sized pits are avoided in the first vertical interconnection channel, thereby ensuring the stability of bonding and ensuring electrical connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0018] Figure 1 is a top view of a three-dimensional storage structure of the background art;

[0019] Figure 2 is an adaptable top view of a three-dimensional storage structure according to a comparative example of the present application;

[0020] Figure 3 is a schematic top view of a three-dimensional storage structure according to an embodiment of the present application;

[0021] Figure 4 yes Figure 3 A schematic cross-sectional view at AA in the middle;

[0022] Figure 5 is a schematic structural diagram of a three-dimensional storage structure according to another embodiment of the present application;

[0023] Figure 6 is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of the present application;

[0024] Figure 7 is a schematic top view of a three-dimensional storage structure according to an embodiment of the present application;

[0025] Figure 8 is a schematic structural diagram of a three-dimensional storage structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the feature. Therefore, without departing from the teaching of the present application, the first vertical interconnection channel discussed below may also be referred to as the second vertical interconnection channel. And vice versa.

[0028] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not strictly drawn to scale. For example, the diameter of the top surface of the first vertical interconnection channel is not in proportion to the diameter of the third vertical interconnection channel in actual production. As used herein, the terms "substantially", "approximately" and similar terms are used as terms of approximation, not as terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values ​​that will be recognized by a person of ordinary skill in the art.

[0029] It should also be understood that the terms "comprises", "including", "having", "includes" and / or "comprising", when used in this specification, indicate the presence of the stated features, elements and / or components, but do not exclude the presence or addition of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0030] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0032] refer to Figure 2 , which shows the three-dimensional storage structure of the comparative example of the present application. Further, Figure 2 The structural diagram shown can be a top view of the memory chip or a bottom view of the peripheral circuit chip. Exemplarily, the three-dimensional memory structure includes a plurality of first vertical interconnection channels 41 of the array, and third vertical interconnection channels 42 and virtual vertical interconnection channels 43 located outside the first vertical interconnection channels 41. In some cases, the third vertical interconnection channels 42 and the virtual vertical interconnection channels 43 have a higher potential in the electrochemical reaction than the first vertical interconnection channels 41.

[0033] Taking a memory chip as an example, the first vertical interconnection channel 41 can be electrically connected to a substrate (not shown) through a conductive structure (not shown) on its back, for example, to a P-well region of the substrate. Since the conductive structure can be in a deflected form in a direction parallel to the substrate, a first vertical interconnection channel 41 and the P-well region to which it is electrically connected do not necessarily coincide in the projection direction. For example, in this comparative example, the first vertical interconnection channel 41 is electrically connected to the P-well region in a one-to-one correspondence. Figure 3 As shown, on the top surface of the chip, a first vertical interconnection channel 41 occupies a first area a1 that does not interfere with adjacent structural areas. Since a plurality of first vertical interconnection channels 41 are usually arranged adjacent to each other, the first vertical interconnection channels 41 may occupy a low potential area A as a whole.

[0034] In this comparative example, the diameter of the top surface of the first vertical interconnection channel 41 is about 200 nm. Further, the ratio of the area of ​​the first vertical interconnection channel 41 to the area of ​​the first region a1 where it is located can be less than or equal to 20%. The memory chip of this comparative example can be bonded to a peripheral circuit chip, and the first vertical interconnection channel 41 is bonded to the vertical interconnection channel of the peripheral circuit chip. When some of the first vertical interconnection channels 41 are etched with pits, the bonding area of ​​these first vertical interconnection channels 41 is small and the resistance is large.

[0035] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0036] refer to Figure 3 and 4The present application provides a three-dimensional storage structure, including: a substrate 1, a channel structure (not shown), a first conductive path 21 and a second conductive path 22. Exemplarily, the conductive paths 21-22 are arranged on the corresponding at least one channel structure. Exemplarily, the first conductive path 21 may include a first conductive channel 211, a lower contact 212, a lower interconnect 213, an upper contact 214, an upper interconnect 215, a first through-silicon contact 31 and a first vertical interconnect channel 41 in a direction away from the substrate 1. The first conductive channel 211 to the upper interconnect 215 are used to form a first conductive structure 210. The second conductive path 22 at least includes a second conductive structure 220, a second through-silicon contact 32 and a second vertical interconnect channel 44 arranged in a direction away from the substrate 1.

[0037] The substrate 1 includes a first functional area 11 and a protection area 13 having the same conductive properties. In some embodiments, the channel structure provided on the substrate is electrically connected to the first functional area 11 and can be electrically isolated from the protection area 13. In other embodiments, the area of ​​the first functional area can be increased compared to the existing area, and then the extra part compared to the existing first functional area is the protection area, so that the second conductive path is electrically connected to the first functional area. However, the second conductive path is usually not used to realize the use function of the three-dimensional memory.

[0038] The first conductive structure 210 and the second conductive structure 220 are also disposed on the substrate, and are electrically connected to the first functional area 11 and the protection area 13, respectively. Furthermore, the first vertical interconnection channel 41 disposed on the first conductive structure 210 is electrically connected to the first functional area 11 through the first conductive structure 210. The first vertical interconnection channel 41 is used to exert the function of the three-dimensional storage structure. The second vertical interconnection channel 44 disposed on the second conductive structure 23 is electrically connected to the protection area 13 through the second conductive structure 23. The second vertical interconnection channel 44 may not be used to realize the preset function of the three-dimensional storage structure, but has similar characteristics to the first vertical interconnection channel 41 in the electrochemical reaction.

[0039] In the three-dimensional storage structure provided by the present application, the plurality of second vertical interconnection channels 44 are arranged on one side of the first vertical interconnection channel 41. Further, the plurality of second vertical interconnection channels 44 are configured to surround the first vertical interconnection channel 41.

[0040] refer to Figure 3 , the plurality of first vertical interconnection channels 41 corresponding to the plurality of first functional areas 11 may occupy the low potential area A. Exemplarily, the sum of the top surface area of ​​the first vertical interconnection channels 41 as a whole and the top surface area of ​​the second vertical interconnection channels 44 located outside the low potential area A is greater than 25% of the area of ​​the low potential area A.

[0041] The second vertical interconnection channel 44 can serve as an adjacent structure of the first vertical interconnection channel 41, and the second vertical interconnection channel 44 can occupy the second area b1. The second area c1 does not interfere with the first area a1, and specifically, the boundary between the two can be located at the midpoint of the first vertical interconnection channel 41 and the second vertical interconnection channel 44. Exemplarily, when the areas of the first vertical interconnection channel 41 and the second vertical interconnection channel 44 are different in size, the midpoint between the center of the first vertical interconnection channel 41 and the center of the second vertical interconnection channel 44 can be used as the boundary of the two areas a1 / b1, and at this time, the area of ​​the first vertical interconnection channel 41 accounts for a larger proportion. In other embodiments, if the midpoint of the interval between the first vertical interconnection channel 41 and the second vertical interconnection channel 44 is used as the boundary of the two areas a1 / b1, the area of ​​the first vertical interconnection channel 41 can also generally account for more than 25%.

[0042] In an exemplary embodiment, a plurality of second regions b1 are arranged to surround the first region a1. Specifically, the protective transition region B formed by the plurality of second regions b1 can completely surround the low potential region A formed by the plurality of first regions a1. During an electrochemical reaction, current is generated in different electrical regions and critical points and the metal near the boundary is etched first. The plurality of second vertical interconnection channels 44 are arranged outside the first vertical interconnection channel 41, so that the first vertical interconnection channel 41 can be completely protected. The second vertical interconnection channel 44 is more likely to withstand electrochemical corrosion, thereby better protecting the first vertical interconnection channel 41.

[0043] The three-dimensional storage structure provided in this embodiment protects the first vertical interconnection channel 41 by providing the second vertical interconnection channel 44, so that the three-dimensional storage structure has better reliability and better working performance.

[0044] In an exemplary embodiment, reference Figure 5 The substrate 1 further includes a second functional region 12, and the electrical properties of the second functional region 12 are different from those of the first functional region 11. Exemplarily, the second functional region 12 may be an N-well region.

[0045] The three-dimensional storage structure also includes a third conductive channel 23 electrically connected to the second functional area 12. The third conductive channel 23 may include a third conductive structure 230 and a third vertical interconnection channel 42. The third conductive structure is disposed on the substrate 1 and is electrically connected to the second functional area 12. The third vertical interconnection channel 42 is electrically connected to the second functional area 12 through the third conductive structure 230. Since the electrical properties of the second functional area 12 are different from those of the first functional area 11, the performance of the third vertical interconnection channel 42 in the electrochemical reaction may be different from that of the first vertical interconnection channel 41. In this embodiment, at least one second vertical interconnection channel 44 may be disposed between the first vertical interconnection channel 41 and the third vertical interconnection channel 42.

[0046] Further, each third vertical interconnection channel may occupy a third region on the surface of the three-dimensional storage structure. The third region does not interfere with the region occupied by the adjacent structure, such as the second region. In this embodiment, the third region may not be adjacent to the first region.

[0047] In some embodiments, structures such as virtual vertical interconnection channels may be provided outside the protection transition region B.

[0048] In an exemplary embodiment, the material of the first vertical interconnection channel 41 includes copper. Further, the material of each of the vertical interconnection channels 41 to 44 may include copper.

[0049] Exemplarily, the first functional area may not be a P-well area. According to the existing three-dimensional storage structure or the three-dimensional storage structure of the comparative example, different functional areas of the substrate may correspond to different areas of the top surface of the three-dimensional storage structure. Under complex manufacturing conditions, the vertical interconnection channels in some areas are more susceptible to corrosion. Then, the portion of the substrate electrically connected to these vertical interconnection channels can be regarded as the first functional area, and the conductive channel where these vertical interconnection channels are located is the first conductive channel.

[0050] refer to Figure 5 In an exemplary embodiment, the three-dimensional storage structure further includes a second conductive path 22 and a channel structure (not shown). Meanwhile, the substrate 1 further includes a protection zone 13. The second conductive path 22 may include a second conductive structure 220 and a second vertical interconnection channel 44.

[0051] The channel structure is arranged on the substrate 1, and the first functional area 11 is electrically connected to the channel structure through other structures of the substrate 1, so that the first vertical interconnection channel 41 cooperates with the channel structure to realize the preset function of the three-dimensional storage structure. The protection area 13 has the same structure or material as the first functional area 11, for example, it can also be a P-well area, or other structures. However, the protection area 13 is not electrically connected to the channel structure used to realize the function in the substrate 1.

[0052] The second vertical interconnection channel 44 is disposed on the second conductive structure 230 and electrically connected to the protection zone 13 through the second conductive structure 230. In an exemplary embodiment, the three-dimensional storage structure further includes a second through silicon contact 32 electrically connected between the second vertical interconnection channel 44 and the second conductive structure 23.

[0053] Since the protection area 13 and the first functional area 11 have the same characteristics, the second vertical interconnection channel 44 and the first vertical interconnection channel 41 have similar characteristics during the electrochemical reaction process. The corrosion of the first vertical interconnection channel 41 is shared by the second vertical interconnection channel 44, so that the first vertical interconnection channel 41 maintains a good shape.

[0054] Figure 6 It is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of the present application. Figure 7 is a top view of a three-dimensional storage structure according to an embodiment of the present application. Figure 6 and Figure 7 The three-dimensional storage structure provided in the embodiment of the present application includes: a substrate 1 and at least one first conductive path 21 disposed on the substrate 1. The first conductive path 21 may include a first conductive structure 210 and at least one first vertical interconnection channel 41. Specifically, the three-dimensional storage structure includes a memory chip or a peripheral circuit chip, and the first vertical interconnection channel 41 is used to bond with a vertical interconnection channel of an opposite chip.

[0055] The substrate 1 may include at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Various circuit structures are provided on the body (not shown) of the substrate 1, including a first functional area 11. The first functional area 11 may be a P-well area, which is used to form a circuit located in the substrate 1. Exemplarily, a stacking structure and a channel structure (not shown) that penetrates the stacking structure and extends into the substrate 1 are provided on the substrate 1. The first functional area 11 can be used to form a CMOS electrically connected to the channel structure or to be electrically connected to the channel structure, and the first functional area 11 can also be used to realize other preset functions of the three-dimensional storage structure.

[0056] The first conductive structure 210 is disposed on the substrate 1 and is electrically connected to the first functional region 11. In an exemplary embodiment, the first conductive structure 210 includes: a first conductive channel 211, a lower layer contact 212, a lower layer interconnection 213, an upper layer contact 214, and an upper layer interconnection 215, which are sequentially disposed in a direction away from the substrate 1. Specifically, an interconnection structure layer may be disposed on the stacking structure, and then the first conductive channel 211 may penetrate the stacking structure, while the lower layer contact 212, the lower layer interconnection 213, the upper layer contact 214, and the upper layer interconnection 215 are located in the interconnection structure layer. In the interconnection structure layer, the lower layer interconnection 213 and the upper layer interconnection 215 may extend in a direction parallel to the substrate 1, so that the top of the upper layer interconnection 215, which can be used as an electrical connection area, may be misaligned with the first functional region 11 in a direction parallel to the substrate 1.

[0057] In an exemplary embodiment, the three-dimensional storage structure further includes a first through silicon contact 31 (TSC). The first through silicon contact 31 is disposed between the first vertical interconnection channel 41 and the first conductive structure 210, and is electrically connected to the first vertical interconnection channel 41 and the first conductive structure 210, respectively. Specifically, the first through silicon contact 31 is disposed on the upper interconnection structure 215. Exemplarily, the ratio of the diameter of the top surface of the first vertical interconnection channel 41 to the diameter of the first through silicon contact 31 is greater than 3. In an exemplary embodiment, the diameter of the first vertical interconnection channel 41 is greater than 500nm. Exemplarily, the diameter of the first vertical interconnection channel 41 is less than 2000nm or less than 1000nm.

[0058] The first vertical interconnection channel 41 is disposed on the first conductive structure 210 and is electrically connected to the first conductive structure 210. Exemplarily, one first conductive structure 210 is electrically connected to at least one first vertical interconnection channel 41.

[0059] In an exemplary embodiment, reference Figure 7 , the first area a1 occupied by the first vertical interconnection channel 41 may be roughly rectangular. Multiple first vertical interconnection channels 41 may be roughly in a rectangular array. Exemplarily, the top of the three-dimensional storage structure also includes a third vertical interconnection channel 42. The material of the third vertical interconnection channel 42 may be the same as that of the first vertical interconnection channel 41, but it does not corrode during electrochemical reactions or the corrosion rate is lower than that of the first vertical interconnection channel 41. The role of the third vertical interconnection channel 42 in the three-dimensional storage structure is different from that of the first vertical interconnection channel 41, and it can be electrically connected to, for example, an N-well region. Each third vertical interconnection channel 42 may also occupy a second area b1.

[0060] For a first vertical interconnection channel 41, its adjacent structure may be another first vertical interconnection channel 41, or a third vertical interconnection channel 42, or some other structures. For a first area a1, its adjacent structure area may be another first area a1, or a second area b1, or an area occupied by other structures. In the three-dimensional storage structure, at least one vertical interconnection channel at the top electrically connected to each conductive structure 210 may occupy a corresponding area, which is not necessarily in the same projection position as the conductive structure, for example, it may be misaligned.

[0061] For example, the midpoint between two adjacent vertical interconnection channels 41 / 42 can be used as the boundary position of the area a1 / b1 occupied by the two, for example, the midpoint between two adjacent first vertical interconnection channels 41 can be used as the position of a partial boundary of the first area a1. Each area a1 / b1 can be bounded by its adjacent area. The ratio of the top surface area of ​​at least one first vertical interconnection channel 41 electrically connected to a first conductive structure 210 to the area of ​​the first area a1 is not less than 25%.

[0062] When the structure of the substrate 1 electrically connected to the first conductive structure 210, specifically the first functional area 11 such as the P-well area, remains unchanged, the location of the first vertical interconnection channel 41 and the first area a1 occupied by the first vertical interconnection channel 41 can be designed to be different locations or designed to have different forms. For example, when a plurality of first vertical interconnection channels 41 are arranged in a honeycomb shape, the first area a1 occupied by each first vertical interconnection channel 41 that does not interfere with the adjacent structural area can be a hexagon.

[0063] The first regions a1 of the first vertical interconnection channels 41 may also be formed as a low potential region A. The high potential vertical interconnection channels 42 are located outside the low potential region A. The ratio of the overall top surface area of ​​the at least two first vertical interconnection channels 41 electrically connected to the at least two first conductive structures 210 to the area of ​​the low potential region A may also be not less than 25%, for example, the area ratio is 35%.

[0064] The top surface of the three-dimensional storage structure provided in the embodiment of the present application is used to be combined with another chip, and the three-dimensional storage structure is electrically connected to the chip through at least a first vertical interconnection channel to achieve a preset function. By increasing the area of ​​at least one first vertical interconnection channel electrically connected to a first functional area exposed to the top surface of the three-dimensional storage structure, for example, making the ratio of the area to the area of ​​the first region occupied by these first vertical interconnection channels not less than 25%, these first vertical interconnection channels have a larger window during the electrochemical reaction to overcome the pits caused by material loss. Then, when the three-dimensional storage structure is combined with another chip, it can ensure that the corresponding pair of vertical interconnection channels (including the first vertical interconnection channel) are electrically connected.

[0065] refer to Figure 8 , which exemplarily shows a three-dimensional storage structure according to an embodiment of the present application. The three-dimensional storage structure includes: a substrate 1 and at least one first conductive path 21 disposed on the substrate 1. The first conductive path 21 may include a first conductive structure 210 and at least two first vertical interconnection channels 41.

[0066] The substrate 1 may include a body (not shown) and a first functional region 11. The first functional region 11 may be a P-well region. The first conductive structure 210 includes a first conductive channel 211, a lower contact 212, a lower interconnect 213, an upper contact 214, and an upper interconnect 215, which are sequentially arranged in a direction away from the substrate 1. Among them, the upper interconnect 215 extends a certain length in a direction parallel to the substrate 1, so that at least two first vertical interconnect channels 41 are electrically connected to the upper interconnect 215. Exemplarily, each first vertical interconnect channel 41 is electrically connected to the upper interconnect 215 through a first through silicon contact 31.

[0067] For example, a portion of at least two first vertical interconnection channels 41 is used to realize the use function of the three-dimensional storage structure, and the other portion may be vacant in the circuit. The vacant first vertical interconnection channels may be arranged outside the first vertical interconnection channels actually used.

[0068] Exemplarily, the first functional area 11 is electrically connected to at least two first vertical interconnection channels 41 through the first conductive structure 210, and these first vertical interconnection channels 41 occupy a first area. Exemplarily, the area ratio of each first vertical interconnection channel 41 to the first area may be no greater than 20%, and the area ratio of the top surface area of ​​the two first vertical interconnection channels 41 as a whole to the area of ​​the first area is greater than or equal to 25%, for example, 30%. In other embodiments, one of the two first vertical interconnection channels 41 may also occupy 20% or even more than 25% of the area of ​​the first area.

[0069] The three-dimensional storage structure provided in this embodiment can add at least one other first vertical interconnection channel electrically connected to the same upper interconnection in addition to the existing first vertical interconnection channel. By sharing the corrosion during the electrochemical reaction through the additional first vertical interconnection channel, it can be ensured that when the three-dimensional storage structure is connected to other chips, the first conductive structure can be well electrically connected to the chip, and then the P-well region (first functional region) can well realize the preset function. By arranging these vacant first vertical interconnection channels on the outside, these vacant first vertical interconnection channels can be better sacrificed. Furthermore, the reliability of the three-dimensional storage structure can be further improved by controlling the area ratio of at least two first vertical interconnection channels corresponding to the first functional region to the first region.

[0070] In an exemplary embodiment, the substrate further includes a second functional area having electrical properties different from those of the first functional area. The three-dimensional storage structure further includes: a third conductive structure disposed on the substrate and a third vertical interconnection channel disposed on the third conductive structure. Exemplarily, a third through-silicon contact electrically connected to the third vertical interconnection channel and the third conductive structure may also be disposed between the third vertical interconnection channel and the third conductive structure. Specifically, the second area is located between the first area and the third area occupied by the third vertical interconnection channel.

[0071] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions in the present application.

Claims

1. A three-dimensional storage structure, characterized in that: include: A substrate, comprising a first functional region and a protection region, wherein the protection region at least partially surrounds the first functional region in a direction parallel to the substrate; A stacking structure is arranged on the substrate; a channel structure, penetrating the stacked structure and connected to the first functional area, the channel structure being isolated from the protection area; A first conductive structure, disposed on the substrate and connected to the first functional area; A first vertical interconnection channel, disposed on a side of the first conductive structure away from the substrate and connected to the first conductive structure; as well as A second vertical interconnection channel is located on the substrate and connected to the protection zone, wherein the second vertical interconnection channel and the first vertical interconnection channel at least partially include the same conductive material.

2. The three-dimensional storage structure according to claim 1, characterized in that: The three-dimensional storage structure further includes: a second conductive structure disposed on the substrate and connected to the protection zone; and The second vertical interconnection channel is disposed on a side of the second conductive structure facing away from the substrate and is connected to the second conductive structure.

3. The three-dimensional storage structure according to claim 1 or 2, characterized in that: The plurality of the second vertical interconnection channels are arranged to surround the plurality of the first vertical interconnection channels.

4. The three-dimensional storage structure according to claim 3, characterized in that: The first conductive structure includes: a first conductive channel, a lower contact, a lower interconnect, an upper contact and an upper interconnect arranged in sequence in a direction away from the substrate, wherein at least two of the first vertical interconnect channels are connected to the upper interconnect of the same first conductive structure.

5. The three-dimensional storage structure according to claim 2, characterized in that: The substrate further includes a second functional region, the electrical properties of the second functional region being different from those of the first functional region; The three-dimensional storage structure also includes: A third conductive structure, disposed on the substrate and connected to the second functional area; and A third vertical interconnection channel is disposed on the third conductive structure and connected to the third conductive structure, wherein the second vertical interconnection channel is located between the first vertical interconnection channel and the third vertical interconnection channel.

6. The three-dimensional storage structure according to claim 1, characterized in that: The diameter of the top surface of the first vertical interconnect channel is between 500 nm and 2000 nm.

7. The three-dimensional storage structure according to claim 1, characterized in that: The second vertical interconnect channel has the same potential as the first vertical interconnect channel in an electrochemical reaction.

8. The three-dimensional storage structure according to claim 1, characterized in that: The conductive material includes copper.

9. The three-dimensional storage structure according to claim 1, characterized in that: The conductivity of the first functional area is the same as that of the protection area.

10. The three-dimensional storage structure according to claim 1, characterized in that: The first functional region includes a P-well region; The first conductive structure is connected to the P-well region.

11. The three-dimensional storage structure according to claim 1, characterized in that: Also includes: A through silicon contact is disposed between the first vertical interconnect channel and the first conductive structure and is connected to the first vertical interconnect channel and the first conductive structure respectively.

12. The three-dimensional storage structure according to claim 11, characterized in that: A ratio of a diameter of a top surface of the first vertical interconnect channel to a diameter of the through-silicon contact is greater than 3.

13. A three-dimensional storage structure, characterized in that: include: A substrate including a first functional region; A stacking structure is arranged on the substrate; a channel structure, penetrating the stacked structure and connected to the first functional area; A first conductive structure, disposed on the substrate and connected to the first functional area, the first conductive structure comprising an upper layer interconnection away from a side of the substrate; as well as First vertical interconnection channels, at least two of the first vertical interconnection channels are connected to the upper interconnection of the same first conductive structure.

14. The three-dimensional storage structure according to claim 13, characterized in that: At least one of the at least two first vertical interconnection channels is used to implement a preset function of three-dimensional storage, and at least another of the at least two first vertical interconnection channels is vacant in the circuit.

15. The three-dimensional storage structure according to claim 13, characterized in that: The first conductive structure further comprises: a first conductive channel, a lower layer contact, a lower layer interconnection and an upper layer contact arranged in sequence in a direction away from the substrate, wherein the upper layer interconnection is located on a side of the upper layer contact away from the substrate and connected to the upper layer contact; The upper layer interconnection extends in a direction parallel to the substrate and includes two ends in the direction parallel to the substrate, the upper layer contact and at least one of the at least two first vertical interconnection channels are connected to the same end of the two ends, and at least another one of the at least two first vertical interconnection channels is connected to the other end of the two ends.

16. The three-dimensional storage structure according to any one of claims 13 to 15, characterized in that: In a direction parallel to the substrate, a size of the upper interconnect is larger than a size of the first vertical interconnect channel.

17. The three-dimensional storage structure according to claim 13, characterized in that: The first functional region includes a P-well region; The first conductive structure is connected to the P-well region.

18. The three-dimensional storage structure according to claim 13, characterized in that: Also includes: A through silicon contact is disposed between the first vertical interconnection channel and the upper interconnection and is connected to the first vertical interconnection channel and the upper interconnection respectively.

19. The three-dimensional storage structure according to claim 13, characterized in that: The material of the first vertical interconnect channel includes copper.

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