Three-dimensional storage structure

Abstract

The application provides a three-dimensional storage structure. The three-dimensional storage structure comprises: a substrate comprising a first functional area; a first conductive structure disposed on the substrate and electrically connected to the first functional area, used to realize a use function of the three-dimensional storage structure; a first vertical interconnection channel disposed on the first conductive structure in an electrically connected manner; and a second vertical interconnection channel having the same potential as the first vertical interconnection channel in an electrochemical reaction.

Description

[0001] This application is a divisional application of the patent filed on September 6, 2021, with application number 202111046537.8, entitled "Three-dimensional storage structure". Technical Field

[0002] This application relates to the semiconductor field, and more specifically, to a three-dimensional storage structure. Background Technology

[0003] The pursuit of larger storage capacity and higher storage density has led to the development of 3D memory. 3D memory typically comprises a three-dimensional storage structure (stacked memory cells) and peripheral circuitry for controlling the memory cells. To further increase the proportion of memory cells and reduce the proportion of peripheral circuitry, X-stacking technology can be used to bond the peripheral circuitry onto the stacked memory cells.

[0004] In X-stacking technology, an upper wafer containing peripheral circuitry and a lower wafer containing the three-dimensional memory structure need to be bonded together. The top layer of the three-dimensional memory structure includes vertical interconnect channels (VIAs), and the bottom layer of the peripheral circuitry also includes VIAs. The three-dimensional memory structure and the peripheral circuitry are then electrically connected through bonding between the VIAs. Therefore, the performance of the VIAs is crucial.

[0005] In a three-dimensional memory structure, vertical interconnect channels (VIAs) can be connected to the substrate via conductive structures. For example, a first vertical conductive channel can be electrically connected to a P-well region via one conductive structure, and a second vertical interconnect channel can be electrically connected to an N-well region via another conductive structure. Virtual vertical interconnect channels can be in a floating state without being electrically connected to other structures. Because many VIAs in some regions can be in different environments, some VIAs may have lower potentials during processes such as mechanochemical polishing, plasma treatment during bonding, and cleaning with deionized water, and thus act as negative electrodes and be corroded during the electrochemical reaction. For example, the first vertical interconnect channel may be electrochemically corroded.

[0006] refer to Figure 1 Corroded VIAs may lose significant amounts of conductive material, forming pits, and the corroded conductive material or external substances in contact with the 3D memory structure may deposit in other locations. Such 3D memory may experience problems such as abnormal bonding connections, product defects, or unreliable performance. Summary of the Invention

[0007] Embodiments of this application provide a three-dimensional storage structure, comprising: a substrate including a first functional region and a protected region, wherein the conductivity of the first functional region and the conductivity of the protected region are the same; a first conductive path disposed on the substrate with its top surface exposed to the surface of the three-dimensional storage structure, wherein the first conductive path is electrically connected to the first functional region; and a second conductive path disposed on the substrate with its top surface exposed to the surface of the three-dimensional storage structure, wherein the second conductive path is electrically connected to the protected region.

[0008] In one embodiment, the first conductive path includes: a first conductive structure disposed on the substrate; a first vertical interconnect channel disposed on the first conductive structure and electrically connected to the first functional region through the first conductive structure; the second conductive path includes: a second conductive structure disposed on the substrate; and a second vertical interconnect channel disposed on the second conductive structure and electrically connected to the protected area through the second conductive structure; wherein, a plurality of second vertical interconnect channels are configured to surround a plurality of first vertical interconnect channels.

[0009] In one embodiment, the first conductive structure includes: a first conductive channel, a lower contact, a lower interconnect, an upper contact, and an upper interconnect arranged sequentially in a direction away from the substrate; and wherein at least two of the first vertical interconnect channels are electrically connected to the upper interconnect of the same first interconnect structure.

[0010] In one embodiment, the substrate further includes a second functional region, the electrical properties of which differ from those of the first functional region; the three-dimensional storage structure further includes: a third conductive structure disposed on the substrate and electrically connected to the second functional region; and a third vertical interconnect channel disposed on the third conductive structure and electrically connected to the third conductive structure, wherein the plurality of second vertical interconnect channels are located between the plurality of first vertical interconnect channels and the third vertical interconnect channel.

[0011] In one embodiment, the diameter of the top surface of the first vertical interconnect channel is between 500 nm and 2000 nm.

[0012] In one embodiment, the material of the first vertical interconnect channel includes copper.

[0013] In one embodiment, the first functional region includes a P-well region; the first conductive structure is electrically connected to the P-well region.

[0014] In one embodiment, the three-dimensional storage structure further includes: a through-silicon contact disposed between the first vertical interconnect channel and the first conductive structure, and electrically connected to the first vertical interconnect channel and the first conductive structure respectively.

[0015] The three-dimensional storage structure provided in this application embodiment includes a second vertical interconnect channel similar to the first vertical interconnect channel. In fact, the overall top surface area of ​​the two vertical interconnect channels is larger than that of the first vertical interconnect channel, and the second vertical interconnect channel can be positioned closer to the outer edge. By sharing the corrosion load from the electrochemical reaction with the second vertical interconnect channel, the reliability of the first vertical interconnect channel used to realize the preset function of the three-dimensional storage structure is ensured.

[0016] Furthermore, by increasing the overall top surface area of ​​at least one first vertical interconnect channel electrically connected to the same conductive structure—specifically, by increasing the proportion of the overall top surface of at least one first vertical interconnect channel electrically connected to the same conductive structure to the first region—the residual portion of the first vertical interconnect channel after electrochemical corrosion is increased. This effectively avoids the formation of numerous large-sized pits in the first vertical interconnect channel, thereby ensuring bonding stability and guaranteeing electrical connection. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0018] Figure 1 It is a top-view photograph of the three-dimensional storage structure of the background technology;

[0019] Figure 2 This is an adaptive top view of a three-dimensional storage structure according to the proportions of this application;

[0020] Figure 3 This is a schematic top view of a three-dimensional storage structure according to an embodiment of this application;

[0021] Figure 4 yes Figure 3 A schematic cross-sectional view at point AA;

[0022] Figure 5 This is a schematic structural diagram of a three-dimensional storage structure according to another embodiment of this application;

[0023] Figure 6 This is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of this application;

[0024] Figure 7 This is a schematic top view of a three-dimensional storage structure according to an embodiment of this application;

[0025] Figure 8 This is a schematic structural diagram of a three-dimensional storage structure according to another embodiment of this application. Detailed Implementation

[0026] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this application, the first vertical interconnect channel discussed below may also be referred to as the second vertical interconnect channel, and vice versa.

[0028] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the diameter of the top surface of the first vertical interconnect channel is not proportional to the diameter of the third vertical interconnect channel in actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0029] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0030] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0032] refer to Figure 2 The diagram illustrates a comparative three-dimensional storage structure of this application. Further, Figure 2 The structural diagram shown can be a top view of the memory chip or a bottom view of the peripheral circuit chips. Exemplarily, this three-dimensional memory structure includes an array of multiple first vertical interconnect channels 41, and third vertical interconnect channels 42 and virtual vertical interconnect channels 43 located outside these first vertical interconnect channels 41. In some cases, the third vertical interconnect channels 42 and virtual vertical interconnect channels 43 have a higher potential in electrochemical reactions than the first vertical interconnect channels 41.

[0033] Taking a memory chip as an example, the first vertical interconnect channel 41 can be electrically connected to the substrate (not shown) via a conductive structure (not shown) on its back, such as a P-well region of the substrate. Since the conductive structure can be deflected in a direction parallel to the substrate, a first vertical interconnect channel 41 and its electrically connected P-well region do not necessarily coincide in the projection direction. Exemplarily, in this comparative example, the first vertical interconnect channel 41 and the P-well region are electrically connected in a one-to-one correspondence. Figure 3 As shown, on the top surface of the chip, a first vertical interconnect channel 41 occupies a first region a1 that does not interfere with adjacent structural regions. Since multiple first vertical interconnect channels 41 are typically arranged adjacent to each other, these first vertical interconnect channels 41 as a whole can occupy a low potential region A.

[0034] In this comparative example, the diameter of the top surface of the first vertical interconnect channel 41 is approximately 200 nm. Furthermore, the ratio of the area of ​​the first vertical interconnect channel 41 to the area of ​​the first region a1 it is located in can be less than or equal to 20%. The memory chip in this comparative example can be bonded to peripheral circuit chips, with the first vertical interconnect channel 41 bonded to the vertical interconnect channels of the peripheral circuit chips. When some of the first vertical interconnect channels 41 are etched with pits, the bonding area of ​​these first vertical interconnect channels 41 is smaller and the resistance is higher.

[0035] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] refer to Figure 3 and 4This application provides a three-dimensional memory structure, including: a substrate 1, a channel structure (not shown), a first conductive path 21, and a second conductive path 22. Exemplarily, conductive paths 21-22 are disposed on at least one corresponding channel structure. Exemplarily, the first conductive path 21 may include a first conductive channel 211 in the direction away from the substrate 1, a lower contact 212, a lower interconnect 213, an upper contact 214, an upper interconnect 215, a first through-silicon contact 31, and a first vertical interconnect channel 41. The first conductive channel 211 to the upper interconnect 215 constitute a first conductive structure 210. The second conductive path 22 includes at least a second conductive structure 220 disposed in the direction away from the substrate 1, a second through-silicon contact 32, and a second vertical interconnect channel 44.

[0037] Substrate 1 includes a first functional region 11 and a protective region 13, both exhibiting the same conductivity. In some embodiments, a channel structure disposed on the substrate is electrically connected to the first functional region 11 and electrically isolated from the protective region 13. In other embodiments, the area of ​​the first functional region can be increased compared to an existing area, and the additional portion, i.e., the protective region, allows a second conductive path to be electrically connected to the first functional region. However, the second conductive path is typically not used to implement the functionality of a three-dimensional memory.

[0038] The first conductive structure 210 and the second conductive structure 220 are also disposed on the substrate and are electrically connected to the first functional region 11 and the protective region 13, respectively. Furthermore, the first vertical interconnect channel 41 disposed on the first conductive structure 210 is electrically connected to the first functional region 11 through the first conductive structure 210. The first vertical interconnect channel 41 is used to perform the function of the three-dimensional storage structure. The second vertical interconnect channel 44 disposed on the second conductive structure 23 is electrically connected to the protective region 13 through the second conductive structure 23. The second vertical interconnect channel 44 may not be used to realize the preset function of the three-dimensional storage structure, but it has similar characteristics to the first vertical interconnect channel 41 in electrochemical reactions.

[0039] In the three-dimensional storage structure provided in this application, a plurality of second vertical interconnect channels 44 are disposed on one side of the first vertical interconnect channel 41. Furthermore, the plurality of second vertical interconnect channels 44 are configured to surround the first vertical interconnect channel 41.

[0040] refer to Figure 3 Each of the multiple first functional areas 11 and the multiple first vertical interconnect channels 41 may occupy a low potential area A. For example, the sum of the top surface area of ​​these first vertical interconnect channels 41 and the top surface area of ​​the second vertical interconnect channel 44 located outside the low potential area A is greater than 25% of the area of ​​the low potential area A.

[0041] The second vertical interconnect channel 44 can serve as an adjacent structure to the first vertical interconnect channel 41, and the second vertical interconnect channel 44 can occupy the second region b1. The second region c1 does not interfere with the first region a1; specifically, the boundary between them can be located at the midpoint between the first vertical interconnect channel 41 and the second vertical interconnect channel 44. For example, when the areas of the first vertical interconnect channel 41 and the second vertical interconnect channel 44 are different, the midpoint between the center of the first vertical interconnect channel 41 and the center of the second vertical interconnect channel 44 can serve as the boundary between the two regions a1 / b1, and in this case, the area proportion of the first vertical interconnect channel 41 is larger. In other embodiments, if the midpoint between the first vertical interconnect channel 41 and the second vertical interconnect channel 44 is used as the boundary between the two regions a1 / b1, the area proportion of the first vertical interconnect channel 41 can typically be more than 25%.

[0042] In an exemplary embodiment, multiple second regions b1 are configured to surround a first region a1. Specifically, the protective transition region B formed by the multiple second regions b1 can completely surround the low-potential region A formed by the multiple first regions a1. During the electrochemical reaction, currents are generated in different electrical regions and at critical points, and the metal near the boundary is etched first. By placing multiple second vertical interconnect channels 44 outside the first vertical interconnect channel 41, the first vertical interconnect channel 41 can be completely protected. The second vertical interconnect channels 44 withstand electrochemical corrosion to a greater extent, thereby better protecting the first vertical interconnect channel 41.

[0043] The three-dimensional storage structure provided in this embodiment protects the first vertical interconnect channel 41 by setting a second vertical interconnect channel 44, which makes the three-dimensional storage structure more reliable and has better working performance.

[0044] In an exemplary implementation, reference Figure 5 The substrate 1 further includes a second functional region 12, the electrical properties of which differ from those of the first functional region 11. For example, the second functional region 12 may be an N-well region.

[0045] The three-dimensional storage structure also includes a third conductive channel 23 electrically connected to the second functional region 12. The third conductive channel 23 may include a third conductive structure 230 and a third vertical interconnect channel 42. The third conductive structure is disposed on the substrate 1 and electrically connected to the second functional region 12. The third vertical interconnect channel 42 is electrically connected to the second functional region 12 through the third conductive structure 230. Because the electrical properties of the second functional region 12 are different from those of the first functional region 11, the performance of the third vertical interconnect channel 42 in electrochemical reactions may differ from that of the first vertical interconnect channel 41. In this embodiment, at least one second vertical interconnect channel 44 may be disposed between the first vertical interconnect channel 41 and the third vertical interconnect channel 42.

[0046] Furthermore, each third vertical interconnect channel may occupy a third region on a surface of the three-dimensional storage structure. The third region does not interfere with the regions occupied by adjacent structures, such as the second region. In this embodiment, the third region may not be adjacent to the first region.

[0047] In some implementations, a virtual vertical interconnect channel or other structure may also be provided outside the protection transition zone B.

[0048] In an exemplary embodiment, the material of the first vertical interconnect channel 41 includes copper. Further, the material of each vertical interconnect channel 41-44 may also include copper.

[0049] For example, the first functional region may not necessarily be a P-well region. Based on existing three-dimensional memory structures or comparative three-dimensional memory structures, different functional regions of the substrate can correspond to different regions on the top surface of the three-dimensional memory structure. Under complex manufacturing conditions, vertical interconnect channels in some regions are more susceptible to etching. Therefore, the portions of the substrate electrically connected to these vertical interconnect channels can be considered as the first functional region, and the conductive channels containing these vertical interconnect channels are the first conductive channels.

[0050] refer to Figure 5 In an exemplary embodiment, the three-dimensional storage structure further includes a second conductive path 22 and a channel structure (not shown). The substrate 1 also includes a protection zone 13. The second conductive path 22 may include a second conductive structure 220 and a second vertical interconnect channel 44.

[0051] The channel structure is disposed on the substrate 1. The first functional region 11 is electrically connected to the channel structure through other structures of the substrate 1, so that the first vertical interconnect channel 41 cooperates with the channel structure to realize the preset function of the three-dimensional storage structure. The protection zone 13 has the same structure or material as the first functional region 11, for example, it can also be a P-well region or other structures. However, the protection zone 13 is not electrically connected to the channel structure used to realize the function in the substrate 1.

[0052] The second vertical interconnect channel 44 is disposed on the second conductive structure 230 and electrically connected to the protection zone 13 through the second conductive structure 230. In an exemplary embodiment, the three-dimensional storage structure further includes a second through-silicon contact 32 electrically disposed between the second vertical interconnect channel 44 and the second conductive structure 23.

[0053] Because the protected area 13 and the first functional area 11 have the same characteristics, the second vertical interconnect channel 44 and the first vertical interconnect channel 41 have similar characteristics during the electrochemical reaction process. Therefore, the second vertical interconnect channel 44 shares the corrosion load received by the first vertical interconnect channel 41, thus maintaining the good morphology of the first vertical interconnect channel 41.

[0054] Figure 6 This is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of this application. Figure 7 This is a top view of a three-dimensional storage structure according to an embodiment of this application. (Reference) Figure 6 and Figure 7 The three-dimensional memory structure provided in this application includes a substrate 1 and at least one first conductive path 21 disposed on the substrate 1. The first conductive path 21 may include a first conductive structure 210 and at least one first vertical interconnect channel 41. Specifically, the three-dimensional memory structure includes a memory chip or a peripheral circuit chip, and the first vertical interconnect channel 41 is used for bonding with the vertical interconnect channel of the opposite chip.

[0055] The substrate 1 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Various circuit structures, including a first functional region 11, are disposed on the body (not shown) of the substrate 1. The first functional region 11 may be a P-well region for forming circuits located in the substrate 1. Exemplarily, a stacked structure and a channel structure (not shown) extending through the stacked structure and into the substrate 1 are disposed on the substrate 1. The first functional region 11 may be used to form CMOS electrically connected to the channel structure or for electrically connecting to the channel structure; the first functional region 11 may also be used to implement other predetermined functions of the three-dimensional memory structure.

[0056] A first conductive structure 210 is disposed on the substrate 1 and electrically connected to the first functional region 11. In an exemplary embodiment, the first conductive structure 210 includes a first conductive channel 211, a lower contact 212, a lower interconnect 213, an upper contact 214, and an upper interconnect 215 sequentially disposed in a direction away from the substrate 1. Specifically, an interconnect structure layer may be disposed on the stacked structure, thereby allowing the first conductive channel 211 to penetrate the stacked structure, while the lower contact 212, lower interconnect 213, upper contact 214, and upper interconnect 215 are located in the interconnect structure layer. In the interconnect structure layer, the lower interconnect 213 and the upper interconnect 215 may extend in a direction parallel to the substrate 1, such that the top of the upper interconnect 215, which can be used as an electrical connection area, may be misaligned with the first functional region 11 in a direction parallel to the substrate 1.

[0057] In an exemplary embodiment, the three-dimensional memory structure further includes a first through-silicon contact 31 (TSC). The first through-silicon contact 31 is disposed between the first vertical interconnect channel 41 and the first conductive structure 210, and is electrically connected to both the first vertical interconnect channel 41 and the first conductive structure 210. Specifically, the first through-silicon contact 31 is disposed on the upper interconnect structure 215. Exemplarily, the ratio of the diameter of the top surface of the first vertical interconnect channel 41 to the diameter of the first through-silicon contact 31 is greater than 3. In an exemplary embodiment, the diameter of the first vertical interconnect channel 41 is greater than 500 nm. Exemplarily, the diameter of the first vertical interconnect channel 41 is less than 2000 nm or less than 1000 nm.

[0058] A first vertical interconnect channel 41 is disposed on and electrically connected to the first conductive structure 210. For example, one first conductive structure 210 is electrically connected to at least one first vertical interconnect channel 41.

[0059] In an exemplary implementation, reference Figure 7 The first region a1 occupied by the first vertical interconnect channel 41 may be generally rectangular. Multiple first vertical interconnect channels 41 may be arranged in a generally rectangular array. Exemplarily, the top of the three-dimensional memory structure also includes a third vertical interconnect channel 42. The material of the third vertical interconnect channel 42 may be the same as that of the first vertical interconnect channel 41, but it does not corrode or has a lower corrosion rate during electrochemical reactions. The third vertical interconnect channel 42 plays a different role in the three-dimensional memory structure than the first vertical interconnect channel 41; it may be electrically connected to, for example, an N-well region. Each third vertical interconnect channel 42 may also occupy a second region b1.

[0060] For a first vertical interconnect channel 41, its adjacent structure can be another first vertical interconnect channel 41, a third vertical interconnect channel 42, or other structures. For a first region a1, its adjacent structural region can be another first region a1, a second region b1, or a region occupied by other structures. In the three-dimensional storage structure, each conductive structure 210 electrically connects to at least one vertical interconnect channel located at the top, which can occupy a corresponding region. This region and the conductive structure are not necessarily at the same projection position; for example, they may be misaligned.

[0061] For example, the midpoint between two adjacent vertical interconnect channels 41 / 42 can be used as the boundary location of their respective occupied regions a1 / b1. For instance, the midpoint between two adjacent first vertical interconnect channels 41 can be used as the partial boundary location of the first region a1. Each region a1 / b1 can be a boundary with its adjacent regions. The ratio of the top surface area of ​​at least one first vertical interconnect channel 41 electrically connected by a first conductive structure 210 to the area of ​​the first region a1 is not less than 25%.

[0062] When the substrate 1 electrically connected to the first conductive structure 210, specifically the first functional region 11 such as the P-well region, remains unchanged, the location of the first vertical interconnect channel 41 and the first region a1 it occupies can be designed to different positions or have different shapes. For example, when multiple first vertical interconnect channels 41 are arranged in a honeycomb pattern, the first region a1 occupied by each first vertical interconnect channel 41 that does not interfere with the adjacent structural region can be hexagonal.

[0063] The first region a1 of these first vertical interconnect channels 41 can also be formed as a low-potential region A. A high-potential vertical interconnect channel 42 is located outside the low-potential region A. The ratio of the total top surface area of ​​the at least two first vertical interconnect channels 41 electrically connected by the at least two first conductive structures 210 to the area of ​​the low-potential region A can also be not less than 25%, for example, an area ratio of 35%.

[0064] The top surface of the three-dimensional memory structure provided in this application embodiment is used for integration with another chip. The three-dimensional memory structure and the chip are electrically connected at least through a first vertical interconnect channel to achieve a predetermined function. By increasing the area exposed on the top surface of the three-dimensional memory structure of at least one first vertical interconnect channel electrically connected to a first functional area, for example, making the ratio of this area to the area of ​​the first region occupied by these first vertical interconnect channels not less than 25%, these first vertical interconnect channels have a larger window during electrochemical reactions to overcome pits caused by material loss. Therefore, when the three-dimensional memory structure is integrated with another chip, it can ensure that a corresponding pair of vertical interconnect channels (including the first vertical interconnect channel) are electrically connected.

[0065] refer to Figure 8 The illustration exemplarily depicts a three-dimensional storage structure according to one embodiment of the present application. The three-dimensional storage structure includes a substrate 1 and at least one first conductive path 21 disposed on the substrate 1. The first conductive path 21 may include a first conductive structure 210 and at least two first vertical interconnect channels 41.

[0066] The substrate 1 may include a body (not shown) and a first functional region 11. The first functional region 11 may be a P-well region. The first conductive structure 210 includes a first conductive channel 211, a lower contact 212, a lower interconnect 213, an upper contact 214, and an upper interconnect 215 sequentially disposed in a direction away from the substrate 1. The upper interconnect 215 extends a certain length in a direction parallel to the substrate 1, such that at least two first vertical interconnect channels 41 are electrically connected to the upper interconnect 215. Exemplarily, each first vertical interconnect channel 41 is electrically connected to the upper interconnect 215 via a first through-silicon contact 31.

[0067] For example, a portion of at least two first vertical interconnect channels 41 is used to implement the functionality of the three-dimensional storage structure, while the other portion may be unused in the circuit. These unused first vertical interconnect channels may be located outside the first vertical interconnect channels that are actually used.

[0068] Exemplarily, the first functional area 11 is electrically connected to at least two first vertical interconnect channels 41 via a first conductive structure 210, these first vertical interconnect channels 41 occupying a first region. Exemplarily, the area ratio of each first vertical interconnect channel 41 to the area of ​​the first region may not exceed 20%, while the ratio of the total top surface area of ​​the two first vertical interconnect channels 41 to the area of ​​the first region is greater than or equal to 25%, for example, 30%. In other embodiments, one of the two first vertical interconnect channels 41 may also occupy 20% or even more than 25% of the area of ​​the first region.

[0069] The three-dimensional memory structure provided in this embodiment can add at least one additional first vertical interconnect channel electrically connected to the same upper-layer interconnect, in addition to the existing first vertical interconnect channel. By sharing the corrosion during electrochemical reactions through the additional first vertical interconnect channel, it can be ensured that the first conductive structure can be well electrically connected to the chip when the three-dimensional memory structure is connected to other chips, thereby enabling the P-well region (first functional region) to perform its preset functions effectively. By placing these unused first vertical interconnect channels on the outside, the sacrifice of these unused first vertical interconnect channels can be better mitigated. Furthermore, the reliability of the three-dimensional memory structure can be further improved by controlling the area ratio of at least two first vertical interconnect channels corresponding to the first functional region to the first region.

[0070] In an exemplary embodiment, the substrate further includes a second functional region with electrical properties different from those of the first functional region. The three-dimensional memory structure also includes a third conductive structure disposed on the substrate and a third vertical interconnect channel disposed on the third conductive structure. Exemplarily, a third through-silicon contact electrically connected to the third conductive structure may also be disposed between the third vertical interconnect channel and the third conductive structure. Specifically, the second region is located between the first region and the third region occupied by the third vertical interconnect channel.

[0071] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this application.

Claims

1. A three-dimensional memory structure, comprising: include: A substrate includes a first functional region and a protection region, the protection region at least partially surrounding the first functional region in a direction parallel to the substrate; A stacked structure is disposed on the substrate; A trench structure extends through the stacked structure and connects to the first functional area, the trench structure being isolated from the protected area; A first conductive structure is disposed on the substrate and connected to the first functional area; A first vertical interconnect channel is disposed on the side of the first conductive structure opposite to the substrate and connected to the first conductive structure; as well as A second vertical interconnect channel is located on the substrate and connected to the protected area, the second vertical interconnect channel comprising at least a portion of the same conductive material as the first vertical interconnect channel. 2.The three-dimensional memory structure of claim 1, wherein, The three-dimensional storage structure further includes: a second conductive structure disposed on the substrate and connected to the protected area; and The second vertical interconnect channel is disposed on the side of the second conductive structure opposite to the substrate and is connected to the second conductive structure.

3. The three-dimensional memory structure of claim 1 or 2, wherein, Multiple second vertical interconnect channels are configured to surround multiple first vertical interconnect channels.

4. The three-dimensional memory structure of claim 3, wherein, The first conductive structure includes: a first conductive channel, a lower contact, a lower interconnect, an upper contact, and an upper interconnect arranged sequentially in a direction away from the substrate, wherein at least two of the first vertical interconnect channels are connected to the upper interconnect of the same first conductive structure.

5. The three-dimensional memory structure of claim 2, wherein, The substrate further includes a second functional region, the electrical properties of which are different from those of the first functional region; The three-dimensional storage structure also includes: A third conductive structure is disposed on the substrate and connected to the second functional region; and A third vertical interconnect channel is disposed on and connected to the third conductive structure, wherein the second vertical interconnect channel is located between the first vertical interconnect channel and the third vertical interconnect channel. 6.The three-dimensional memory structure of claim 1, wherein, The diameter of the top surface of the first vertical interconnect channel is between 500 nm and 2000 nm. 7.The three-dimensional memory structure of claim 1, wherein, The second vertical interconnect channel has the same potential as the first vertical interconnect channel in the electrochemical reaction. 8.The three-dimensional memory structure of claim 1, wherein, The conductive material includes copper. 9.The three-dimensional memory structure of claim 1, wherein, The conductivity of the first functional area is the same as that of the protected area.

10. The three-dimensional memory structure of claim 1, wherein, The first functional region includes a P-well region; The first conductive structure is connected to the P-well region. 11.The three-dimensional memory structure of claim 1, wherein, Also includes: Through-silicon contacts disposed between the first vertical interconnect channel and the first conductive structure, and respectively connected to the first vertical interconnect channel and the first conductive structure.

12. The three-dimensional memory structure of claim 11, wherein, The ratio of the diameter of the top surface of the first vertical interconnect channel to the diameter of the through silicon contact is greater than 3.

13. A three-dimensional memory structure, comprising: include: Substrate, including a first functional region; A stacked structure is disposed on the substrate; A channel structure extends through the stacked structure and connects to the first functional area; A first conductive structure is disposed on the substrate and connected to the first functional area, the first conductive structure including an upper interconnect on the side away from the substrate; as well as A first vertical interconnect channel, at least two of the first vertical interconnect channels are connected to the upper interconnect of the same first conductive structure.

14. The three-dimensional memory structure of claim 13, wherein, At least one of the at least two first vertical interconnect channels is used to implement a preset function for three-dimensional storage, and at least the other of the at least two first vertical interconnect channels is left unused in the circuit.

15. The three-dimensional memory structure of claim 13, wherein, The first conductive structure further includes: a first conductive channel, a lower contact, a lower interconnect, and an upper contact arranged sequentially in a direction away from the substrate, wherein the upper interconnect is located on the side of the upper contact away from the substrate and is connected to the upper contact; The upper interconnect extends in a direction parallel to the substrate and includes two ends in a direction parallel to the substrate. The upper contact and at least one of the at least two first vertical interconnect channels are connected to the same end of the two ends, and at least one of the at least two first vertical interconnect channels is connected to the other end of the two ends.

16. The three-dimensional memory structure of any one of claims 13-15, wherein, In a direction parallel to the substrate, the size of the upper interconnect is larger than the size of the first vertical interconnect channel.

17. The three-dimensional memory structure of claim 13, wherein, The first functional region includes a P-well region; The first conductive structure is connected to the P-well region.

18. The three-dimensional memory structure of claim 13, wherein, Also includes: Through-silicon contacts are disposed between the first vertical interconnect channel and the upper interconnect, and are respectively connected to the first vertical interconnect channel and the upper interconnect.

19. The three-dimensional memory structure of claim 13, wherein, The material of the first vertical interconnect channel includes copper.

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