Semiconductor device, manufacturing method thereof and operating method thereof

Abstract

The present technology relates to a semiconductor device, a method of manufacturing the same, and a method of operating the same. The semiconductor device includes: a gate stack including first interlayer insulating layers and word line stack layers alternately stacked; a vertical channel structure extending in a vertical direction in the gate stack; and a memory structure interposed between the word line stack layers and the vertical channel structure, each word line stack layer including an even conductive layer, a second interlayer insulating layer, and an odd conductive layer stacked in sequence, and a thickness of any one of the first interlayer insulating layers is greater than a thickness of any one of the second interlayer insulating layers.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a semiconductor device, a method of manufacturing the semiconductor device, and a method of operating the semiconductor device. Background Art

[0002] A nonvolatile memory device is a memory device that retains stored data even if its power supply is cut off. Recently, as improvements in the integration of two-dimensional nonvolatile memory devices in which memory cells are formed in a single layer on a substrate have reached a maximum limit, three-dimensional nonvolatile memory devices in which memory cells are vertically stacked on a substrate have been proposed.

[0003] A three-dimensional nonvolatile memory device includes interlayer insulating layers and gate electrodes alternately stacked and a channel layer passing through the interlayer insulating layers and the gate electrodes, and memory cells are stacked along the channel layer. In order to improve the operational reliability of a nonvolatile memory device having such a three-dimensional structure, various structures and manufacturing methods are being developed. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a gate stack including alternately stacked first interlayer insulating layers and word line stacks; a channel layer extending in a vertical direction in the gate stack; and a memory structure inserted between the word line stack and the channel layer, each word line stack including an even conductive layer, a second interlayer insulating layer and an odd conductive layer stacked in sequence, and a thickness of each first interlayer insulating layer is greater than a thickness of any second interlayer insulating layer included in any word line stack.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stacked structure by alternately stacking a first material layer and a multilayer stack, wherein each multilayer stack includes a second material layer, a third material layer and another second material layer stacked in sequence; forming a vertical hole that at least partially passes through the stacked structure; forming a recessed area by etching the sidewall of the second material layer exposed by the vertical hole to a specific depth; forming a blocking insulating layer by oxidizing the sidewall of the second material layer exposed by the recessed area; forming a charge capture layer in each recessed area, wherein the charge capture layers are spaced apart from each other in a vertical direction by the first material layer and the third material layer; and forming a tunnel insulating layer and a channel layer in sequence along the sidewall of the vertical hole, and the thickness of any one of the first material layers is greater than the thickness of any one of the third material layers.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a gate stack including a first interlayer insulating layer and a word line stack layer alternately stacked; a channel layer extending in a vertical direction in the gate stack; and a memory structure inserted between the word line stack layer and the channel layer, each word line stack layer including an even conductive layer, a second interlayer insulating layer and an odd conductive layer stacked in sequence, each memory structure including a blocking insulating layer, a charge trapping layer and a tunnel insulating layer inserted in sequence between the sidewalls of the even conductive layer and the sidewalls of the odd conductive layer, and the thickness of any first interlayer insulating layer is greater than the thickness of any second interlayer insulating layer.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stacked structure by alternately stacking a first material layer and a multilayer stack, wherein each multilayer stack includes a second material layer, a third material layer and another second material layer stacked in sequence; forming a vertical hole that at least partially passes through the stacked structure; forming a first recessed region by etching the sidewall of the second material layer exposed by the vertical hole to a specific depth; forming a blocking insulating layer by oxidizing the sidewall of the second material layer exposed by the first recessed region; forming a charge capture layer in each first recessed region, wherein the charge capture layers are spaced apart from each other in a vertical direction by the first material layer and the third material layer; forming a second recessed region by etching the sidewall of the charge capture layer exposed by the vertical hole to a specific depth; forming a tunnel insulating layer in each second recessed region; and forming a channel layer along the sidewall of the vertical hole.

[0008] According to an embodiment of the present disclosure, a method for operating a semiconductor device may include the following steps: providing a memory cell array including a first memory group, a first interlayer insulating layer, and a second memory group stacked in a vertical direction, wherein each of the first memory group and the second memory group includes an even memory cell, a second interlayer insulating layer, and an odd memory cell stacked in the vertical direction, and the thickness of any one of the first interlayer insulating layers is greater than the thickness of any one of the second interlayer insulating layers; programming the even memory cells of the first memory group with a first programming method; and programming the odd memory cells of the first memory group with a second programming method, and the first programming method is a programming method with relatively high storage bits compared to the second programming method.

[0009] According to an embodiment of the present disclosure, a method for operating a semiconductor device may include the following steps: providing a memory cell array including a first memory group, a first interlayer insulating layer, and a second memory group stacked in a vertical direction, wherein each of the first memory group and the second memory group includes even memory cells, a second interlayer insulating layer, and odd memory cells stacked in the vertical direction, and the thickness of any one of the first interlayer insulating layers is greater than the thickness of any one of the second interlayer insulating layers; reading the even memory cells of the first memory group; and reading the odd memory cells of the first memory group, and reading the even memory cells of the first memory group includes applying a read voltage to the even memory cells of the first memory group, applying a first pass voltage to the odd memory cells of the first memory group, and applying a second pass voltage higher than the first pass voltage to the even memory cells and the odd memory cells of the second memory group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is a circuit diagram showing a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3 is a cross-sectional view showing a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5 is a cross-sectional view showing a memory cell array of a semiconductor device according to another embodiment of the present disclosure.

[0015] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0016] Figure 7 is a flowchart illustrating a programming method of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 8is a flowchart illustrating a reading method of a semiconductor device according to an embodiment of the present disclosure.

[0018] Fig. 9 is a diagram showing a solid state drive (SSD) system to which the semiconductor device of the present disclosure is applied. DETAILED DESCRIPTION

[0019] Only the specific structural or functional description of the embodiments of the concepts disclosed in this specification or this application is shown to describe the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0020] Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the semiconductor device, and a method for operating the semiconductor device, wherein the integration of memory cells is improved by reducing a gap between at least two memory cells adjacent in the vertical direction among a plurality of memory cells stacked in the vertical direction.

[0021] In various embodiments, the integration of the memory cells can be improved by reducing the gap between at least two memory cells adjacent in the vertical direction among a plurality of memory cells stacked in the vertical direction. In addition, during a programming operation and a read operation, in an embodiment, a pass voltage applied to a memory cell adjacent to a selected memory cell can be applied to be lower than a pass voltage applied to other memory cells, thereby improving a disturbance phenomenon.

[0022] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the semiconductor device 1100 may include a memory cell array 110 storing data and a peripheral circuit including elements 120 to 170 capable of performing a program operation, a read operation, or an erase operation.

[0024] The memory cell array 110 may include a plurality of memory blocks storing data. Each memory block includes a plurality of memory cells, and the plurality of memory cells may be nonvolatile memory cells. The nonvolatile memory cells may be implemented in a three-dimensional structure in which the nonvolatile memory cells are stacked on a substrate in a vertical direction.

[0025] The peripheral circuit including the elements 120 to 170 may include a row decoder 120 , a voltage generator 130 , a page buffer group 140 , a column decoder 150 , an input / output circuit 160 , and a control logic circuit 170 .

[0026] The row decoder 120 may select one memory block from among memory blocks included in the memory cell array 110 according to the row address RADD and transmit an operating voltage Vop to the selected memory block.

[0027] The voltage generator 130 may generate and output an operation voltage Vop required for various operations in response to the operation code OPCD. For example, the voltage generator 130 may generate a set voltage, a reset voltage, a turn-on voltage, a turn-off voltage, a read voltage, an erase voltage, etc. in response to the operation code OPCD, and selectively output the generated voltage. According to the present embodiment, the voltage generator 130 may generate a voltage equal to or greater than 0V as a voltage to be applied to a word line, and may further include a device for generating a negative voltage less than 0V.

[0028] The page buffer group 140 may be connected to the memory cell array 110 via a bit line. For example, the page buffer group 140 may include page buffers connected to the respective bit lines. The page buffers may operate simultaneously in response to the page buffer control signal PBSIG, and may store data during a programming operation or a read operation. During a read operation or a verification operation, the page buffer may sense the current of the bit line that varies according to the threshold voltage of the memory cell. The words "simultaneously" and "simultaneously" used herein with respect to a process mean that the processes occur at overlapping time intervals. For example, if a first process occurs at a first time interval and a second process occurs simultaneously at a second time interval, the first interval and the second interval overlap at least partially with each other, so that there is a time when both the first process and the second process occur.

[0029] The column decoder 150 may transmit data DATA between the input / output circuit 160 and the page buffer group 140 according to the column address CADD.

[0030] The input / output circuit 160 may be connected to an external device through an input / output line IO. For example, the external device may be a controller capable of sending a command CMD, an address ADD, or data DATA to the semiconductor device 1100. The input / output circuit 160 may input and output a command CMD, an address ADD, and data DATA through the input / output line IO. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external device through the input / output line IO to the control logic circuit 170, and send data DATA received from an external device through the input / output line IO to the column decoder 150. The input / output circuit 160 may output the data DATA received from the column decoder 150 to the external device through the input / output line IO.

[0031] The control logic circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, the control logic circuit 170 may include software that executes an algorithm in response to the command CMD and hardware configured to output the address ADD and various signals.

[0032] Figure 2 is a circuit diagram showing a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0033] Reference Figure 2 , a plurality of even word lines WLe and a plurality of odd word lines WLo arranged in parallel between the first selection line and the second selection line may be connected to the memory cell array 110. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. For example, the memory cell array 110 may include a plurality of memory strings ST connected between the bit lines BL1 to BLm and the source lines SL. The bit lines BL1 to BLm may be connected to the memory strings ST, respectively, and the source lines SL may be connected to the memory strings ST in common.

[0034] Since the memory strings ST may be configured identically to one another, the memory string ST connected to the first bit line BL1 is specifically described as an example.

[0035] The memory string ST may include a source selection transistor SST, a plurality of even memory cells MCe, a plurality of odd memory cells MCo, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. In one memory string ST, at least one or more source selection transistors SST and at least one or more drain selection transistors DST may be included, and a plurality of even memory cells MCe and a plurality of odd memory cells MCo whose number is greater than the number shown in the figure may also be included. A plurality of even memory cells MCe and a plurality of odd memory cells MCo may be alternately arranged. The source selection transistor SST, a plurality of even memory cells MCe, a plurality of odd memory cells MCo, and a drain selection transistor DST may be stacked and arranged in a first direction Z (vertical direction of the substrate).

[0036] The source of the source selection transistor SST may be connected to the source line SL, and the drain of the drain selection transistor DST may be connected to the first bit line BL1. A plurality of even memory cells MCe and a plurality of odd memory cells MCo may be alternately connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different memory strings ST may be connected to the source selection line SSL, the gates of the drain selection transistors DST may be connected to the drain selection line DSL, the gates of the plurality of even memory cells MCe may be respectively connected to a plurality of even word lines WLe, and the gates of the plurality of odd memory cells MCo may be respectively connected to a plurality of odd word lines WLo. The plurality of even word lines WLe and the plurality of odd word lines WLo may extend in a second direction X (horizontal direction of the substrate). The second direction X may be orthogonal to the first direction Z.

[0037] A plurality of even memory cells MCe and a plurality of odd memory cells MCo respectively connected to an even word line WLe and an odd word line WLo disposed adjacent to each other may be defined as a memory group MGR. A plurality of even memory cells MCe and a plurality of odd memory cells MCo included in a memory group MGR may be programmed in different programming methods. For example, a plurality of even memory cells MCe included in a memory group MGR may be programmed in a quad-level cell (QLC) method, and a plurality of odd memory cells MCo may be programmed in a triple-level cell (TLC) method. As another embodiment, a plurality of even memory cells MCe included in a memory group MGR may be programmed in a QLC method, and a plurality of odd memory cells MCo may be programmed in a multi-level cell (MLC) method. The programming operation of the semiconductor device may be performed in units of pages. For example, a programming operation of an even memory cell MCe connected to an even word line WLe included in a memory group MGR may be performed, and then a programming operation of an odd memory cell MCo connected to an odd word line WLo may be performed. During a programming operation of a semiconductor device, a memory cell that is first programmed among even memory cells MCe and odd memory cells MCo included in one memory group MGR may be programmed in a programming method in which the storage bit of the memory cell is relatively high, and a memory cell that is programmed thereafter may be programmed in a programming method in which the storage bit of the memory cell is relatively low. For example, when a programming operation of even memory cells MCe connected to an even word line WLe included in one memory group MGR is performed, and then a programming operation of odd memory cells MCo connected to an odd word line WLo is performed, the even memory cells MCe connected to the even word line WLe may be programmed in a QLC method in which the storage bit is relatively high, and the odd memory cells MCo connected to the odd word line WLo may be programmed in a TLC or MLC method in which the storage bit is relatively low.

[0038] Figure 3 is a cross-sectional view showing a memory cell array of a semiconductor device according to an embodiment of the present disclosure. Figure 3 Show Figure 2 part of the memory string ST.

[0039] Reference Figure 3 , the memory string may include a plurality of even memory cells MCe and a plurality of odd memory cells MCo, and the plurality of even memory cells MCe and the plurality of odd memory cells MCo may be connected to an even conductive layer CDLe corresponding to an even word line and an odd conductive layer CDLo corresponding to an odd word line. Each of the even memory cells MCe and the odd memory cells MCo may include a blocking insulating layer BOX, a charge trap layer CTN, a tunnel insulating layer TIL, and a channel layer CHL.

[0040] One even-numbered memory cell MCe and one odd-numbered memory cell MCo adjacent to each other in the first direction Z (vertical direction) may be included in one memory group MGR.

[0041] The first interlayer insulating layer ISL1 may be formed between the memory groups MGR adjacent in the first direction Z, and the second interlayer insulating layer ISL2 may be formed between one even memory cell MCe and one odd memory cell MCo included in one memory group MGR. The first interlayer insulating layer ISL1 and the second interlayer insulating layer ISL2 extend in the horizontal direction and are disposed between the even conductive layer CDLe and the odd conductive layer CDLo respectively connected to the even memory cell MCe and the odd memory cell MCo. The thickness T2 of the second interlayer insulating layer ISL2 may be smaller than the thickness T1 of the first interlayer insulating layer ISL1. That is, in an embodiment, the thickness T2 of the second interlayer insulating layer ISL2 disposed between one even memory cell MCe and one odd memory cell MCo adjacent in the first direction Z included in one memory group MGR may be smaller than the thickness T1 of the first interlayer insulating layer ISL1 disposed between the memory groups MGR adjacent in the first direction Z.

[0042] The gate stack GST may be configured by including an even conductive layer CDLe, an odd conductive layer CDLo, a first interlayer insulating layer ISL1, and a second interlayer insulating layer ISL2. An even conductive layer CDLe, a second interlayer insulating layer ISL2, and an odd conductive layer CDLo corresponding to a memory group MGR may be defined as a word line stack. For example, the first interlayer insulating layer ISL1 and a plurality of word line stacks may be alternately stacked on a lower structure (not shown). The lower structure may include a substrate or at least one of a source line, a source selection line, and a peripheral circuit formed on the substrate. In an embodiment, the even conductive layer CDLe and the odd conductive layer CDLo may be collectively referred to as a conductive layer CDL.

[0043] The even conductive layers CDLe and the odd conductive layers CDLo may be used as word lines or selection lines. For example, assuming that the first interlayer insulating layer ISL1 and a plurality of word line stacking layers are alternately stacked on the substrate, at least one even conductive layer CDLe disposed at the bottom and at least one odd conductive layer CDLo disposed at the top may be used as a selection line. Figure 3 As shown in FIG. 1 , the uppermost odd-numbered conductive layer CDLo disposed highest in the first direction Z compared to other conductive layers may be a selection line. Figure 3 As shown, the next-to-last even-numbered conductive layer CDLe disposed at the bottom in the first direction Z compared to other conductive layers may be a selection line.

[0044] The first and second interlayer insulating layers ISL1 and ISL2 may be formed of oxide, and the even and odd conductive layers CDLe and CDLo may include a conductive material such as polysilicon, tungsten, molybdenum, or metal.

[0045] In the memory string, a vertical hole VH may be formed passing through the first interlayer insulating layer ISL1, the second interlayer insulating layer ISL2, the even conductive layer CDLe, and the odd conductive layer CDLo in the first direction Z (vertical direction). The width of the vertical hole VH may decrease as measured toward the lower end. For example, the width VH_U of the lower end vertical hole may be smaller than the width VH_T of the upper end vertical hole.

[0046] The first interlayer insulating layer ISL1 and the second interlayer insulating layer ISL2 may protrude further in a direction adjacent to the vertical hole VH than the even conductive layer CDLe and the odd conductive layer CDLo. That is, the blocking insulating layer BOX and the charge trapping layer CTN may be interposed in a space between protrusions of the first interlayer insulating layer ISL1 and the second interlayer insulating layer ISL2 adjacent to each other along the first direction Z. That is, the blocking insulating layer BOX and the charge trapping layer CTN may be interposed between the even conductive layer CDLe and the odd conductive layer CDLo and the vertical hole VH. In an embodiment of the present disclosure, the blocking insulating layer BOX and the charge trapping layer CTN may be defined as a memory structure.

[0047] The tunnel insulating layer TIL and the channel layer CHL may be sequentially inserted along the sidewall of the vertical hole VH. For example, the tunnel insulating layer TIL may be inserted along the sidewall of the vertical hole VH (i.e., the sidewalls of the first interlayer insulating layer ISL1, the second interlayer insulating layer ISL2, and the charge trapping layer CTN), and the channel layer CHL may be inserted along the sidewall of the tunnel insulating layer TIL. The core insulating layer CO may be inserted in the central region of the vertical hole VH. In an embodiment of the present disclosure, the tunnel insulating layer TIL, the channel layer CHL, and the core insulating layer CO may be defined as a vertical channel structure.

[0048] The tunnel insulating layer TIL may be a layer through which charges tunnel by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride. The charge trapping layer CTN may include a plurality of trapping sites, and charges flowing through the tunnel insulating layer TIL during a programming operation may be trapped. The charge trapping layer CTN may include a nitride, a chalcogenide, or a metal oxide. The blocking insulating layer BOX may prevent or mitigate charges trapped in the charge trapping layer CTN from moving to the even conductive layer CDLe or the odd conductive layer CDLo, and may include a high dielectric constant material such as aluminum oxide Al2O3, hafnium oxide HfOx, and hafnium silicon oxide HfSiOx. The channel layer CHL may be used to allow current to flow in the memory string, and may be formed of polysilicon.

[0049] In an embodiment, the channel layer CHL may have a cylindrical structure extending in a first direction Z (vertical direction) in the vertical hole VH. The tunnel insulating layer TIL may extend in the first direction Z (vertical direction) in the vertical hole VH and may be formed to surround an outer sidewall of the channel layer CHL.

[0050] The charge trap layer CTN may be formed as a portion of the outer side wall surrounding the tunnel insulating layer TIL, and the charge trap layer CTN corresponding to one memory cell may have a structure separated from the charge trap layer CTN corresponding to another memory cell adjacent along the first direction Z (vertical direction) by the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2. Therefore, in an embodiment, interference phenomenon and disturbance phenomenon between memory cells adjacent along the first direction Z may be reduced.

[0051] In addition, the blocking insulating layer BOX can be formed as an outer side wall surrounding the charge capture layer CTN, and the blocking insulating layer BOX corresponding to one memory cell can have a structure separated from the blocking insulating layer BOX corresponding to another memory cell adjacent along the first direction Z (vertical direction) by the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2.

[0052] The vertical thickness of the blocking insulating layer BOX and the vertical thickness of the charge trapping layer CTN corresponding to one nonvolatile memory cell MC may be the same. In an embodiment, the vertical thickness of the layer may be measured in the first direction Z. The sidewall of the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2 in contact with the vertical hole VH may be located on the same line as the sidewall of the charge trapping layer CTN in contact with the vertical hole VH, or may be formed so that the side of the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2 in contact with the vertical hole VH protrudes compared to the sidewall of the charge trapping layer CTN in contact with the vertical hole VH. In addition, the upper surface heights of the even conductive layer CDLe or the odd conductive layer CDLo, the blocking insulating layer BOX, and the charge trapping layer CTN corresponding to one memory cell may be the same. In addition, the lower surface heights of the even conductive layer CDLe or the odd conductive layer CDLo, the blocking insulating layer BOX, and the charge trapping layer CTN corresponding to one memory cell may be the same. For example, the lower surface heights of the even conductive layer CDLe or the odd conductive layer CDLo, the blocking insulating layer BOX, and the charge trapping layer CTN corresponding to one memory cell may be the same, such as Figure 3 shown.

[0053] 4A to 4F is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0054] Reference Figure 4A , forming a stacked structure ST on the substrate SUB. The stacked structure ST may include first material layers 11 and multilayer stacks 14 that are alternately stacked. Each multilayer stack 14 may include a second material layer 12, a third material layer 13, and another second material layer 12 that are sequentially stacked. The first material layer 11, the second material layer 12, and the third material layer 13 may extend in the second direction X (the horizontal direction of the substrate SUB). The first material layer 11, the second material layer 12, and the third material layer 13 may be stacked in the first direction Z (the vertical direction of the substrate SUB). The first material layer 11, the second material layer 12, and the third material layer 13 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0055] The thickness T1 of the first material layer 11 may be greater than the thickness T2 of the third material layer 13 .

[0056] The first material layer 11 and the third material layer 13 may include a material having a high etching selectivity with respect to the second material layer 12. As an example, the first material layer 11 and the third material layer 13 may include an insulating material such as an oxide, and the second material layer 12 may include a sacrificial material such as a nitride. As another example, the first material layer 11 and the third material layer 13 may include an insulating material such as an oxide, and the second material layer 12 may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal.

[0057] Subsequently, a vertical hole VH may be formed passing through the stack structure ST. The vertical hole VH may be cylindrical extending in the first direction Z. The vertical hole VH may be formed such that a width VH_T of an upper portion is greater than a width VH_U of a lower portion.

[0058] Reference Figure 4B , the sidewall of the second material layer 12 exposed through the vertical hole VH may be etched to a specific depth to form a recessed region R. That is, the sidewall of the second material layer 12 is etched to a specific depth so that the first material layer 11 and the third material layer 13 protrude in the second direction X compared with the second material layer 12. Therefore, the sidewall of the vertical hole VH may be formed into a structure in which uneven portions are sequentially arranged in the first direction Z (vertical direction of the substrate SUB).

[0059] Reference Figure 4C , an oxidation process is performed to oxidize the sidewalls of the second material layer 12 exposed by the vertical hole VH to form a blocking insulating layer 15. The oxidation process may be performed as a radical oxidation process or a wet oxidation process. The sidewalls of the second material layer 12 may be oxidized by a specific thickness (i.e., in the X direction) by the oxidation process to form a blocking insulating layer 15.

[0060] Reference Figure 4D ,exist Figure 4C The charge trapping layer 16 is formed in the recessed region R. For example, the charge trapping layer 16 may be formed along the sidewall of the vertical hole VH, and the thickness may be controlled so that Figure 4C The concave region R is completely buried to form the charge trapping layer 16. Subsequently, by etching a portion of the charge trapping layer 16, the charge trapping layer 16 is left only in the Figure 4C That is, the charge trapping layer formed on the sidewalls of the first material layer 11 and the third material layer 13 is removed by etching to form a concave region R. Figure 4C The charge trap layers 16 in the recessed region R are physically and electrically separated from each other in the first direction Z. That is, the charge trap layers 16 adjacent to each other in the first direction Z have a structure that is spaced apart from each other by the first material layer 11 and the third material layer 13 .

[0061] The charge trapping layer 16 may include a charge trapping material, a nitride, a variable resistance material or nanostructure, a chalcogenide, a metal oxide, or a combination thereof.

[0062] Reference Figure 4E , along Figure 4D The sidewalls of the vertical hole VH are sequentially formed with a tunnel insulating layer 17 and a channel layer 18. The tunnel insulating layer 17 may be a layer through which charges are tunneled by FN tunneling, etc., and may include an insulating material such as oxide or nitride. The channel layer 18 may include polysilicon.

[0063] The tunnel insulating layer 17 may be formed along the sidewalls of the first and third material layers 11 and 13 and the sidewalls of the charge trap layer 16. The tunnel insulating layer 17 and the channel layer 18 may be formed to extend in the first direction Z.

[0064] Subsequently, a core insulating layer 19 may be formed to fill Figure 4D The core insulating layer 19 may include an oxide. Figure 4D When the central area of ​​the vertical hole VH is filled with the channel layer 18 , the process of forming the core insulating layer 19 may be skipped.

[0065] Reference Figure 4F ,Will Figure 4D The second material layer 12 is replaced by the conductive layer 20. For example, etching Figure 4D The stacked structure ST is formed to form a slit (not shown) extending in the first direction Z to expose Figure 4D The sidewalls of the second material layer 12 are selectively etched and removed. Figure 4D The second material layer 12 is filled with a conductive material. Figure 4D The second material layer 12 is removed from the space to form the conductive layer 20 .

[0066] The first material layer 11, the third material layer 13 and the conductive layer 20 may be defined as a gate stack GST. The first material layer 11 may correspond to Figure 3 The first interlayer insulating layer ISL1, the third material layer 13 may correspond to Figure 3 The second interlayer insulating layer ISL2, the conductive layer 20 may correspond to Figure 3 Even-numbered conductive layers CDLe and odd-numbered conductive layers CDLo.

[0067] Figure 5 is a cross-sectional view showing a memory cell array of a semiconductor device according to another embodiment of the present disclosure. Figure 5 Show Figure 2 part of the memory string ST.

[0068] Reference Figure 5 , the memory string may include a plurality of even memory cells MCe and a plurality of odd memory cells MCo, and the plurality of even memory cells MCe and the plurality of odd memory cells MCo may be connected to an even conductive layer CDLe corresponding to an even word line and an odd conductive layer CDLo corresponding to an odd word line. Each of the even memory cells MCe and the odd memory cells MCo may include a blocking insulating layer BOX, a charge trap layer CTN, a tunnel insulating layer TIL, and a channel layer CHL.

[0069] One even-numbered memory cell MCe and one odd-numbered memory cell MCo adjacent to each other in the first direction Z (vertical direction) may be included in one memory group MGR.

[0070] The first interlayer insulating layer ISL1 may be formed between the memory groups MGR adjacent in the first direction Z, and the second interlayer insulating layer ISL2 may be formed between one even memory cell MCe and one odd memory cell MCo included in one memory group MGR. The first interlayer insulating layer ISL1 and the second interlayer insulating layer ISL2 extend in the horizontal direction and are disposed between the even conductive layer CDLe and the odd conductive layer CDLo respectively connected to the even memory cell MCe and the odd memory cell MCo. The thickness T2 of the second interlayer insulating layer ISL2 may be smaller than the thickness T1 of the first interlayer insulating layer ISL1. That is, the thickness T2 of the second interlayer insulating layer ISL2 disposed between one even memory cell MCe and one odd memory cell MCo adjacent in the first direction Z included in one memory group MGR may be smaller than the thickness T1 of the first interlayer insulating layer ISL1 disposed between the memory groups MGR adjacent in the first direction Z.

[0071] The gate stack GST may be configured by including an even conductive layer CDLe, an odd conductive layer CDLo, a first interlayer insulating layer ISL1, and a second interlayer insulating layer ISL2. One even conductive layer CDLe, one second interlayer insulating layer ISL2, and one odd conductive layer CDLo corresponding to one memory group MGR may be defined as one word line stack. For example, the first interlayer insulating layer ISL1 and a plurality of word line stacks may be alternately stacked on a lower structure (not shown). The lower structure may include a substrate or at least one of a source line, a source selection line, and a peripheral circuit formed on the substrate.

[0072] The even conductive layers CDLe and the odd conductive layers CDLo may be used as word lines or selection lines. For example, assuming that the first interlayer insulating layer ISL1 and a plurality of word line stacking layers are alternately stacked on the substrate, at least one even conductive layer CDLe disposed at the lower end and at least one odd conductive layer CDLo disposed at the upper end may be used as a selection line.

[0073] The first and second interlayer insulating layers ISL1 and ISL2 may be formed of oxide, and the even and odd conductive layers CDLe and CDLo may include a conductive material such as polysilicon, tungsten, molybdenum, or metal.

[0074] In the memory string, a vertical hole VH may be formed passing through the first interlayer insulating layer ISL1, the second interlayer insulating layer ISL2, the even conductive layer CDLe, and the odd conductive layer CDLo in the first direction Z (vertical direction). The width of the vertical hole VH may decrease toward the lower end. For example, the width VH_U of the lower end vertical hole may be smaller than the width VH_T of the upper end vertical hole.

[0075] The first interlayer insulating layer ISL1 and the second interlayer insulating layer ISL2 may protrude further in a direction adjacent to the vertical hole VH than the even conductive layer CDLe and the odd conductive layer CDLo. That is, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL may be interposed in a space between protrusions of the first interlayer insulating layer ISL1 and the second interlayer insulating layer ISL2 adjacent to each other along the first direction Z. That is, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL may be interposed between the even conductive layer CDLe and the odd conductive layer CDLo and the vertical hole VH. In an embodiment of the present disclosure, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL may be defined as a memory structure.

[0076] The channel layer CHL may be inserted along the sidewall of the vertical hole VH. For example, the channel layer CHL may be inserted along the sidewall of the vertical hole VH (i.e., the sidewalls of the first interlayer insulating layer ISL1, the second interlayer insulating layer ISL2, and the tunnel insulating layer TIL). The core insulating layer CO may be inserted in the central region of the vertical hole VH. In an embodiment of the present disclosure, the channel layer CHL and the core insulating layer CO may be defined as a vertical channel structure.

[0077] The tunnel insulating layer TIL may be a layer through which charges tunnel by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride. The charge trapping layer CTN may include a plurality of trapping sites, and charges flowing through the tunnel insulating layer TIL during a programming operation may be trapped. The charge trapping layer CTN may include a nitride, a chalcogenide, or a metal oxide. The blocking insulating layer BOX may prevent or mitigate charges trapped in the charge trapping layer CTN from moving to the even conductive layer CDLe or the odd conductive layer CDLo, and may include a high dielectric constant material such as aluminum oxide Al2O3, hafnium oxide HfOx, and hafnium silicon oxide HfSiOx. The channel layer CHL may be used to allow current to flow in the memory string, and may be formed of polysilicon.

[0078] The channel layer CHL may have a cylindrical structure extending in the first direction Z (vertical direction) in the vertical hole VH. The tunnel insulating layer TIL may be formed as a portion of the outer side wall surrounding the channel layer CHL. The charge trapping layer CTN may be formed as the outer side wall surrounding the tunnel insulating layer TIL, and the charge trapping layer CTN and the tunnel insulating layer TIL corresponding to one memory cell may have a structure separated from the charge trapping layer CTN and the tunnel insulating layer TIL corresponding to another memory cell adjacent along the first direction Z (vertical direction) by the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2. Therefore, in an embodiment, interference phenomenon and disturbance phenomenon between memory cells adjacent along the first direction Z can be reduced.

[0079] In addition, the blocking insulating layer BOX can be formed as an outer side wall surrounding the charge capture layer CTN, and the blocking insulating layer BOX corresponding to one memory cell can have a structure separated from the blocking insulating layer BOX corresponding to another memory cell adjacent along the first direction Z (vertical direction) by the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2.

[0080] The vertical thickness of the blocking insulating layer BOX, the vertical thickness of the charge trapping layer CTN, and the thickness of the tunnel insulating layer TIL corresponding to one nonvolatile memory cell MC may be the same. The side wall of the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2 in contact with the vertical hole VH may be located on the same line as the side wall of the tunnel insulating layer TIL in contact with the vertical hole VH, or may be formed so that the side of the first interlayer insulating layer ISL1 or the second interlayer insulating layer ISL2 in contact with the vertical hole VH protrudes compared to the side wall of the tunnel insulating layer TIL in contact with the vertical hole VH. In addition, the upper surface heights of the even conductive layer CDLe or the odd conductive layer CDLo, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL corresponding to one memory cell may be the same. In addition, the lower surface heights of the even conductive layer CDLe or the odd conductive layer CDLo, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL corresponding to one memory cell may be the same.

[0081] FIG. 6A to FIG. 6G is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0082] Reference Fig. 6A, forming a stacked structure ST on the substrate SUB. The stacked structure ST may include first material layers 31 and multilayer stacks 34 that are alternately stacked. Each multilayer stack 34 may include a second material layer 32, a third material layer 33, and a second material layer 32 that are sequentially stacked. The first material layer 31, the second material layer 32, and the third material layer 33 may extend in the second direction X (the horizontal direction of the substrate SUB). The first material layer 31, the second material layer 32, and the third material layer 33 may be stacked in the first direction Z (the vertical direction of the substrate SUB). The first material layer 31, the second material layer 32, and the third material layer 33 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0083] The thickness T1 of the first material layer 31 may be greater than the thickness T2 of the third material layer 33 .

[0084] The first material layer 31 and the third material layer 33 may include a material having a high etching selectivity with respect to the second material layer 32. As an example, the first material layer 31 and the third material layer 33 may include an insulating material such as an oxide, and the second material layer 32 may include a sacrificial material such as a nitride. As another example, the first material layer 31 and the third material layer 33 may include an insulating material such as an oxide, and the second material layer 32 may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal.

[0085] Subsequently, a vertical hole VH may be formed passing through the stack structure ST. The vertical hole VH may be cylindrical extending in the first direction Z. The vertical hole VH may be formed such that a width VH_T of an upper portion is greater than a width VH_U of a lower portion.

[0086] Reference Figure 6B , the sidewall of the second material layer 32 exposed by the vertical hole VH may be etched to a certain depth to form the first recessed region R1. That is, the sidewall of the second material layer 32 is etched to a certain depth so that the first material layer 31 and the third material layer 33 protrude in the second direction X compared with the second material layer 32. Therefore, the sidewall of the vertical hole VH may be formed into a structure in which uneven portions are sequentially arranged in the first direction Z (vertical direction of the substrate SUB).

[0087] Reference Figure 6C , an oxidation process is performed to oxidize the sidewalls of the second material layer 32 exposed by the vertical hole VH to form a blocking insulating layer 35. The oxidation process may be performed as a radical oxidation process or a wet oxidation process. The sidewalls of the second material layer 32 may be oxidized by a specific thickness through the oxidation process to form a blocking insulating layer 35.

[0088] Reference Fig.6D , forming a charge trapping layer 36 in contact with the blocking insulating layer 35. For example, the charge trapping layer 36 is formed along the sidewall of the vertical hole VH. The charge trapping layer 36 can be formed by controlling the thickness so that Figure 6C The first recessed region R1 is buried to form. At this time, the charge capture layer 36 may be formed so that the first recessed region R1 is completely buried, or only a portion of the first recessed region R1 is buried. The charge capture layer 36 may include a charge capture material, a nitride, a variable resistance material or a nanostructure, a chalcogenide, a metal oxide, or a combination thereof. Thereafter, an etching process is performed so that the charge capture layer 36 remains only in Figure 6C That is, the charge trapping layer formed on the sidewalls of the first material layer 31 and the third material layer 33 is removed by etching to form a first recessed region R1. Figure 6C The charge trap layers 36 in the first recessed region R1 are physically and electrically separated from each other in the first direction Z. That is, the charge trap layers 36 adjacent along the first direction Z have a structure separated from each other by the first material layer 31 and the third material layer 33 .

[0089] Thereafter, an additional etching process is performed to etch the charge trap layer 36 exposed by the vertical hole VH to a certain depth (ie, in the X direction) to form a second recessed region R2. That is, the sidewall of the charge trap layer 36 is etched to a certain depth so that the first material layer 31 and the third material layer 33 protrude in the horizontal direction compared to the charge trap layer 36.

[0090] Reference Fig. 6E ,exist Fig. 6F The tunnel insulating layer 37 is formed in the second recessed region R2. By performing an oxidation process, the tunnel insulating layer 37 may be formed to contact the sidewall of the charge trap layer 36. The tunnel insulating layer 37 may be a layer through which charges tunnel by FN tunneling or the like, and may include an insulating material such as oxide or nitride.

[0091] Reference Fig. 6F , along Fig. 6E The sidewalls of the vertical holes VH form channel layers 38. The channel layers 38 may include polysilicon.

[0092] The channel layer 38 may be formed along the sidewalls of the first material layer 31, the third material layer 33, and the tunnel insulating layer 37. The channel layer 38 may be formed to extend in the first direction Z.

[0093] Subsequently, a core insulating layer 39 may be formed to fill Fig. 6E The core insulating layer 39 may include an oxide. Fig. 6E When the central area of ​​the vertical hole VH is filled with the channel layer 38 , the process of forming the core insulating layer 39 may be skipped.

[0094] Reference Figure 6G ,Will Fig. 6F The second material layer 32 is replaced by the conductive layer 40. For example, etching Fig. 6FThe stacked structure ST is formed to form a slit extending in the first direction Z to expose Fig. 6F The sidewalls of the second material layer 32 are selectively etched and removed. Fig. 6F The second material layer 32 is filled with a conductive material. Fig. 6F The second material layer 32 is removed from the space to form the conductive layer 40 .

[0095] The first material layer 31 , the third material layer 33 , and the conductive layer 40 may be defined as a gate stack GST.

[0096] Figure 7 is a flowchart illustrating a programming method of a semiconductor device according to an embodiment of the present disclosure.

[0097] Reference Figure 1 , Figure 2 and Figure 7 A programming method of a semiconductor device is described as follows.

[0098] As reference Figure 3 or Figure 5 Described, Figure 2 A plurality of even memory cells MCe and a plurality of odd memory cells MCo included in the memory string ST may be included in one memory group MGR, and a thickness T2 of a second interlayer insulating layer ISL2 disposed between the even memory cells MCe and the odd memory cells MCo adjacent to each other in a vertical direction may be smaller than a thickness T1 of a first interlayer insulating layer ISL1 disposed between the memory groups MGR adjacent to each other.

[0099] In step S710, even memory cells MCe of a first memory group selected from among a plurality of memory groups MGR are programmed. The first memory group may be a memory group MGR adjacent to a source selection transistor SST. Even memory cells MCe of the selected first memory group may be programmed in a QLC method.

[0100] The page buffer group 140 applies a program inhibition voltage (eg, a power supply voltage) or a program permission voltage (eg, a ground voltage) to the bit lines BL1 to BLm based on data DATA received during a program operation.

[0101] The voltage generator 130 generates a program voltage, a first pass voltage, and a second pass voltage in response to the operation code OPCD. A potential level of the first pass voltage may be lower than a potential level of the second pass voltage.

[0102] According to the row address RADD, the row decoder 120 applies a program voltage to the even word line WLe corresponding to the first memory group, applies a first pass voltage to the odd word line WLo corresponding to the first memory group, and applies a second pass voltage to the even word lines WLe and odd word lines WLo corresponding to the remaining memory groups.

[0103] In an embodiment, during a programming operation, a relatively low level first pass voltage may be applied to odd memory cells MCo of a first memory group that are separated from even memory cells MCe of a selected first memory group by a thickness T2 of a second interlayer insulating layer ISL2 in a vertical direction, thereby suppressing a disturbance phenomenon of odd memory cells MCo of the first memory group caused by a programming voltage applied to an even word line WLe.

[0104] In step S720, the odd memory cells MCo of the first memory group selected from the plurality of memory groups MGR are programmed. The odd memory cells MCo of the selected first memory group may be programmed according to a programming method of storing bits lower than the programming method of the even memory cells MCe of the first memory group. For example, the odd memory cells MCo of the selected first memory group may be programmed according to a TLC method. Because the odd memory cells MCo of the first memory group close to the even memory cells MCe of the first memory group may be susceptible to interference, disturbance, etc., the odd memory cells MCo may be programmed according to a programming method with relatively high data stability.

[0105] The voltage generator 130 generates a program voltage, a first pass voltage, and a second pass voltage in response to the operation code OPCD. A potential level of the first pass voltage may be lower than a potential level of the second pass voltage.

[0106] According to the row address RADD, the row decoder 120 applies a program voltage to the odd word line WLo corresponding to the first memory group, applies a first pass voltage to the even word line WLe corresponding to the first memory group, and applies a second pass voltage to the even word line WLe and the odd word line WLo corresponding to the remaining memory groups.

[0107] In step S730, even memory cells MCe of a second memory group selected from among the plurality of memory groups MGR are programmed. The second memory group may be a memory group adjacent to the first memory group. Even memory cells MCe of the selected second memory group may be programmed in a QLC method.

[0108] In step S740, the odd memory cells MCo of the second memory group selected from the plurality of memory groups MGR are programmed. The odd memory cells MCo of the selected second memory group may be programmed according to a programming method of storing bits lower than the programming method of the even memory cells MCe of the second memory group. For example, the odd memory cells MCo of the selected second memory group may be programmed according to the TLC method.

[0109] Thereafter, a program operation may be performed by sequentially selecting a last selected memory group among the plurality of memory groups MGR.

[0110] As described above, according to the embodiments of the present disclosure, by programming the even memory cells and the odd memory cells included in the selected memory group with different programming methods during the programming operation of the semiconductor device, data stability can be improved. In addition, by applying a first pass voltage lower than a second pass voltage to the odd memory cells relatively close to the even memory cells during the programming operation of the even memory cells included in the selected memory group, the disturbance phenomenon can be improved.

[0111] Figure 8 is a flowchart illustrating a reading method of a semiconductor device according to an embodiment of the present disclosure.

[0112] Reference Figure 1 , Figure 2 and Figure 8 A reading method of a semiconductor device is described as follows.

[0113] As reference Figure 3 or Figure 5 Described, Figure 2 A plurality of even memory cells MCe and a plurality of odd memory cells MCo included in the memory string ST may be included in one memory group MGR, and a thickness T2 of a second interlayer insulating layer ISL2 disposed between the even memory cells MCe and the odd memory cells MCo adjacent to each other in a vertical direction may be smaller than a thickness T1 of a first interlayer insulating layer ISL1 disposed between the memory groups MGR adjacent to each other.

[0114] In step S810, even memory cells MCe of a first memory group selected from among a plurality of memory groups MGR are read. The first memory group may be a memory group MGR adjacent to a source selection transistor SST. When even memory cells MCe of the selected first memory group are programmed in a programming operation, even memory cells MCe of the selected first memory group may be read in a QLC method.

[0115] The voltage generator 130 generates a plurality of read voltages, a first pass voltage, and a second pass voltage in response to the operation code OPCD. A potential level of the first pass voltage may be lower than a potential level of the second pass voltage.

[0116] According to the row address RADD, the row decoder 120 applies a plurality of read voltages to the even word lines WLe corresponding to the first memory group, applies a first pass voltage to the odd word lines WLo corresponding to the first memory group, and applies a second pass voltage to the even word lines WLe and the odd word lines WLo corresponding to the remaining memory groups.

[0117] The page buffer group 140 senses data based on potential levels or current amounts of the bit lines BL1 to BLm.

[0118] In an embodiment, during a read operation, a first pass voltage of a relatively low level may be applied to odd memory cells MCo of a first memory group that are separated from even memory cells MCe of a selected first memory group by a thickness T2 of a second interlayer insulating layer ISL2 in a vertical direction, and a disturbance phenomenon of odd memory cells MCo of the first memory group may be suppressed.

[0119] In step S820, odd memory cells MCo of a first memory group selected from among the plurality of memory groups MGR are read. When odd memory cells MCo of the selected first memory group are programmed in a TLC method in a program operation, odd memory cells MCo of the selected first memory group may be read in the TLC method.

[0120] The voltage generator 130 generates a plurality of read voltages, a first pass voltage, and a second pass voltage in response to the operation code OPCD. A potential level of the first pass voltage may be lower than a potential level of the second pass voltage.

[0121] According to the row address RADD, the row decoder 120 applies a plurality of read voltages to the odd word lines WLo corresponding to the first memory group, applies a first pass voltage to the even word lines WLe corresponding to the first memory group, and applies a second pass voltage to the even word lines WLe and the odd word lines WLo corresponding to the remaining memory groups.

[0122] The page buffer group 140 senses data based on potential levels or current amounts of the bit lines BL1 to BLm.

[0123] In an embodiment, during a read operation, a first pass voltage of a relatively low level may be applied to the even memory cells MCe of the first memory group that are separated from the odd memory cells MCo of the selected first memory group by the thickness T2 of the second interlayer insulating layer ISL2 in the vertical direction, which may suppress the disturbance phenomenon of the even memory cells MCe of the first memory group.

[0124] In step S830, the even memory cells MCe of the second memory group selected from the plurality of memory groups MGR are read. The second memory group may be a memory group adjacent to the first memory group. When the even memory cells MCe of the selected second memory group are programmed in the QLC method in the programming operation, the even memory cells MCe of the selected second memory group may be read in the QLC method.

[0125] In step S840, odd memory cells MCo of a second memory group selected from among the plurality of memory groups MGR are read. When odd memory cells MCo of the selected second memory group are programmed in a TLC method in a program operation, odd memory cells MCo of the selected second memory group may be read in the TLC method.

[0126] As described above, according to an embodiment of the present disclosure, during a read operation of the even memory cells included in a selected memory group, a first pass voltage lower than a second pass voltage may be applied to odd memory cells relatively close to the even memory cells, and during a read operation of the odd memory cells included in the selected memory group, a first pass voltage lower than the second pass voltage may be applied to even memory cells relatively close to the odd memory cells, thereby improving the disturbance phenomenon.

[0127] Fig. 9 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0128] Reference Fig. 9 , the SSD system 2000 includes a host 2100 and an SSD 2200. The SSD 2200 exchanges signals with the host 2100 through a signal connector 2001, and receives power through a power connector 2002. The SSD 2200 includes a controller 2210, a plurality of memory devices 2221 to 222n, an auxiliary power supply 2230, and a buffer memory 2240.

[0129] The controller 2210 may control the plurality of memory devices 2221 to 222n in response to a signal received from the host 2100. For example, the signal may be a signal based on an interface between the host 2100 and the SSD 2200. For example, the signal may be a signal defined by at least one interface such as a Universal Serial Bus (USB), a Multi Media Card (MMC), an Embedded MMC (eMMC), a Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), an Advanced Technology Attachment (ATA), a Serial ATA, a Parallel ATA, a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0130] The plurality of memory devices 2221 to 222n may be configured to store data and include a plurality of nonvolatile memory cells. Each of the plurality of memory devices 2221 to 222n may be connected to Figure 1 The semiconductor devices 1100 shown are configured identically.

[0131] The auxiliary power supply 2230 is connected to the host 2100 through the power connector 2002. The auxiliary power supply 2230 may receive a power voltage from the host 2100 and be charged with the power voltage. When the power from the host 2100 is not smooth, the auxiliary power supply 2230 may provide a power voltage for the SSD 2200. For example, the auxiliary power supply 2230 may be located in the SSD 2200, or may be located outside the SSD 2200. For example, the auxiliary power supply 2230 may be located on a mainboard, and may provide auxiliary power to the SSD 2200.

[0132] The buffer memory 2240 operates as a buffer memory of the SSD 2200. For example, the buffer memory 2240 may temporarily store data received from the host 2100 or data received from the plurality of memory devices 2221 to 222n, or may store metadata (e.g., a mapping table) of the plurality of memory devices 2221 to 222n. The buffer memory 2240 may include a volatile memory such as DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), and LPDDR SDRAM (Low Power DDR SDRAM), or a nonvolatile memory such as FRAM (Ferroelectric Random Access Memory), ReRAM (Resistance Random Access Memory), STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory), and PRAM (Parametric Random Access Memory).

[0133] CROSS-REFERENCE TO RELATED APPLICATIONS

[0134] This application claims the priority of Korean Patent Application No. 10-2023-0128937 filed in the Korean Intellectual Property Office on September 26, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a gate stack including a first interlayer insulating layer and a word line stack layer alternately stacked; a channel layer extending in a vertical direction in the gate stack; as well as a memory structure interposed between the word line layer stack and the channel layer, Each of the word line stacking layers comprises an even-numbered conductive layer, a second interlayer insulating layer and an odd-numbered conductive layer stacked in sequence, and The thickness of each of the first interlayer insulating layers is greater than the thickness of any one of the second interlayer insulating layers included in any one of the word line stack layers.

2. The semiconductor device according to claim 1, wherein Each of the memory structures includes a blocking insulating layer and a charge trapping layer sequentially interposed between a sidewall of the even-numbered conductive layer and a sidewall of the odd-numbered conductive layer, and The side walls of the first interlayer insulating layer and the second interlayer insulating layer contacting the channel layer are located on the same line as the side walls of the charge capture layer contacting the channel layer, or the sides of the first interlayer insulating layer and the second interlayer insulating layer contacting the channel layer protrude farther toward the side walls of the channel layer compared to the charge capture layer.

3. The semiconductor device according to claim 2, wherein: The first interlayer insulating layer and the second interlayer insulating layer protrude further than the even-numbered conductive layer and the odd-numbered conductive layer in the direction of the channel layer, and The blocking insulating layer and the charge trap layer are interposed in a space between the protruding first and second interlayer insulating layers.

4. The semiconductor device according to claim 2, wherein: The charge trap layers interposed between side walls of each of the even-numbered conductive layers and the odd-numbered conductive layers are spaced apart from each other by the first interlayer insulating layer and the second interlayer insulating layer.

5. The semiconductor device according to claim 2, further comprising a tunnel insulating layer extending in the vertical direction along a side wall of the first interlayer insulating layer, a side wall of the second interlayer insulating layer, and a side wall of the charge trapping layer, in, The channel layer extends in the vertical direction along the sidewall of the tunnel insulating layer.

6. A method for manufacturing a semiconductor device, the method comprising the steps of: Forming a stacked structure by alternately stacking a first material layer and a multilayer stack, wherein each of the multilayer stacks includes a second material layer, a third material layer, and another second material layer stacked in sequence; forming a vertical hole at least partially through the stacked structure; forming a recessed area by etching the sidewall of the second material layer exposed by the vertical hole to a specific depth; forming a blocking insulating layer by oxidizing the sidewalls of the second material layer exposed by the recessed region; forming a charge trap layer in each of the recessed regions, wherein the charge trap layers are spaced apart from each other in a vertical direction by the first material layer and the third material layer; and forming a tunnel insulating layer and a channel layer in sequence along the sidewall of the vertical hole, Wherein, the thickness of any one of the first material layers is greater than the thickness of any one of the third material layers.

7. The method according to claim 6, wherein: The step of forming the blocking insulating layer includes the following steps: performing a radical oxidation process or a wet oxidation process to oxidize the sidewall of the second material layer by a specific thickness to form the blocking insulating layer.

8. The method according to claim 6, further comprising the steps of: After forming the channel layer, the second material layer is replaced with a conductive layer.

9. A semiconductor device, comprising: a gate stack including a first interlayer insulating layer and a word line stack layer alternately stacked; a channel layer extending in a vertical direction in the gate stack; as well as a memory structure interposed between the word line layer stack and the channel layer, Each of the word line stacking layers includes an even-numbered conductive layer, a second interlayer insulating layer and an odd-numbered conductive layer stacked in sequence. Each of the memory structures includes a blocking insulating layer, a charge trapping layer and a tunnel insulating layer sequentially interposed between the sidewalls of the even-numbered conductive layer and the sidewalls of the odd-numbered conductive layer, and Wherein, the thickness of any one of the first interlayer insulating layers is greater than the thickness of any one of the second interlayer insulating layers.

10. The semiconductor device according to claim 9, wherein The first interlayer insulating layer and the second interlayer insulating layer protrude further in a direction toward the channel layer than the even-numbered conductive layers and the odd-numbered conductive layers, and The blocking insulating layer, the charge trap layer, and the tunnel insulating layer are interposed in a space between the protruding first and second interlayer insulating layers.

11. The semiconductor device according to claim 9, wherein The charge trap layers interposed between side walls of each of the even-numbered conductive layers and the odd-numbered conductive layers are spaced apart from each other by the first interlayer insulating layer and the second interlayer insulating layer.

12. A method for manufacturing a semiconductor device, the method comprising the steps of: Forming a stacked structure by alternately stacking a first material layer and a multilayer stack, wherein each of the multilayer stacks includes a second material layer, a third material layer, and another second material layer stacked in sequence; forming a vertical hole at least partially through the stacked structure; forming a first recessed region by etching the sidewall of the second material layer exposed by the vertical hole to a specific depth; forming a blocking insulating layer by oxidizing the sidewalls of the second material layer exposed by the first recessed region; forming a charge trapping layer in each of the first recessed regions, wherein the charge trapping layers are spaced apart from each other in a vertical direction by the first material layer and the third material layer; forming a second recessed region by etching the sidewall of the charge trap layer exposed by the vertical hole to a specific depth; forming a tunnel insulating layer in each of the second recessed regions; and A channel layer is formed along the sidewalls of the vertical hole.

13. The method according to claim 12, wherein: The step of forming the blocking insulating layer includes the following steps: performing a radical oxidation process or a wet oxidation process to oxidize the sidewall of the second material layer to a specific depth to form the blocking insulating layer.

14. The method according to claim 12, further comprising the steps of: After forming the channel layer, the second material layer is replaced with a conductive layer.

15. A method of operating a semiconductor device, the method comprising the steps of: Providing a memory cell array including a first memory group, a first interlayer insulating layer, and a second memory group stacked in a vertical direction, wherein each of the first memory group and the second memory group includes an even-numbered memory cell, a second interlayer insulating layer, and an odd-numbered memory cell stacked in the vertical direction, and a thickness of any one of the first interlayer insulating layers is greater than a thickness of any one of the second interlayer insulating layers; programming the even-numbered memory cells of the first memory group using a first programming method; and programming the odd memory cells of the first memory group using a second programming method, The first programming method is a programming method with relatively higher storage bits than the second programming method.

16. The method according to claim 15, wherein: The first programming method is a quad level cell (QLC) method, and the second programming method is a triple level cell (TLC) method.

17. The method according to claim 15, further comprising the steps of: After programming the odd memory cells of the first memory group, the even memory cells of the second memory group are programmed in the first programming method and the odd memory cells of the second memory group are programmed in the second programming method.

18. The method according to claim 15, wherein: The programming operation of the even memory cells of the first memory group applies a programming voltage to the even word lines corresponding to the even memory cells of the first memory group, applies a first pass voltage to the odd word lines corresponding to the odd memory cells of the first memory group, and applies a second pass voltage higher than the first pass voltage to the remaining word lines corresponding to the even memory cells and the odd memory cells of the second memory group.

19. The method according to claim 15, wherein: The programming operation of the odd memory cells of the second memory group applies a programming voltage to the odd word lines corresponding to the odd memory cells of the first memory group, applies a first pass voltage to the even word lines corresponding to the even memory cells of the first memory group, and applies a second pass voltage higher than the first pass voltage to the remaining word lines corresponding to the even memory cells and the odd memory cells of the second memory group.

20. A method of operating a semiconductor device, the method comprising the steps of: Providing a memory cell array including a first memory group, a first interlayer insulating layer, and a second memory group stacked in a vertical direction, wherein each of the first memory group and the second memory group includes an even-numbered memory cell, a second interlayer insulating layer, and an odd-numbered memory cell stacked in the vertical direction, and a thickness of any one of the first interlayer insulating layers is greater than a thickness of any one of the second interlayer insulating layers; reading the even-numbered memory cells of the first memory group; and reading the odd memory cells of the first memory group, The step of reading the even-numbered memory cells of the first memory group comprises the following steps: applying a read voltage to the even-numbered memory cells of the first memory group; applying a first pass voltage to the odd-numbered memory cells of the first memory group; and A second pass voltage higher than the first pass voltage is applied to the even-numbered memory cells and the odd-numbered memory cells of the second memory group.

21. The method according to claim 20, wherein: The step of reading the odd memory cells of the first memory group comprises the following steps: applying the read voltage to the odd-numbered memory cells of the first memory group; applying the first pass voltage to the even-numbered memory cells of the first memory group; and The second pass voltage is applied to the even-numbered memory cells and the odd-numbered memory cells of the second memory group.

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