Semiconductor device

Abstract

A semiconductor device includes: a substrate including a cell region and a peripheral region; a first lower insulating layer disposed on the cell region and extending onto the peripheral region; a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region; a data storage pattern disposed on the second lower insulating layer on the cell region; a cell insulating layer disposed on the second lower insulating layer on the cell region and covering the data storage pattern; and a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region and including a different material from the unit insulating layer. A thickness of the second lower insulating layer on the peripheral region is smaller than a maximum thickness of the second lower insulating layer on the cell region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0130259 filed in the Korean Intellectual Property Office on September 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various example embodiments relate to a semiconductor device and / or a method of manufacturing the same, and more particularly, to a semiconductor device including a magnetic tunnel junction and / or a method of manufacturing the same. Background Art

[0004] With the high speed and / or low power consumption of electronic devices, the requirements or expectations for the high speed and / or low operating voltage of semiconductor devices incorporated into electronic devices are increasing. In order to meet or at least partially meet these expectations, magnetic storage devices have been proposed as semiconductor storage devices. Since magnetic storage devices can exhibit characteristics such as high-speed operation and / or non-volatility, they are attracting attention as next-generation semiconductor devices.

[0005] Generally, a magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The MTJ pattern may include two magnetic materials and an insulating layer therebetween. The resistance of the MTJ pattern may vary depending on the magnetization directions of the two magnetic materials. For example, when the magnetization directions of the two magnetic materials are antiparallel to each other, the MTJ pattern may have a low resistance. Data may be written / read using the resistance difference.

[0006] In accordance with various needs or desires of the electronics industry, various studies have been conducted on a semiconductor device having an embedded structure in which a magnetic tunnel junction pattern is provided between metal wirings. Summary of the invention

[0007] Some example embodiments may provide a semiconductor device and / or a method of manufacturing the same capable of reducing or minimizing defects caused by a manufacturing process.

[0008] Alternatively or additionally, some example embodiments may provide a semiconductor device having improved electrical characteristics and / or a method of manufacturing the same.

[0009] A semiconductor device according to some example embodiments may include: a substrate including a cell region and a peripheral region; a first lower insulating layer on the cell region and extending onto the peripheral region; a second lower insulating layer on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region; a data storage pattern on the second lower insulating layer on the cell region; a cell insulating layer on the second lower insulating layer on the cell region and covering the data storage pattern; and a peripheral insulating layer on the second lower insulating layer on the peripheral region and including a material different from a material in the cell insulating layer. A thickness of the second lower insulating layer on the peripheral region may be less than a maximum thickness of the second lower insulating layer on the cell region.

[0010] Alternatively or additionally, a semiconductor device according to some example embodiments may include: a substrate including a cell region and a peripheral region; a first lower insulating layer on the cell region and extending onto the peripheral region; a second lower insulating layer on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region; a data storage pattern on the second lower insulating layer on the cell region; a lower electrode contact on the cell region, passing through the first lower insulating layer and the second lower insulating layer, and connected to the data storage pattern, respectively; a cell insulating layer on the second lower insulating layer on the cell region and covering the data storage pattern; a peripheral insulating layer on the second lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer; and a peripheral conductive contact in the peripheral insulating layer and passing through the first lower insulating layer and the second lower insulating layer on the peripheral region. An upper surface of the second lower insulating layer on the peripheral region may be located at a lower height than an uppermost surface of the second lower insulating layer on the cell region. The peripheral insulating layer may contact a side surface of the cell insulating layer and an upper surface of the second lower insulating layer on the peripheral region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments described herein.

[0012] Figure 1 is a circuit diagram illustrating a unit memory cell of a semiconductor device according to some example embodiments.

[0013] Figure 2 is a plan view of a semiconductor device according to some example embodiments.

[0014] Figure 3 is along Figure 2 A cross-sectional view taken along line II′.

[0015] Figure 4A and Figure 4B are cross-sectional views respectively illustrating examples of magnetic tunnel junction patterns of semiconductor devices according to some example embodiments.

[0016] Figure 5 yes Figure 3 An enlarged view of portion "A".

[0017] Figures 6 to 11 is a view showing a method of manufacturing a semiconductor device according to some example embodiments, and is related to Figure 2 Cross-sectional view corresponding to line II′.

[0018] Fig.12 yes Fig.11 An enlarged view of portion "B" of FIG. DETAILED DESCRIPTION

[0019] Hereinafter, the inventive concept will be described in detail by explaining various exemplary embodiments with reference to the attached drawings.

[0020] Figure 1 is a circuit diagram illustrating a unit memory cell of a semiconductor device according to some example embodiments.

[0021] refer to Figure 1 , the unit memory cell MC may include a storage element ME and a selection element SE. The storage element ME and the selection element SE may be electrically connected to each other in series. The storage element ME may be connected between a column line or a bit line BL and the selection element SE. The selection element SE may be connected between the storage element ME and the source line SL and may be controlled by a row line or a word line WL. In some example embodiments, the source line SL and the bit line BL may be orthogonal to each other; however, the example embodiments are not limited thereto. The selection element SE may be or may include, for example, a bipolar transistor and / or a MOS field effect transistor. In some example embodiments, the selection element SE may be an NMOS transistor; however, the example embodiments are not limited thereto.

[0022] The storage element ME may be or may include a magnetic tunnel junction pattern MTJ, which includes magnetic patterns MP1 and MP2 spaced apart from each other and a tunnel barrier pattern TBP located between the magnetic patterns MP1 and MP2. One of the magnetic patterns MP1 and MP2 may be or may correspond to a reference magnetic pattern having a magnetization direction fixed in one direction regardless of an external magnetic field under a normal use environment. The other of the magnetic patterns MP1 and MP2 may be or may correspond to a free magnetic pattern in which the magnetization direction is changed between two stable magnetization directions by an external magnetic field. When the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel to each other, the resistance of the magnetic tunnel junction pattern MTJ may be much higher, for example, several orders of magnitude higher, than when the magnetization directions are parallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ may be adjusted by changing the magnetization direction of the free magnetic pattern. Therefore, the storage element ME may store data in a unit memory cell MC using a resistance difference depending on the magnetization directions of the reference magnetic pattern and the free magnetic pattern.

[0023] Figure 2 is a plan view of a semiconductor device according to some example embodiments. Figure 3 is along Figure 2 A cross-sectional view taken along line II′. Figure 4A and Figure 4B are cross-sectional views respectively illustrating examples of magnetic tunnel junction patterns of semiconductor devices according to some example embodiments. Figure 5 yes Figure 3 An enlarged view of portion "A".

[0024] refer to Figure 2 and Figure 3 , a substrate 100 including a cell region CR, a peripheral region PR, and a boundary region BR therebetween may be provided. The substrate 100 may be or may include a semiconductor substrate containing one or more of silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), etc., or may be composed of one or more of them. The cell region CR may be or may correspond to a region of the substrate 100 provided with Figure 1 The peripheral region PR may be or may correspond to another region of the substrate 100 where a peripheral circuit for driving and / or reading the memory cells MC is disposed. The boundary region BR may be another region of the substrate 100 disposed between the cell region CR and the peripheral region PR.

[0025] Wiring structures 102 and 104 may be disposed on substrate 100. Wiring structures 102 and 104 may be disposed on cell regions CR and peripheral regions PR of substrate 100. Wiring structures 102 and 104 may include wiring lines 102 vertically spaced apart from substrate 100 and wiring contacts 104 connected to wiring lines 102. Wiring lines 102 may be spaced apart from the upper surface 100U of substrate 100 in a direction perpendicular to the upper surface 100U of substrate 100. Wiring contacts 104 may be disposed between substrate 100 and wiring lines 102. Each wiring line 102 may be electrically connected to substrate 100 by corresponding wiring contacts 104. Wiring lines 102 and wiring contacts 104 may include metal (e.g., copper). Although two layers are shown for wiring structures 102 and 104, respectively, example embodiments are not limited thereto. In some examples, wiring structures 102 and 104 may have line widths different from each other and / or spacings different from each other; however, example embodiments are not limited thereto.

[0026] Select the component SE (such as Figure 1 The wiring lines 102 may be arranged on the cell region CR of the substrate 100, and the peripheral transistors constituting the peripheral circuit (or included therein) may be arranged on the peripheral region PR of the substrate 100. For example, the selection element and the peripheral transistor may be or may include a field effect transistor, such as an NMOS and / or PMOS field effect transistor. Each wiring line 102 may be electrically connected to one (or more) terminals (e.g., source terminal, drain terminal, or gate terminal) of the corresponding selection element or to one (or more) terminals (e.g., source terminal, drain terminal, or gate terminal) of the corresponding peripheral transistor through the corresponding wiring contact 104.

[0027] The wiring insulation layer 110 may be disposed on the substrate 100 to cover the wiring structures 102 and 104. The wiring insulation layer 110 may be disposed on the cell region CR of the substrate 100, and may extend onto the boundary region BR and the peripheral region PR of the substrate 100. The wiring insulation layer 110 may expose the upper surface of the uppermost wiring line 102 among the wiring lines 102. For example, the upper surface of the wiring insulation layer 110 may be substantially coplanar with the upper surface of the uppermost wiring line 102. For example, the wiring insulation layer 110 may include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0028] The first lower insulating layer 120 may be disposed on the wiring insulating layer 110 and may cover the exposed upper surface of the uppermost wiring line 102. The first lower insulating layer 120 may be disposed on the wiring insulating layer 110 on the cell region CR, and may extend onto the wiring insulating layer 110 on the boundary region BR and the peripheral region PR. For example, the first lower insulating layer 120 may include one or more of silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a material that is the same as or different from that of the wiring insulating layer 110.

[0029] The second lower insulating layer 130 may be disposed on the first lower insulating layer 120. The second lower insulating layer 130 may be disposed on the first lower insulating layer 120 on the cell region CR, and may extend onto the first lower insulating layer 120 on the boundary region BR and the peripheral region PR. The first lower insulating layer 120 may be interposed between the wiring insulating layer 110 on the cell region CR, the boundary region BR, and the peripheral region PR, and the second lower insulating layer 130. For example, the second lower insulating layer 130 may include one or more of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0030] The second lower insulating layer 130 may include a material different from that of the first lower insulating layer 120 or a material different from any of the materials of the first lower insulating layer 120. In some example embodiments, the second lower insulating layer 130 and the first lower insulating layer 120 may not include any common material. As an example, the first lower insulating layer 120 may include silicon nitride (e.g., SiCN), and the second lower insulating layer 130 may include silicon oxide (e.g., tetraethoxysilane (TEOS)). In some examples, the first lower insulating layer 120 may not include silicon oxide, and / or the second lower insulating layer 130 may not include silicon nitride.

[0031] The data storage patterns DS may be disposed on the second lower insulating layer 130 on the cell region CR. The data storage patterns DS may be spaced apart from each other in first and second directions D1 and D2 that are parallel to the upper surface 100U of the substrate 100 and intersect each other.

[0032] The second lower insulating layer 130 on the cell region CR has a recessed upper surface 130RU that is recessed toward the substrate 100 between the data storage patterns DS. The recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR may be located at a height lower than an uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR. As described herein, the height is a distance measured from the upper surface 100U of the substrate 100 in a third direction D3 perpendicular to the upper surface 100U of the substrate 100.

[0033] The upper surface 130U2 of the second lower insulation layer 130 on the peripheral region PR may be located at a lower height than the uppermost surface 130U1 of the second lower insulation layer 130 on the cell region CR. According to some example embodiments, the upper surface 130U2 of the second lower insulation layer 130 on the peripheral region PR may be located at a lower height than the recessed upper surface 130RU of the second lower insulation layer 130 on the cell region CR. Alternatively, according to some example embodiments, the upper surface 130U2 of the second lower insulation layer 130 on the peripheral region PR may be located at the same height as the recessed upper surface 130RU of the second lower insulation layer 130 on the cell region CR. Alternatively, according to some example embodiments, the upper surface 130U2 of the second lower insulation layer 130 on the peripheral region PR may be located at a higher height than the recessed upper surface 130RU of the second lower insulation layer 130 on the cell region CR.

[0034] The second lower insulating layer 130 on the boundary region BR may have a recessed upper surface 130RUa recessed toward the substrate 100. The recessed upper surface 130RUa of the second lower insulating layer 130 on the boundary region BR may be located at a height lower than the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR. According to some example embodiments, the recessed upper surface 130RUa of the second lower insulating layer 130 on the boundary region BR may be located at a height lower than the recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR, and may be located at a height lower than the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR.

[0035] The thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be less than the maximum thickness 130T1 of the second lower insulating layer 130 on the cell region CR (e.g., 130T1>130T2). The thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be measured from the lower surface 130L of the second lower insulating layer 130 to the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR in the third direction D3. The maximum thickness 130T1 of the second lower insulating layer 130 on the cell region CR may be measured from the lower surface 130L of the second lower insulating layer 130 to the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR in the third direction D3. For example, the thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be measured from the lower surface 130L of the second lower insulating layer 130 to the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR. to (3nm to 35nm), and preferably, can be to (5nm to 25nm) range.

[0036] The lower electrode contacts 140 may be disposed in the second lower insulating layer 130 on the cell region CR and may be spaced apart from each other in the first direction D1 and the second direction D2. The lower electrode contacts 140 may be disposed under the data storage patterns DS, respectively, and may be electrically connected to the data storage patterns DS, respectively. Each lower electrode contact 140 may pass through the first lower insulating layer 120 and the second lower insulating layer 130 on the cell region CR and may be connected to the corresponding uppermost wiring line 102. Each data storage pattern DS may be electrically connected to one terminal or at least one terminal (e.g., a drain terminal) of the corresponding selection element through each lower electrode contact 140 and the corresponding uppermost wiring line 102.

[0037] The upper surface 140U of the lower electrode contact 140 may be located at a height higher than the recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR. The upper surface 140U of the lower electrode contact 140 may be located at the same height as the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR. The recessed upper surface 130RUa of the second lower insulating layer 130 on the boundary region BR and the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR may be located at a lower height than the upper surface 140U of the lower electrode contact 140.

[0038] The lower electrode contact 140 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium and / or tantalum), a metal-semiconductor compound (e.g., metal silicide), and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride).

[0039] Each data storage pattern DS may include a lower electrode BE, a magnetic tunnel junction pattern MTJ, and an upper electrode TE sequentially stacked on the second lower insulating layer 130 along the third direction D3. The magnetic tunnel junction pattern MTJ may be disposed between the lower electrode BE and the upper electrode TE. Each lower electrode contact 140 may be connected to the lower electrode BE of each data storage pattern DS. The lower electrode BE of each data storage pattern DS may contact the upper surface 140U of each lower electrode contact 140 and the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR.

[0040] The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP therebetween. The first magnetic pattern MP1 may be disposed between the lower electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the upper electrode TE and the tunnel barrier pattern TBP. For example, the lower electrode BE may include a conductive metal nitride (e.g., titanium nitride and / or tantalum nitride). The upper electrode TE may include at least one of a metal (e.g., one or more of Ta, W, Ru, Ir, etc.) and a conductive metal nitride (e.g., TiN and / or TaN).

[0041] refer to Figure 4A and Figure 4B In some example embodiments, the first magnetic pattern MP1 may be or correspond to a reference layer having a magnetization direction MD1 fixed in one direction, and the second magnetic pattern MP2 may be or correspond to a free layer having a magnetization direction MD2 changeable to be parallel or anti-parallel to the magnetization direction MD1 of the first magnetic pattern MP1. Figure 4A and Figure 4B , and , all show the case where the second magnetic pattern MP2 is a free layer as an example, but the concept of the present disclosure is not limited thereto. Figure 4A and Figure 4B Differently, alternatively or additionally, the first magnetic pattern MP1 may be or correspond to a free layer, and the second magnetic pattern MP2 may be or correspond to a reference layer.

[0042] refer to Figure 4A, the magnetization directions MD1 and MD2 of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be perpendicular to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include at least one of an intrinsic vertical magnetic material and an extrinsic vertical magnetic material. The intrinsic vertical magnetic material may include a material having a vertical magnetization property even in the absence of external factors (e.g., no external electric field or magnetic field). The intrinsic vertical magnetic material may include at least one of the following items: i) a vertical magnetic material (e.g., CoFeTb, CoFeGd, CoFeDy); ii) a vertical magnetic material having an L10 structure; iii) CoPt having a hexagonal close-packed lattice structure; and iv) a vertical magnetic structure. The vertical magnetic material having an L10 structure may include at least one of FePt with an L10 structure, FePd with an L10 structure, CoPd with an L10 structure, or CoPt with an L10 structure. The vertical magnetic structure may include alternating and repeatedly stacked magnetic layers and non-magnetic layers. For example, the vertical magnetic structure may include at least one of (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, or (CoCr / Pd)n ("n" is the number of stacks). The extrinsic vertical magnetic material may include a material having an intrinsic horizontal magnetization property and a vertical magnetization property due to external factors. For example, the extrinsic vertical magnetic material may have a vertical magnetization property due to magnetic anisotropy caused by forming a junction of the first magnetic pattern MP1 (or the second magnetic pattern MP2) and the tunnel barrier pattern TBP. The extrinsic vertical magnetic material may include, for example, CoFeB.

[0043] refer to Figure 4B As another example, the magnetization directions MD1 and MD2 of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be parallel to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a ferromagnetic substance. The first magnetic pattern MP1 may also include an antiferromagnetic substance for fixing the magnetization direction of the ferromagnetic substance in the first magnetic pattern MP1.

[0044] Each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a cobalt-based Heusler alloy. The tunnel barrier pattern TBP may include at least one of a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (Mg-Zn) oxide layer, or a magnesium-boron (Mg-B) oxide layer.

[0045] Reference again Figure 2 and Figure 3 , the capping insulating layer 150 may be disposed on the second lower insulating layer 130 on the cell region CR. The capping insulating layer 150 may conformally cover the side surface of each data storage pattern DS on the cell region CR and the recessed upper surface 130RU of the second lower insulating layer 130. When viewed in a plan view, the capping insulating layer 150 may surround the side surface of each data storage pattern DS. The capping insulating layer 150 may extend onto the second lower insulating layer 130 on the boundary region BR and may conformally cover the recessed upper surface 130RUa of the second lower insulating layer 130 on the boundary region BR.

[0046] The capping insulating layer 150 may conformally cover the side surfaces of the lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE. When viewed in a plan view, the capping insulating layer 150 may surround the side surfaces of the lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE. The capping insulating layer 150 may include a nitride (e.g., silicon nitride). The capping insulating layer 150 may have a flat upper surface; however, example embodiments are not limited thereto.

[0047] The cell insulating layer 160 may be disposed on the second lower insulating layer 130 on the cell region CR and may cover the data storage pattern DS. The cell insulating layer 160 may fill the space between the data storage patterns DS. The capping insulating layer 150 may be interposed between the side surface of each data storage pattern DS and the cell insulating layer 160, and may extend between the recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR and the cell insulating layer 160. The cell insulating layer 160 may extend onto the second lower insulating layer 130 on the boundary region BR. The capping insulating layer 150 may extend between the cell insulating layer 160 and the recessed upper surface 130RUa of the second lower insulating layer 130 on the boundary region BR. For example, the cell insulating layer 160 may include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0048] The upper insulating layer 170 may be disposed on the cell insulating layer 160 on the cell region CR. The upper insulating layer 170 may extend onto the cell insulating layer 160 on the boundary region BR. The upper insulating layer 170 may include a material different from that of the cell insulating layer 160. As an example, the cell insulating layer 160 may include silicon oxide, and the upper insulating layer 170 may include silicon nitride (e.g., SiCN and / or SiN). The cell insulating layer 160 may include the same or different material as the capping insulating layer 150, and may or may not have the same thickness as the capping insulating layer 150.

[0049] The peripheral insulating layer 180 may be disposed on the second lower insulating layer 130 on the peripheral region PR. The peripheral insulating layer 180 may be in contact with the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR. The peripheral insulating layer 180 may be in contact with the side surface 160S of the unit insulating layer 160 and the side surface 170S of the upper insulating layer 170. The peripheral insulating layer 180 may be in contact with the side surface 150S of the cover insulating layer 150.

[0050] An upper surface 180U of the peripheral insulating layer 180 may be located at the same height as an upper surface 170U of the upper insulating layer 170 . An upper surface 180U of the peripheral insulating layer 180 may be coplanar with an upper surface 170U of the upper insulating layer 170 .

[0051] The peripheral insulating layer 180 may include a material different from that of the unit insulating layer 160. The peripheral insulating layer 180 may include an insulating material having a dielectric constant (k) lower than that of the unit insulating layer 160. The peripheral insulating layer 180 may include a material different from that of the upper insulating layer 170, and may include an insulating material having a dielectric constant (k) lower than that of the upper insulating layer 170. The peripheral insulating layer 180 may include a material different from that of the second lower insulating layer 130 or a material different from any of the materials of the second lower insulating layer 130. For example, there may be no common material between the peripheral insulating layer 180 and the second lower insulating layer 130. For example, the peripheral insulating layer 180 may include silicon oxide, silicon nitride, and / or silicon oxynitride. As an example, the peripheral insulating layer 180 may include an insulating material having a dielectric constant (k) of about 2.5 or less than 2.0, such as porous SiOC.

[0052] The first unit conductive line 192 may be disposed on the unit region CR. The first unit conductive line 192 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. Each first unit conductive line 192 may have a line shape extending in the second direction D2. Each first unit conductive line 192 may be electrically connected to a corresponding data storage pattern spaced apart from each other in the second direction D2 among the data storage patterns DS, respectively. The data storage patterns DS spaced apart from each other in the first direction D1 among the data storage patterns DS may be electrically connected to the first unit conductive line 192, respectively.

[0053] Each first unit conductive line 192 may pass through the upper insulating layer 170 and may pass through the upper portion of the unit insulating layer 160 to be connected to the corresponding data storage pattern DS. A lower surface 192L of each first unit conductive line 192 may contact the upper electrode TE of the corresponding data storage pattern DS. An upper surface 192U of the first unit conductive line 192 may be located at the same height as the upper surface 170U of the upper insulating layer 170 and may be coplanar with the upper surface 170U of the upper insulating layer 170. The first unit conductive line 192 may include a conductive material, such as a metal (e.g., copper).

[0054] The peripheral wire 210 may be disposed on the second lower insulating layer 130 on the peripheral region PR and in the peripheral insulating layer 180. The peripheral insulating layer 180 may cover the peripheral wire 210. An upper surface 210U of the peripheral wire 210 may be exposed without being covered by the peripheral insulating layer 180. The upper surface 210U of the peripheral wire 210 may be located at the same height as the upper surface 180U of the peripheral insulating layer 180 and may be coplanar with the upper surface 180U of the peripheral insulating layer 180. The upper surface 210U of the peripheral wire 210, the upper surface 180U of the peripheral insulating layer 180, the upper surface 192U of the first unit wire 192, and the upper surface 170U of the upper insulating layer 170 may be located at the same height and may be coplanar with each other.

[0055] The peripheral conductive contact 220 may be disposed on the peripheral region PR and below the peripheral wire 210. The peripheral conductive contact 220 may be electrically connected to the peripheral wire 210. Each peripheral conductive contact 220 may contact a corresponding peripheral wire 210 in the peripheral wire 210 without an interface therebetween; for example, each peripheral conductive contact 220 may be formed or filled simultaneously with the peripheral wire 210 (e.g., using a damascene process). Each peripheral conductive contact 220 and the corresponding peripheral wire 210 may be connected to each other to form an integral unit. Each peripheral conductive contact 220 may pass through the lower portion of the peripheral insulating layer 180. Each peripheral conductive contact 220 may pass through the second lower insulating layer 130 and the first lower insulating layer 120 on the peripheral region PR, and may be electrically connected to the corresponding uppermost wiring line 102. Each peripheral wire 210 may be electrically connected to one (or at least one) terminal (e.g., source terminal, drain terminal, or gate terminal) of the corresponding peripheral transistor through the corresponding peripheral conductive contact 220 and the corresponding uppermost wiring line 102.

[0056] refer to Figure 5, each peripheral conductive contact 220 may include a first portion 220P1 in the first lower insulating layer 120, a second portion 220P2 in the second lower insulating layer 130, and a third portion 220P3 in the peripheral insulating layer 180. Each peripheral conductive contact 220 may have a width in a direction parallel to the upper surface 100U of the substrate 100. The first width W1 of the first portion 220P1 may be smaller than the third width W3 of the third portion 220P3, and the second width W2 of the second portion 220P2 may decrease as the second portion 220P2 is farther away from the third portion 220P3 in a direction perpendicular to the upper surface 100U of the substrate 100 and as the second portion 220P2 is closer to the first portion 220P1. The side surface of the first portion 220P1 may be linear or curved and may be inclined at a first angle θ1 relative to the lower surface 120L of the first lower insulating layer 120, and the side surface of the second portion 220P2 may be linear or curved and may be inclined at a second angle θ2 relative to the lower surface 130L of the second lower insulating layer 130. The second angle θ2 may be different from the first angle θ1. The side surface of the third portion 220P3 may be linear or curved and may be inclined at a third angle θ3 relative to the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR. The second angle θ2 may be different from the third angle θ3. As an example, each of the first angle θ1 and the third angle θ3 may be less than or equal to 90°, and the second angle θ2 may be less than the first angle θ1 and the third angle θ3.

[0057] Reference again Figure 2 and Figure 3 , the peripheral wire 210 and the peripheral conductive contact 220 may include a conductive material, such as a metal (e.g., copper). The first unit wire 192, the peripheral wire 210, and the peripheral conductive contact 220 may include the same material. In some example embodiments, the first unit wire 192, the peripheral wire 210, and the peripheral conductive contact 220 may be formed simultaneously, for example, using a damascene process; however, example embodiments are not limited thereto.

[0058] The upper interlayer insulating layer 200 may be disposed on the cell region CR, the boundary region BR, and the peripheral region PR, and may cover an upper surface 170U of the upper insulating layer 170, an upper surface 192U of the first cell conductive line 192, an upper surface 180U of the peripheral insulating layer 180, and an upper surface 210U of the peripheral conductive line 210. For example, the upper interlayer insulating layer 200 may include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0059] The second unit conductor 196 may be disposed in the upper interlayer insulating layer 200 on the cell region CR. The second unit conductors 196 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. Each second unit conductor 196 may overlap vertically (e.g., in the third direction D3) with each first unit conductor 192. The conductive contact 194 may be disposed in the upper interlayer insulating layer 200 on the cell region CR and may be disposed between the first unit conductor 192 and the second unit conductor 196. Each first unit conductor 192 may be electrically connected to each second unit conductor 196 through a corresponding conductive contact 194 in the conductive contact 194. Each first unit conductor 192, the corresponding conductive contact 194, and each second unit conductor 196 may constitute a bit line 190 ( Figure 1 bit line BL) or is included in bit line 190 ( Figure 1 The conductive contact 194 and the second unit conductive line 196 may include a conductive material, such as metal (eg, copper).

[0060] According to various example embodiments, on the peripheral region PR, the second lower insulating layer 130 may be interposed between the first lower insulating layer 120 and the peripheral insulating layer 180. In this case, the possibility of the first lower insulating layer 120 being recessed during an etching process performed before forming the peripheral insulating layer 180 and / or being affected by the recess may be prevented or reduced, and thus, the upper surface of the uppermost wiring line 102 may be prevented or reduced from being recessed.

[0061] The upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR may be located at a height lower than the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR, and the thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be less than the maximum thickness 130T1 of the second lower insulating layer 130 on the cell region CR. The thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be to When the thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR is less than When the thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR is greater than When the thickness of the semiconductor device is less than 35 nm, parasitic capacitance between the peripheral conductive contacts 220 and / or between the peripheral conductive lines 210 may increase, and thus, electrical characteristics of the semiconductor device may be degraded.

[0062] Alternatively or additionally, each peripheral conductive contact 220 may include a first portion 220P1 in the first lower insulating layer 120, a second portion 220P2 in the second lower insulating layer 130, and a third portion 220P3 in the peripheral insulating layer 180. The second lower insulating layer 130 may include a material different from the first lower insulating layer 120 and the peripheral insulating layer 180, and thus, each peripheral conductive contact 220 may be formed to have a width W2 that decreases as the second portion 220P2 is farther away from the third portion 220P3 and closer to the first portion 220P1. As a result, the width W1 of the first portion 220P1 may be smaller than the width W3 of the third portion 220P3. When the thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR is greater than (35 nm), the width W1 of the first portion 220P1 may decrease, and as a result, the resistance of each peripheral conductive contact 220 may increase. Therefore, the electrical characteristics of the semiconductor device may be deteriorated.

[0063] Therefore, on the peripheral region PR, the second lower insulating layer 130 may be interposed between the first lower insulating layer 120 and the peripheral insulating layer 180 and may have a desired thickness 130T2, thereby providing a semiconductor device capable of minimizing or reducing process-related defects and / or having improved electrical characteristics.

[0064] Figures 6 to 11 is a view showing a method of manufacturing a semiconductor device according to some example embodiments, and is related to Figure 2 A cross-sectional view corresponding to line II'. Fig.12 yes Fig.11 In order to simplify the description, the reference Figures 1 to 3 , Figure 4A , Figure 4B and Figure 5 The description of the semiconductor device is repeated.

[0065] refer to Figure 2 and Figure 6 A substrate 100 including a cell region CR, a peripheral region PR, and a boundary region BR therebetween may be provided. A selection element SE ( Figure 1The wiring structures 102 and 104 may include wiring lines 102 spaced apart vertically (e.g., in the third direction D3) from the substrate 100 and wiring contacts 104 connected to the wiring lines 102. Each wiring line 102 may be electrically connected to one or more terminals (e.g., source terminal, drain terminal, or gate terminal) of a corresponding selection element or to one or more terminals (e.g., source terminal, drain terminal, or gate terminal) of a corresponding peripheral transistor through a corresponding wiring contact 104.

[0066] A wiring insulation layer 110 may be formed on the substrate 100, and the wiring insulation layer 110 covers the wiring structures 102 and 104. The wiring insulation layer 110 may expose the upper surface of the uppermost wiring line 102 in the wiring lines 102. The wiring insulation layer 110 may be formed using one or more processes such as a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure CVD (LPCVD) process, or an atomic layer deposition (ALD) process; however, example embodiments are not limited thereto. In some cases, the wiring insulation layer 110 may be planarized, for example, using a chemical mechanical planarization (CMP) process and / or an etch-back process; however, example embodiments are not limited thereto.

[0067] A first lower insulating layer 120 may be formed on the wiring insulating layer 110, and the first lower insulating layer 120 may cover the exposed upper surface of the uppermost wiring line 102. The first lower insulating layer 120 may be formed on the wiring insulating layer 110 on the cell region CR, and may extend onto the wiring insulating layer 110 on the boundary region BR and the peripheral region PR. The first lower insulating layer 120 may be formed using one or more of a PECVD process, an LPCVD process, or an ALD process; however, example embodiments are not limited thereto. In some cases, the first lower insulating layer 120 may be planarized, for example, using a CMP process and / or an etch-back process; however, example embodiments are not limited thereto.

[0068] The second lower insulating layer 130 may be formed on the first lower insulating layer 120. The second lower insulating layer 130 may be formed on the first lower insulating layer 120 on the cell region CR, and may extend onto the first lower insulating layer 120 on the boundary region BR and the peripheral region PR. The second lower insulating layer 130 may be formed using one or more of a PECVD process, an LPCVD process, or an ALD process; however, example embodiments are not limited thereto. In some cases, the second lower insulating layer 130 may be planarized, for example, using a CMP process and / or an etch-back process; however, example embodiments are not limited thereto.

[0069] The lower electrode contacts 140 may be formed in the second lower insulating layer 130 on the cell region CR. Each of the lower electrode contacts 140 may pass through the first lower insulating layer 120 and the second lower insulating layer 130 on the cell region CR, and may be electrically connected to one of the uppermost wiring lines 102. Forming the lower electrode contacts 140 may include, for example, forming a lower contact hole passing through the first lower insulating layer 120 and the second lower insulating layer 130 on the cell region CR, forming a lower contact layer on the second lower insulating layer 130 to fill the lower contact hole, and planarizing the lower contact layer until the upper surface of the second lower insulating layer 130 is exposed. The lower electrode contacts 140 may be locally formed in the lower contact holes, respectively, through a planarization process. The planarization process may include a CMP process and / or an etch-back process.

[0070] The lower electrode layer BEL and the magnetic tunnel junction layer MTJL may be sequentially deposited on the second lower insulating layer 130. The lower electrode layer BEL and the magnetic tunnel junction layer MTJL may be formed on the second lower insulating layer 130 on the cell region CR, and may extend to the second lower insulating layer 130 on the boundary region BR and the peripheral region PR. The magnetic tunnel junction layer MTJL may include a first magnetic layer ML1, a tunnel barrier layer TBL, and a second magnetic layer ML2 sequentially stacked on the lower electrode layer BEL. For example, the magnetic tunnel junction layer MTJL and the lower electrode layer BEL may be formed by one or more sputtering processes such as a physical vapor deposition process, a CVD process, or an ALD process.

[0071] A conductive mask pattern CM may be formed on the magnetic tunnel junction layer MTJL on the cell region CR. The conductive mask pattern CM may define a region in which a magnetic tunnel junction pattern MTJ to be described later will be formed. The conductive mask pattern CM may be spaced apart from each other in the first direction D1 and the second direction D2 on the magnetic tunnel junction layer MTJL, and may be formed of a metal (e.g., one or more of Ta, W, Ru, Ir, etc.) and a conductive metal nitride (e.g., TiN).

[0072] A blocking mask pattern BM may be formed on the magnetic tunnel junction layer MTJL on the peripheral region PR. The blocking mask pattern BM may cover the magnetic tunnel junction layer MTJL on the peripheral region PR and expose the magnetic tunnel junction layer MTJL on the boundary region BR. For example, the blocking mask pattern BM may include silicon nitride and / or metal nitride. The blocking mask pattern BM may be formed before, after, or simultaneously with the conductive mask pattern CM.

[0073] refer to Figure 2 and Figure 7, a first etching process may be performed using the conductive mask pattern CM as an etching mask to etch the magnetic tunnel junction layer MTJL and the lower electrode layer BEL. For example, the first etching process may be or may include an ion beam etching process using an ion beam. The ion beam may include inert ions, such as but not limited to inert gas ions. As the magnetic tunnel junction layer MTJL and the lower electrode layer BEL are etched, a magnetic tunnel junction pattern MTJ and a lower electrode BE may be formed, respectively.

[0074] Etching the magnetic tunnel junction layer MTJL may include sequentially etching the second magnetic layer ML2, the tunnel barrier layer TBL, and the first magnetic layer ML1. The second magnetic layer ML2, the tunnel barrier layer TBL, and the first magnetic layer ML1 may be etched to form a second magnetic pattern MP2, a tunnel barrier pattern TBP, and a first magnetic pattern MP1, respectively. The remaining portion of the conductive mask pattern CM remaining on the magnetic tunnel junction pattern MTJ after the first etching process may be referred to as an upper electrode TE. The lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE may be referred to as a data storage pattern DS. A plurality of data storage patterns DS may be formed on each lower electrode contact 140 and may be spaced apart from each other in the first direction D1 and the second direction D2.

[0075] Through the first etching process, the upper portion of the second lower insulating layer 130 between the plurality of data storage patterns DS may be recessed. Therefore, the second lower insulating layer 130 on the cell region CR may have a recessed upper surface 130RU recessed toward the substrate 100. The recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR may be located at a lower height than the upper surface 140U of the lower electrode contact 140, and may be located at a lower height than the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR.

[0076] The blocking mask pattern BM may be removed during the first etching process, and the magnetic tunnel junction layer MTJL and the lower electrode layer BEL on the boundary region BR and the peripheral region PR may also be removed during the first etching process. In addition, the upper portion of the second lower insulating layer 130 on the boundary region BR and the peripheral region PR may be recessed by the first etching process.

[0077] The upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR may be located at a lower height than the uppermost surface 130U1 of the second lower insulating layer 130 on the cell region CR. As the thickness of the blocking mask pattern BM (e.g., the thickness in the third direction D3) is adjusted, the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR may be controlled to be located at a higher height or a lower height than the recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR, and the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR may be controlled to be located at the same height as the recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR.

[0078] The thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be less than the maximum thickness 130T1 of the second lower insulating layer 130 on the cell region CR (e.g., 130T1>130T2). As the thickness of the blocking mask pattern BM (e.g., the thickness in the third direction D3) is adjusted, the thickness 130T2 of the second lower insulating layer 130 on the peripheral region PR may be controlled to be (3nm) to (35nm) range.

[0079] The recessed upper surface 130RUa of the second lower insulation layer 130 on the boundary region BR may be located at a height lower than the uppermost surface 130U1 of the second lower insulation layer 130 on the cell region CR. The blocking mask pattern BM may not be provided on the boundary region BR, and thus the recessed upper surface 130RUa of the second lower insulation layer 130 on the boundary region BR may be located at a height lower than the recessed upper surface 130RU of the second lower insulation layer 130 on the cell region CR and the upper surface 130U2 of the second lower insulation layer 130 on the peripheral region PR.

[0080] refer to Figure 2 and Figure 8 , a cover insulating layer 150 may be formed on the second lower insulating layer 130 on the cell region CR, and the cover insulating layer 150 may conformally cover the upper surface and the side surface of each data storage pattern DS. The cover insulating layer 150 may conformally cover the recessed upper surface 130RU of the second lower insulating layer 130 on the cell region CR. The cover insulating layer 150 may extend onto the second lower insulating layer 130 on the boundary region BR, and may conformally cover the recessed upper surface 130RUa of the second lower insulating layer 130 on the boundary region BR. The cover insulating layer 150 may extend onto the second lower insulating layer 130 on the peripheral region PR, and may cover the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR.

[0081] A cell insulating layer 160 may be formed on the capping insulating layer 150. The cell insulating layer 160 may be formed on the capping insulating layer 150 on the cell region CR to cover the data storage pattern DS and fill the space between the data storage patterns DS. The cell insulating layer 160 may extend onto the capping insulating layer 150 on the boundary region BR and the peripheral region PR. For example, the cell insulating layer 160 may be formed using a high density plasma chemical vapor deposition (HDP CVD) process.

[0082] An upper insulating layer 170 may be formed on the cell insulating layer 160. The upper insulating layer 170 may be formed on the cell insulating layer 160 on the cell region CR, and may extend onto the cell insulating layer 160 on the boundary region BR and the peripheral region PR.

[0083] refer to Figure 2 and Fig. 9 , a peripheral opening OP may be formed on the peripheral region PR, and the peripheral opening OP may expose the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR. The peripheral opening OP may expose the side surface 170S of the upper insulating layer 170, the side surface 160S of the cell insulating layer 160, and the side surface 150S of the cover insulating layer 150 on the boundary region BR.

[0084] Forming the peripheral opening OP may include performing a second etching process to remove the upper insulating layer 170, the unit insulating layer 160, and the cover insulating layer 150 on the peripheral region PR. For example, forming the peripheral opening OP may include forming a unit mask pattern on the upper insulating layer 170 on the unit region CR, and performing the second etching process using the unit mask pattern as an etching mask. For example, the unit mask pattern may be a photoresist pattern. As the upper insulating layer 170, the unit insulating layer 160, and the cover insulating layer 150 on the peripheral region PR are removed by the second etching process, the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR may be exposed, and the side surface 170S of the upper insulating layer 170, the side surface 160S of the unit insulating layer 160, and the side surface 150S of the cover insulating layer 150 may be exposed.

[0085] When the second lower insulating layer 130 on the peripheral region PR is over-etched during the second etching process, the first lower insulating layer 120 on the peripheral region PR may be recessed by the second etching process, and in addition, the upper surface of the uppermost wiring line 102 on the peripheral region PR may also be recessed by the second etching process. Therefore, a defect may occur in the uppermost wiring line 102.

[0086] However, according to various example embodiments, the second lower insulating layer 130 on the peripheral region PR may be controlled to have a required or desired thickness 132T2 using the blocking mask pattern BM. Therefore, the first lower insulating layer 120 and the uppermost wiring line 102 on the peripheral region PR may be prevented from being recessed by the second etching process or the possibility of being recessed may be reduced.

[0087] refer to Figure 2 and Fig.10 , a peripheral insulating layer 180 may be formed to fill the peripheral opening OP. The peripheral insulating layer 180 may be in contact with the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR, and may be in contact with the side surface 150S of the cover insulating layer 150, the side surface 160S of the unit insulating layer 160, and the side surface 170S of the upper insulating layer 170 on the boundary region BR. Forming the peripheral insulating layer 180 may include, for example, forming an insulating layer filling the peripheral opening OP, and planarizing the insulating layer until the upper surface of the upper insulating layer 170 is exposed. The insulating layer may be formed using, for example, a chemical vapor deposition process. The planarization process may be performed using, for example, at least one of an etch-back process and a chemical mechanical polishing process.

[0088] refer to Figure 2 and Fig.11 , a first unit trench 192T may be formed on the cell region CR. The first unit trenches 192T may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. Each first unit trench 192T may have a line shape extending in the second direction D2, and may expose a corresponding data storage pattern DS spaced apart from each other in the second direction D2 among the data storage patterns DS. Each first unit trench 192T may pass through the upper insulating layer 170, and an upper portion of the unit insulating layer 160. Each first unit trench 192T may expose an upper electrode TE of each corresponding data storage pattern DS.

[0089] The peripheral trench 210T may be formed on the peripheral region PR and in the peripheral insulating layer 180. Each peripheral trench 210T may pass through an upper portion of the peripheral insulating layer 180. The peripheral hole 220H may extend from a bottom surface of the peripheral trench 210T toward the substrate 100. Each peripheral hole 220H may pass through a lower portion of the peripheral insulating layer 180, and may pass through the second lower insulating layer 130 and the first lower insulating layer 120 on the peripheral region PR. Each peripheral hole 220H may expose an upper surface of a corresponding one of the uppermost wiring lines 102.

[0090] refer to Fig.12, each peripheral hole 220H may include a first region 220H1 in the first lower insulating layer 120, a second region 220H2 in the second lower insulating layer 130, and a third region 220H3 in the peripheral insulating layer 180. Each peripheral hole 220H may have a width in a direction parallel to the upper surface 100U of the substrate 100. The first width W1 of the first region 220H1 may be smaller than the third width W3 of the third region 220H3, and the second width W2 of the second region 220H2 may decrease as the second region 220H2 is farther away from the third region 220H3 and closer to the first region 220H1 in a direction perpendicular to the upper surface 100U of the substrate 100. The inner surface of the first region 220H1 may be inclined at a first angle θ1 relative to the lower surface 120L of the first lower insulating layer 120, and the inner surface of the second region 220H2 may be inclined at a second angle θ2 relative to the lower surface 130L of the second lower insulating layer 130. The second angle θ2 may be different from the first angle θ1. The inner surface of the third region 220H3 may be inclined at a third angle θ3 relative to the upper surface 130U2 of the second lower insulating layer 130 on the peripheral region PR. The second angle θ2 may be different from the third angle θ3. As an example, each of the first angle θ1 and the third angle θ3 may be less than or equal to 90°, and the second angle θ2 may be less than the first angle θ1 and the third angle θ3.

[0091] The second lower insulating layer 130 may include a material different from the first lower insulating layer 120 and the peripheral insulating layer 180, and therefore, during the etching process for forming the peripheral hole 220H, the etching rate of the second lower insulating layer 130 may be different from the etching rates of the first lower insulating layer 120 and the peripheral insulating layer 180. Therefore, the width W2 of each second region 220H2 of the peripheral hole 220H may decrease as the second region 220H2 is farther away from the third region 220H3 and as the second region 220H2 is closer to the first region 220H1. In addition, the slope of the inner surface of the second region 220H2 may be different from the slope of the inner surface of the first region 220H1 and the slope of the inner surface of the third region 220H3.

[0092] Reference again Figure 2 and Figure 3, a first unit conductor 192 may be formed in each unit trench 192T. A peripheral conductor 210 may be formed in each peripheral trench 210T, and a peripheral conductive contact 220 may be formed in each peripheral hole 220H. Forming the first unit conductor 192, the peripheral conductor 210, and the peripheral conductive contact 220 may include, for example, forming a conductive layer on the upper insulating layer 170 and the peripheral insulating layer 180 to fill the unit trench 192T, the peripheral trench 210T, and the peripheral hole 220H, and planarizing the conductive layer until the upper surface 170U of the upper insulating layer 170 and the upper surface 180U of the peripheral insulating layer 180 are exposed. Through the planarization process, the upper surface 192U of the first unit conductor 192, the upper surface 170U of the upper insulating layer 170, the upper surface 180U of the peripheral insulating layer 180, and the upper surface 210U of the peripheral conductor 210 may be located at the same height as each other.

[0093] An upper interlayer insulating layer 200 may be formed on the cell region CR, the boundary region BR, and the peripheral region PR and may cover an upper surface 170U of the upper insulating layer 170 , an upper surface 192U of the first cell wire 192 , an upper surface 180U of the peripheral insulating layer 180 , and an upper surface 210U of the peripheral wire 210 .

[0094] The second unit conductive line 196 and the conductive contact 194 may be formed in the upper interlayer insulating layer 200. Forming the second unit conductive line 196 and the conductive contact 194 may include, for example, forming a second unit trench through an upper portion of the upper interlayer insulating layer 200, forming a contact hole through a lower portion of the upper interlayer insulating layer 200 from a bottom surface of each second unit trench, forming a conductive layer on the upper interlayer insulating layer 200 to fill the second unit trench and the contact hole, and planarizing the conductive layer until the upper surface of the upper interlayer insulating layer 200 is exposed.

[0095] According to various example embodiments, on the peripheral region, the second lower insulating layer may be interposed between the first lower insulating layer and the peripheral insulating layer and may have a desired thickness. Therefore, during the etching process performed before forming the peripheral insulating layer, the first lower insulating layer and the uppermost wiring line below the first lower insulating layer may be prevented from being recessed or the possibility of being recessed may be reduced. Alternatively or additionally, an increase in parasitic capacitance between the peripheral conductive contacts and / or the peripheral wires may be suppressed, and a reduction in resistance of the peripheral conductive contacts may be suppressed.

[0096] Therefore, a semiconductor device capable of minimizing or reducing defects during a manufacturing process and having improved electrical characteristics and a method of manufacturing the same can be provided.

[0097] Although various example embodiments are described above, it will be appreciated by those of ordinary skill in the art that many modifications and variations may be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. Therefore, the example embodiments should be considered in all respects to be illustrative and not restrictive, and the spirit and scope of the inventive concept is indicated by the appended claims. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

Claims

1. A semiconductor device, comprising: A substrate including a cell region and a peripheral region; a first lower insulating layer on the cell region and extending onto the peripheral region; a second lower insulating layer on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region; a data storage pattern on the second lower insulating layer on the cell region; a cell insulating layer on the second lower insulating layer on the cell region and covering the data storage pattern; as well as a peripheral insulating layer on the second lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer, Wherein, the thickness of the second lower insulating layer on the peripheral region is smaller than the maximum thickness of the second lower insulating layer on the cell region.

2. The semiconductor device according to claim 1, wherein A height of an upper surface of the second lower insulating layer on the peripheral region is lower than a height of an uppermost surface of the second lower insulating layer on the cell region.

3. The semiconductor device according to claim 2, wherein: The second lower insulating layer on the cell region has a recessed upper surface that is recessed toward the substrate and between the data storage patterns, and A height of the recessed upper surface of the second lower insulating layer on the cell region is lower than a height of the uppermost surface of the second lower insulating layer on the cell region.

4. The semiconductor device according to claim 3, further comprising: lower electrode contacts in the second lower insulating layer on the cell region and respectively connected to the data storing patterns, Wherein, the data storage patterns are respectively on the lower electrode contact members, and The uppermost surface of the second lower insulating layer on the cell region is at the same height as the upper surface of the lower electrode contact.

5. The semiconductor device according to claim 2, wherein: The peripheral insulating layer contacts an upper surface of the second lower insulating layer on the peripheral region.

6. The semiconductor device according to claim 5, wherein: The peripheral insulating layer includes an insulating material having a lower dielectric constant than that of the unit insulating layer.

7. The semiconductor device according to claim 5, further comprising: an upper insulating layer, on the unit insulating layer, The peripheral insulating layer contacts the side surface of the unit insulating layer and the side surface of the upper insulating layer.

8. The semiconductor device according to claim 7, wherein: The peripheral insulating layer includes an insulating material having a lower dielectric constant than dielectric constants of the cell insulating layer and the upper insulating layer.

9. The semiconductor device according to claim 1, wherein: The second lower insulating layer includes a material different from that of the first lower insulating layer.

10. The semiconductor device according to claim 1, further comprising: a peripheral conductive contact, on the peripheral region, passing through the first lower insulating layer and the second lower insulating layer and through a lower portion of the peripheral insulating layer, wherein the peripheral conductive contact comprises a first portion in the first lower insulating layer, a second portion in the second lower insulating layer, and a third portion in the peripheral insulating layer, and The width of the first portion is smaller than the width of the third portion.

11. The semiconductor device according to claim 10, wherein: The width of the second portion decreases as the second portion approaches the first portion.

12. The semiconductor device according to claim 10, further comprising: a lower electrode contact, on the cell region, passing through the first lower insulating layer and the second lower insulating layer, and connected to the data storage patterns respectively; as well as a wiring line between the substrate and the first lower insulating layer, The lower electrode contact and the peripheral conductive contact pass through the first lower insulating layer and are connected to the wiring line.

13. A semiconductor device comprising: A substrate including a cell region and a peripheral region; a first lower insulating layer on the cell region and extending onto the peripheral region; a second lower insulating layer on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region; a data storage pattern on the second lower insulating layer on the cell region; a lower electrode contact, on the cell region, passing through the first lower insulating layer and the second lower insulating layer, and connected to the data storage patterns respectively; a cell insulating layer on the second lower insulating layer on the cell region and covering the data storage pattern; a peripheral insulating layer on the second lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer; as well as a peripheral conductive contact in the peripheral insulating layer and through the first lower insulating layer and the second lower insulating layer on the peripheral region, wherein the height of the upper surface of the second lower insulating layer on the peripheral region is lower than the height of the uppermost surface of the second lower insulating layer on the cell region, and The peripheral insulating layer contacts side surfaces of the unit insulating layer and an upper surface of the second lower insulating layer on the peripheral region.

14. The semiconductor device according to claim 13, wherein The second lower insulating layer on the cell region has a recessed upper surface that is recessed toward the substrate and between the data storage patterns, and A height of the recessed upper surface of the second lower insulating layer on the cell region is lower than a height of the uppermost surface of the second lower insulating layer on the cell region.

15. The semiconductor device according to claim 14, further comprising: a capping insulating layer interposed between a side surface of each of the data storage patterns and the cell insulating layer and extending between the recessed upper surface of the second lower insulating layer on the cell region and the cell insulating layer, The peripheral insulating layer is in contact with a side surface of the cover insulating layer.

16. The semiconductor device according to claim 15, further comprising: an upper insulating layer, on the unit insulating layer, Wherein, the peripheral insulating layer contacts the side surface of the upper insulating layer.

17. The semiconductor device according to claim 13, wherein: The peripheral insulating layer includes an insulating material having a lower dielectric constant than that of the unit insulating layer.

18. The semiconductor device according to claim 13, wherein: The first lower insulating layer and the second lower insulating layer include different materials.

19. The semiconductor device according to claim 18, wherein The peripheral conductive contact includes a first portion in the first lower insulating layer, a second portion in the second lower insulating layer, and a third portion in the peripheral insulating layer, The side surface of the first portion is inclined at a first angle relative to the lower surface of the first lower insulating layer, A side surface of the second portion is inclined at a second angle relative to a lower surface of the second lower insulating layer, and The second angle is different from the first angle.

20. The semiconductor device according to claim 19, wherein A side surface of the third portion is inclined at a third angle with respect to an upper surface of the second lower insulating layer on the peripheral region, and The second angle is different from the third angle.

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