3D chip packaging structure
By configuring the connecting pad and conductive cylinder in the 3D chip package structure to form a predefined connection area and connection clearance area, the complex problem of existing high-bandwidth memory circuit design is solved, and the effect of simplifying design difficulty and reducing costs is achieved.
Patent Information
- Application Number
- CN202311271715.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-28
- Publication Date
- 2025-03-28
AI Technical Summary
The circuit design of existing high-bandwidth memory is complex and difficult to directly apply to the logic circuit area, resulting in difficulty in designing chip circuits and increasing costs.
A 3D chip packaging structure is proposed, by configuring a connecting pad and a conductive cylinder in a memory device to form a predefined connection area and a connection clearance area, so that the circuit components can be directly applied to the 3D chip packaging structure without changing the internal design.
It simplifies the difficulty of circuit design, reduces the overall design cost of integrated circuit chips, and improves the convenience of chip design.
Smart Images
Figure CN119730255A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor packaging structure, and in particular to a 3D chip packaging structure. Background Art
[0002] As the demand for data volume increases, conventional memories can no longer meet the requirements for high data volume transmission. Therefore, a high-bandwidth memory with a smaller size, lower power consumption and higher bandwidth is proposed.
[0003] In order to achieve high bandwidth of high bandwidth memory, high bandwidth memory must have more channels to perform data exchange, and currently high bandwidth memory can support up to 4GB channels. Therefore, the number of controllers used to control each channel also increases accordingly.
[0004] Generally speaking, the controller is distributed throughout the entire logic circuit area corresponding to the channel connection point position in the high-bandwidth memory, and the controller is electrically connected to the channel connection point through a conductor. Therefore, the conductor will be distributed between the high-bandwidth memory and the logic circuit area. However, this configuration will make the chip circuit design in the logic circuit area difficult. For example, in order to maintain the configuration between the controller and the high-bandwidth memory, the chip circuit in the logic circuit area needs to be designed to avoid the position of the conductor and the controller. Silicon Intellectual Property (IP) chips are chip types with established internal designs. If their designs are not easy to change, they will be difficult to directly apply to the chip circuit design in the logic circuit area, causing inconvenience in the design of integrated circuit chips. Summary of the invention
[0005] In order to solve the above technical problems, the present application proposes a 3D chip packaging structure, which is applicable to existing silicon intellectual property components, effectively simplifies the difficulty of circuit design, and reduces the overall design cost of integrated circuit (IC) chips, thereby achieving the purpose of improving the convenience of integrated circuit chip design.
[0006] In order to achieve the above-mentioned purpose, the present application proposes a 3D chip packaging structure, which includes a memory device. The memory device includes a memory crystal layer and a connection layer. The memory crystal layer includes at least one memory partition. The connection layer is located on one side of the memory crystal layer and is configured with at least one connection pad. The connection layer corresponding to the at least one memory partition is defined with at least one connection clearance area and at least one connection area, the at least one connection clearance area is adjacent to the at least one connection area, and the area of the at least one connection clearance area is equal to or larger than the at least one connection area. The at least one connection pad is only configured in the at least one connection area.
[0007] Based on the above content, the 3D chip packaging structure provided by the present application configures the connection pads in a predefined connection area and forms a connection clearance area without a conductive column, so that the circuit components can be directly applied to the 3D chip packaging structure according to the connection clearance area configuration without changing their internal design, thereby simplifying the difficulty of circuit design and reducing the overall design cost of the integrated circuit chip with existing circuit components, thereby achieving the purpose of improving the convenience of integrated circuit chip design. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0009] Figure 1 Schematic diagram of a 3D chip packaging structure according to an embodiment of the present application.
[0010] Figure 2 It is a schematic diagram of the configuration of the connection clearance area and the connection area according to an embodiment of the present application.
[0011] Figure 3 Schematic diagram of another configuration of the connection clearance area and the connection area according to an embodiment of the present application.
[0012] Figure 4 Schematic diagram of a structural embodiment of a memory device according to the present application.
[0013] Figure 5 FIG. 4 is a schematic diagram of another structural embodiment of a memory device according to the present application. DETAILED DESCRIPTION
[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0015] See also Figure 1 , Figure 1 Schematic diagram of an embodiment of a 3D chip packaging structure of the present application. The 3D chip packaging structure 1 includes a memory device 10, a logic circuit layer 30 and a substrate 50, wherein the memory device 10 is connected to one side of the logic circuit layer 30 via at least one conductive pillar 20, and the substrate 50 is connected to the other side of the logic circuit layer 30 via a plurality of connection pads 40, so that the logic circuit layer 30 is located between the memory device 10 and the substrate 50.
[0016] The memory device 10 further includes a memory crystal layer 11 and a connection layer 12, and the connection layer 12 is located on one side of the memory crystal layer 11. The memory crystal layer 11 includes at least one memory partition 111. In the present embodiment, a plurality of memory partitions 111 (111a, 111b) are taken as an example, and the present application is not limited thereto. The connection layer 12 is used to configure at least one connection pad 121, and the at least one connection pad 121 is electrically connected to the corresponding memory partition 111, and the at least one connection pad 121 is in contact with and connected to the corresponding conductive column 20. In the present embodiment, a plurality of connection pads 121 are taken as an example, but the present application is not limited thereto. Further, the connection layer 12 corresponding to one memory partition 111 is defined with at least one connection clearance area 13 and at least one connection area 14. The at least one connection clearance area 13 is adjacent to the at least one connection area 14. In the present embodiment, the at least one connection pad 121 is only configured in the at least one connection area 14. That is, the connection pad 121 is not disposed in at least one connection clearance area 13 .
[0017] In one embodiment, at least one connection pad 121 may be implemented by a HBL and a HBC.
[0018] In this embodiment, the memory device 10 is implemented as a high bandwidth memory (HBM).
[0019] Furthermore, the connection area 14 corresponding to a memory partition 111 may be adjacent to one side of the memory partition 111. Figure 1 As shown, the connection area 14 of the memory partition 111 a is respectively arranged on the left and right sides of the corresponding memory partition 111 a in the figure.
[0020] In one embodiment, the number of at least one connection clearance area 13 and at least one connection area 14 is not limited to that shown in the figure. Figure 1 In the embodiment, the memory partition 111a corresponds to two connection areas 14 and one connection clearance area 13. However, in other embodiments, the memory partition 111a may correspond to only one connection area 14 and one connection clearance area 13. Alternatively, in other embodiments, the memory partition 111a may correspond to a plurality of connection areas 14 and a plurality of connection clearance areas 13.
[0021] Furthermore, at least one conductive column 20 is only disposed corresponding to at least one connection area 14. That is, at least one conductive column 20 is not disposed in at least one connection clearance area 13. Figure 1As shown, a plurality of conductive pillars 20 are only arranged on the left and right sides of the corresponding memory partition 111a (111b) in the figure corresponding to the connection area 14. In this embodiment, each of the conductive pillars 20 is in contact with and connected to a connection pad 121 arranged corresponding to at least one connection area 14. Therefore, in this embodiment, the number of at least one conductive pillar 20 corresponds to the number of at least one connection pad 121. That is, the number of at least one conductive pillar 20 is the same as the number of at least one connection pad 121. In one embodiment, at least one conductive pillar 20 can be implemented by multiple metal layers, and the present application is not limited thereto.
[0022] The logic circuit layer 30 is disposed on one side of the memory device 10 and is combined with the memory device 10 through the conductive pillars 20. The logic circuit layer 30 includes at least one circuit element 32. In one embodiment, the logic circuit layer 30 may further include at least one memory controller 31. The at least one memory controller 31 is electrically connected to the corresponding conductive pillars 20. Further, the at least one memory controller 31 may be disposed corresponding to the at least one connection clearance area 13 and / or the at least one connection area 14 of the connection layer 12. For example, Figure 1 As shown, taking a plurality of memory controllers 31 as an example, the memory controllers 31 may correspond to the connection area 14 of the memory partition 111a and be configured at least on one side of the logic circuit layer 30. In other embodiments, the memory controllers 31 may correspond to the connection clearance area 13 of the memory partition 111a and be away from the side of the logic circuit layer 30. In the embodiment in which the memory controllers 31 may correspond to the connection area 14 of the memory partition 111a, the memory controllers 31 may be in contact with and connected to the corresponding conductive pillars 20. In the embodiment in which the memory controllers 31 may correspond to the connection clearance area 13 of the memory partition 111a, the memory controllers 31 may be electrically connected to the conductive pillars 20 through the metal wiring layer (not shown) of the logic circuit layer 30.
[0023] Further, at least one circuit element 32 (32a, 32b) of the logic circuit layer 30 is arranged corresponding to at least one connection clearance area 13. The vertical projection of at least one circuit element 32 overlaps with the vertical projection of at least one connection clearance area 13, and the vertical projection of at least one circuit element 32 does not overlap with the vertical projection of at least one connection area 14. For example, Figure 1 The circuit element 32a is arranged corresponding to the connection clearance area 13 of the memory partition 111a, and the vertical projection of the circuit element 32a overlaps with the vertical projection of the connection clearance area 13 of the memory partition 111a. In this embodiment, at least one circuit element 32 is implemented by an intellectual property (IP) element.
[0024] The embodiment of the 3D chip package structure 1 provided by the present application includes a connection clearance area 13 and a connection area 14, and the connection pad 121 and the conductive column 20 are arranged corresponding to the connection area 14, so that the conductive column 20 is concentrated in the connection area 14 and forms a connection clearance area 13. The circuit component 32 does not need to change and / or divide its circuit design in accordance with the distribution position of the conductive column 20, but can be directly applied to the integrated circuit design in the 3D chip package structure 1 with the original circuit design architecture corresponding to the connection clearance area 13. Therefore, the present application can effectively simplify the difficulty of circuit design, and can reduce the overall design cost of the integrated circuit chip by using the existing quantized circuit component 32, thereby achieving the purpose of improving the convenience of integrated circuit chip design.
[0025] In this embodiment, the 3D chip packaging structure 1 is a single chip system (System on a Chip, SoC) implemented by wafer stacking (3D Wafer on Wafer, WoW).
[0026] Please refer to Figure 2 , Figure 2 Schematic diagram of the configuration of the connection clearance area 13 and the connection area 14. In this embodiment, one memory partition 111 corresponds to one connection clearance area 13 and one connection area 14. The connection area 14 is configured adjacent to the side S1 of the memory partition 111, and the connection clearance area 13 is configured adjacent to the side S2 of the memory partition 111. In this embodiment, the area of the connection clearance area 13 is greater than the area of the connection area 14. In other embodiments, the area of the connection clearance area 13 may be equal to the area of the connection area 14. That is, the area of the connection clearance area 13 is not less than the area of the connection area 14.
[0027] In one embodiment, the connection area 14 may be disposed adjacent to the side S3 of the memory partition 111, and the connection clearance area 13 may be disposed adjacent to the side S4 of the memory partition 111. That is, the connection area 14 may be disposed adjacent to at least any side (S1-S4) of the memory partition 111.
[0028] Please refer to Figure 3 , Figure 3 1 is another configuration diagram of the connection clearance area 13 and the connection area 14. In this embodiment, one memory partition 111 corresponds to a plurality of connection clearance areas 13 and a plurality of connection areas 14, and one connection clearance area 13 is located between two connection areas 14, but the present application is not limited thereto. In this embodiment, the connection area 14 can be further located at a position away from the side of the memory partition 111 according to requirements, but the present application is not limited thereto.
[0029] In one embodiment, the areas of each of the connection clearance regions 13 are the same or different from each other. Figure 3 In the embodiment, the area of the connection clearance region 13a and the area of the connection clearance region 13b may be the same or different.
[0030] In one embodiment, the area of each of the connection regions 14 is the same or different from each other. Figure 3 In the embodiment, the area of the connection region 14a and the area of the connection region 14b may be the same or different.
[0031] Please refer to Figure 4 , Figure 4 Schematic diagram of a structural embodiment of the memory device of the present application. In this embodiment, the memory device 10 includes a metal connection layer 15 and at least one redistribution layer 16 in addition to a memory crystal layer 11 and a connection layer 12. The metal connection layer 15 is configured on one side of the memory crystal layer 11, and the at least one redistribution layer 16 is configured on one side of the connection layer 12. The at least one redistribution layer 16 is located between the metal connection layer 15 and the connection layer 12. The at least one redistribution layer 16 is used to adjust the connection method between the connection point of the metal connection layer 15 and the at least one connection pad 121 of the connection layer 12, and to configure the at least one connection pad 121 in the corresponding connection area 14 or the connection clearance area 13. Therefore, the existing memory device 10 does not need to change the internal wiring design, and only needs to use the at least one redistribution layer 16 to configure the at least one connection pad 121 in the corresponding connection area 14 or the connection clearance area 13, so as to achieve the purpose of improving the convenience of integrated circuit chip design.
[0032] In one embodiment, the memory device 10 may include a plurality of redistribution layers 16 to realize the connection between the connection points of the metal connection layer 15 and the connection pads 121 of the connection layer 12 , and the present application is not limited thereto.
[0033] In one embodiment, the thickness of the at least one redistribution layer 16 is 0.7 to 0.9 micrometers (μm), and the present application is not limited thereto.
[0034] Please refer to Figure 5 , Figure 5 It is a schematic diagram of a structural embodiment of a memory device of the present application. Figure 5 Examples and Figure 4 The difference is that Figure 5The memory device 10 does not include the at least one redistribution layer 16. In this embodiment, the metal connection layer 15 of the memory device 10 can be configured corresponding to the connection area 14 or the connection clearance area 13 during the design stage, so that the memory device 10 does not need to change the configuration of the metal connection layer 15 through additional process procedures, and the connection pad 121 can be directly electrically connected to the metal connection layer 15 and correspondingly arranged in the connection area 14 or the connection clearance area 13, thereby achieving the purpose of improving the convenience of integrated circuit chip design.
[0035] In summary, the 3D chip packaging structure provided by the present application centrally configures the connection pads and conductive pillars between the memory device and the logic circuit layer in a predefined connection area, and forms a connection clearance area where no connection pads and conductive pillars are configured, so that the circuit components can be directly applied to the 3D chip packaging structure without changing their internal design, thereby simplifying the difficulty of circuit design and reducing the overall design cost of the integrated circuit chip with existing circuit components, thereby achieving the purpose of improving the convenience of integrated circuit chip design.
[0036] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0037] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present application and the claims, all of which belong to the scope of protection of the present application.
Claims
1. A 3D chip packaging structure, characterized in that: include: A memory device comprising: A memory crystal layer including at least one memory partition; and A connection layer, located on one side of the memory crystal layer, and provided with at least one connection pad; Among them, the connection layer corresponding to the at least one memory partition is defined with at least one connection clearance area and at least one connection area, the at least one connection clearance area is adjacent to the at least one connection area, the area of the at least one connection clearance area is equal to or larger than the at least one connection area, and the at least one connection pad is only configured in the at least one connection area.
2. The 3D chip packaging structure according to claim 1, characterized in that: It further includes at least one conductive column connected to the at least one connection pad and arranged corresponding to the at least one connection area.
3. The 3D chip packaging structure according to claim 1, characterized in that: The at least one connection region is adjacent to a side of the at least one memory partition.
4. The 3D chip packaging structure according to claim 1, characterized in that: The connection layer corresponding to the at least one memory partition is defined with a plurality of connection areas, and a connection clearance area is configured between two connection areas.
5. The 3D chip packaging structure according to claim 1, characterized in that: The connection layer defines a plurality of connection clearance areas, and the areas of each of the connection clearance areas are the same or different from each other.
6. The 3D chip packaging structure according to claim 4, characterized in that: The area of each of the connecting regions may be the same or different from each other.
7. The 3D chip packaging structure according to claim 2, characterized in that: include: A logic circuit layer is combined with the memory device through the at least one conductive pillar and includes: A vertical projection of at least one circuit element overlaps with a vertical projection of the at least one connection clearance area.
8. The 3D chip packaging structure according to claim 7, characterized in that: The logic circuit layer further includes at least one memory controller, and the at least one memory controller is electrically connected to the at least one conductive column.
9. The 3D chip packaging structure according to claim 1, characterized in that: The memory device includes at least one redistribution layer, and the at least one redistribution layer is disposed between the memory crystal layer and the connection layer.
10. The 3D chip packaging structure according to claim 9, characterized in that: The thickness of the at least one redistribution layer is 0.7 to 0.9 microns.