Variable capacitor device and manufacturing method thereof

Abstract

The invention discloses a variable capacitor device and a manufacturing method thereof. The variable capacitor device comprises a semiconductor substrate, a first electrode structure and a gate structure, an active region is arranged in the semiconductor substrate, a first groove is formed in one side of the active region, and an insulating structure is arranged in the first groove; at least part of the first electrode structure covers the insulating structure in the first groove, and at least part of the first electrode structure is opposite to the first side wall of the first groove; at least part of the gate structure is arranged on the active region, when gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least part of the active region outside the depletion region serves as a second electrode structure and forms a variable capacitor with the first electrode structure. The first electrode structure is formed on the side wall of the first groove of the semiconductor substrate, and at least part of the active region outside the formed depletion region is used as the second electrode structure, so that the capacitance value can be adjusted, the area occupied by the capacitor structure is reduced, the cost is effectively reduced, and the subsequent product performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a variable capacitor device and a manufacturing method thereof. Background Art

[0002] In semiconductor technology, capacitor devices are widely used. Among them, the existing variable capacitors are usually planar structures, that is, the structure of the existing variable capacitor devices is usually polysilicon gate-oxide layer-PW (P-type well) substrate / NW (N-type well) substrate.

[0003] The researchers and developers of this application have discovered that existing planar variable capacitors need to occupy a large active area (AA), which affects the miniaturization of the device. In addition, variable capacitors are usually based on changing the relative effective area between electrode sheets or the distance between electrode sheets to adjust the capacitance value. The accuracy of the adjustment is difficult to control, which makes the cost of variable capacitors high and the difficulty of adjusting the capacitance value high, affecting the performance of subsequent products. Summary of the invention

[0004] The main technical problem solved by the present invention is: to provide a variable capacitor device and a manufacturing method thereof, wherein a first electrode structure is formed in a first groove of a semiconductor substrate, and at least a portion of the first electrode structure is opposite to a first side wall of the first groove, and a depletion region is formed in an active region when a gate voltage is applied to a gate structure, and at least a portion of the active region outside the depletion region is used as a second electrode structure, which can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and corresponding accuracy of adjusting the capacitance value, thereby improving the performance of subsequent products.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a variable capacitor device, including: a semiconductor substrate, wherein an active area is provided in the semiconductor substrate, and a first groove is formed on one side of the active area, and an insulating structure is arranged in the first groove; a first electrode structure, wherein at least part of the first electrode structure covers the insulating structure in the first groove, and at least part of the first electrode structure is opposite to a first side wall of the first groove, and the first side wall is adjacent to the well region; a gate structure, wherein at least part of the gate structure is arranged on the active area, wherein when a gate voltage is applied to the gate structure, a depletion area is formed in the active area, and at least part of the active area outside the depletion area serves as a second electrode structure, forming a variable capacitor with the first electrode structure.

[0006] In one embodiment of the present application, the semiconductor base comprises: a semiconductor substrate, wherein the semiconductor substrate has an active area, and a first groove is formed in the semiconductor substrate on one side of the active area, wherein a first doping region and a second doping region are formed in the active area, the first doping region is formed in the semiconductor substrate, the second doping region is close to the surface of the semiconductor substrate, the first doping region is in contact with the second doping region, and the bottom of the first groove extends to at least a portion of the first doping region; an insulating structure, filling the first groove and covering the semiconductor base.

[0007] In one embodiment of the present application, the insulating structure includes: a first oxide layer, the first oxide layer at least partially covers the first side wall of the first groove; a dielectric layer, covering the first oxide layer, filling the first groove, and covering the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and the first electrode structure at least partially covers the second side wall of the second groove.

[0008] In one embodiment of the present application, the first sidewall of the first groove is in contact with at least the second doped region; wherein, the second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is arranged parallel to the first oxide layer, and at least a portion of the first electrode structure is arranged parallel to the second doped region.

[0009] In one embodiment of the present application, the device further includes: a second oxide layer, wherein the second oxide layer fills the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode layer.

[0010] In one embodiment of the present application, the gate structure includes: a third oxide layer, at least a portion of the third oxide layer covers the insulating structure on the second doping region, and at least a portion of the third oxide layer covers the insulating structure in the first groove and the first electrode structure; a gate layer, the gate layer covers the third oxide layer, and at least a portion of the gate layer is located on the second doping region; and an isolation sidewall covering the sidewalls on both sides of the gate layer.

[0011] In one embodiment of the present application, it also includes: an interlayer dielectric layer, covering the first electrode structure and the gate structure, and a connecting column is formed in the interlayer dielectric layer, and the connecting column includes: a first connecting column and a second connecting column; wherein the first connecting column corresponds to connecting the first electrode structure, and the second connecting column corresponds to connecting the gate structure.

[0012] In one embodiment of the present application, a doped lead-out region is also formed in the active region, wherein the doped lead-out region is in contact with the second doped region in the active region; the connecting column also includes a third connecting column, wherein the third connecting column is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region through the third connecting column.

[0013] To solve the above technical problems, another technical solution adopted in the present application is: providing a method for manufacturing a variable capacitor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has an active area, and a first groove is formed in the semiconductor substrate on one side of the active area, and an insulating structure is arranged in the first groove; forming a first electrode structure, wherein at least part of the first electrode structure covers the insulating structure in the first groove, and at least part of the first electrode structure is opposite to the first side wall of the first groove; forming a gate structure, wherein at least part of the gate structure is arranged on the active area, wherein when a gate voltage is applied to the gate structure, a depletion area is formed in the active area, and at least part of the active area outside the depletion area serves as a second electrode structure, constituting a variable capacitor with the first electrode structure.

[0014] In one embodiment of the present application, providing a semiconductor base includes: providing a semiconductor substrate, and forming an active area in the semiconductor substrate, wherein a first doping area and a second doping area are formed in the active area, the first doping area is formed in the semiconductor substrate, the second doping area is close to the surface of the semiconductor substrate, and the first doping area is in contact with the second doping area; forming a first groove, the first groove is located on one side of the active area, wherein the bottom of the first groove extends at least to a depth of at least a portion of the first doping area; forming an insulating structure, the insulating structure fills the first groove and covers the semiconductor base.

[0015] In one embodiment of the present application, the forming of the insulating structure includes: forming a first oxide layer, wherein the first oxide layer at least partially covers the first side wall of the first groove; forming a dielectric layer, covering the first oxide layer, filling the first groove, and covering the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and the first electrode structure at least partially covers the second side wall of the second groove.

[0016] In one embodiment of the present application, the first sidewall of the first groove is in contact with at least the second doped region; wherein, the second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is arranged parallel to the first oxide layer, and at least a portion of the first electrode structure is arranged parallel to the second doped region.

[0017] In an embodiment of the present application, the method further includes: forming a second oxide layer, wherein the second oxide layer fills the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode structure.

[0018] In one embodiment of the present application, the forming of the gate structure includes: forming a third oxide layer, wherein at least a portion of the third oxide layer covers the second doping region, and at least a portion of the third oxide layer covers the insulating structure in the first groove and the first electrode structure; forming a gate layer, wherein the gate layer covers the third oxide layer, and at least a portion of the gate layer is located on the second doping region; and forming an isolation sidewall, covering the sidewalls on both sides of the gate layer.

[0019] In one embodiment of the present application, it also includes: forming an interlayer dielectric layer to cover the first electrode structure and the gate structure, and a connecting column is formed in the interlayer dielectric layer, and the connecting column includes: a first connecting column and a second connecting column; wherein the first connecting column corresponds to connecting the first electrode structure, and the second connecting column corresponds to connecting the gate structure.

[0020] In one embodiment of the present application, before forming the interlayer dielectric layer, it also includes: forming a doped lead-out region in the active area, wherein the doped lead-out region is in contact with a second doped region in the active area; the connecting column also includes a third connecting column, wherein the third connecting column is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region through the third connecting column.

[0021] Different from the current technology, the variable capacitor device provided by the present application includes a semiconductor substrate, a first electrode structure, and a gate structure; wherein the semiconductor substrate has an active area, and a first groove is formed on one side of the active area, and an insulating structure is arranged in the first groove; at least part of the first electrode structure covers the insulating structure in the first groove, and at least part of the first electrode structure is opposite to the first side wall of the first groove; at least part of the gate structure is arranged on the active area, wherein when the gate voltage is applied to the gate structure, a depletion region is formed in the active area, and at least part of the active area outside the depletion region is used as a second electrode structure to form a variable capacitor with the first electrode structure. That is, in the present application, by forming a first electrode structure covering the side wall of the first groove in the first groove of the semiconductor substrate, the area occupied by the capacitor structure is reduced, and the cost is effectively reduced, and at least part of the active area outside the depletion region formed by applying the gate voltage is used as the second electrode structure, the width of the depletion region can be controlled according to the gate voltage, and then the capacitance value of the capacitor device can be accurately adjusted, which reduces the difficulty of adjustment and is conducive to improving the performance of subsequent products. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0023] Figure 1 is a schematic structural diagram of a first embodiment of a variable capacitance device in the present application;

[0024] Figure 2 is a schematic structural diagram of a second embodiment of a variable capacitance device in the present application;

[0025] Figure 3 It is a flow chart of an embodiment of a method for manufacturing a variable capacitance device in the present application;

[0026] Figure 4 It is a structural schematic diagram of an embodiment of forming the first doping region and the second doping region in the present application;

[0027] Figure 5 is a structural schematic diagram of an embodiment of forming a first groove in the present application;

[0028] Figure 6 is a structural schematic diagram of an embodiment of forming an insulating structure in the present application;

[0029] Figure 7 is a structural schematic diagram of an embodiment of forming a first electrode structure in the present application;

[0030] Figure 8 is a structural schematic diagram of an embodiment of forming a gate structure in the present application;

[0031] Fig. 9 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer and a connecting column in the present application.

[0032] In the accompanying drawings, there are a semiconductor body 100, a semiconductor substrate 110, an active area 111, a first doped area 1111, a second doped area 1112, a depletion region A, a first groove 101, a first sidewall 1011, an insulating structure 120, a first oxide layer 121, a dielectric layer 122, a second groove 102, a second oxide layer 130, a first electrode structure 200, a gate structure 300, a third oxide layer 310, a gate layer 320, an isolation sidewall 330, an interlayer dielectric layer 400, a first connecting column 401, a second connecting column 402, a third connecting column 403, and a doped lead-out region B. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] Current capacitor devices, especially variable capacitor devices, are usually planar structures, that is, the structure of current variable capacitor devices is usually polysilicon gate-oxide layer-PW substrate / NW substrate. Because it is a planar structure, it will occupy a large amount of active area (Active Area, AA), making the cost of variable capacitor devices relatively high; and the capacitance value is usually adjusted based on changing the relative effective area between electrode sheets or the distance between electrode sheets. The difficulty of adjusting the capacitance value is relatively high, which affects the performance of subsequent products.

[0035] Therefore, the present application provides a variable capacitor device, which can effectively reduce the area occupied by the capacitor structure, reduce costs, and improve the difficulty and corresponding accuracy of capacitance value adjustment by forming a first electrode structure in a first groove of a semiconductor substrate, and at least a portion of the first electrode structure is opposite to the first side wall of the first groove, and using the substrate portion outside the depletion region formed in the active area as the second electrode structure.

[0036] See also Figure 1 , Figure 1 It is a schematic structural diagram of the first embodiment of the variable capacitance device in this application.

[0037] The variable capacitor device of the present application includes: a semiconductor substrate 100, a first electrode structure 200, and a gate structure 300; the semiconductor substrate 100 has an active area 111, and a first groove 101 is formed in the semiconductor substrate 100 on one side of the active area 111, and an insulating structure 120 is arranged in the first groove 101. At least part of the first electrode structure 200 covers the insulating structure 120 in the first groove 101, and at least part of the first electrode structure 200 is opposite to the first sidewall 1011 in the first groove 101. At least part of the gate structure 300 is arranged on the active area 111, wherein when a gate voltage is applied to the gate structure 300, a depletion region A is formed in the active area 111, and at least part of the active area 111 outside the depletion region A serves as a second electrode structure, and the second electrode structure and the first electrode structure 200 constitute a variable capacitor.

[0038] The first electrode structure 200 may be a metal layer with uniform thickness.

[0039] In some embodiments, the gate voltage can change the thickness of the depletion region in the horizontal direction, thereby affecting the capacitance value of the variable capacitor. The capacitance value of the variable capacitor device can be adjusted according to the gate voltage, which is a negative correlation, that is, the larger the gate voltage, the larger the thickness of the depletion region in the horizontal direction, the larger the distance between the first electrode structure and the second electrode structure, and the smaller the capacitance value of the variable capacitor; and the smaller the gate voltage, the smaller the thickness of the depletion region in the horizontal direction, the smaller the distance between the first electrode structure and the second electrode structure, and the larger the capacitance value of the variable capacitor.

[0040] In this embodiment, a first electrode structure is formed in a first groove of a semiconductor substrate, and at least a portion of the first electrode structure is opposite to a first side wall of the first groove. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region. At least a portion of the active region outside the depletion region serves as a second electrode structure. The width of the depletion region can be controlled according to the gate voltage, thereby effectively reducing the area occupied by the capacitor structure, reducing costs, and increasing the difficulty and corresponding accuracy of adjusting the capacitance value, thereby improving the performance of subsequent products.

[0041] See also Figure 2 , Figure 2 It is a schematic structural diagram of the second embodiment of the variable capacitance device in the present application.

[0042] like Figure 2 As shown, the semiconductor body 100 includes a semiconductor substrate 110 and an insulating structure 120. The semiconductor substrate 110 has an active area 111, and a first groove 101 is formed in the semiconductor substrate 110 on one side of the active area 111, wherein the active area 111 may be formed with a first doping region 1111 and a second doping region 1112, the first doping region 1111 is formed in the semiconductor substrate 110, the second doping region 1112 is close to the surface of the semiconductor substrate 110, and the first doping region 1111 and the second doping region 1112 are in contact, and the bottom of the first groove 101 extends to at least part of the first doping region 1111. The insulating structure 120 fills the first groove 101 and covers the surface of the semiconductor body 100, specifically covers the surface of the semiconductor substrate 110, and covers the surface of the second doping region 1112.

[0043] The semiconductor substrate 110 may be any suitable substrate known in the art.

[0044] In some embodiments, the first doping region 1111 and the second doping region 1112 in the active region 111 may be doping regions of different types, i.e., the doping types are opposite; for example, the first doping region 1111 is an N-type doping region, and the second doping region is a P-type doping region. In addition, the first doping region 1111 is far from the surface of the semiconductor substrate 110, while the second doping region is close to the surface of the semiconductor substrate 110. Figure 2 As shown, the second doping region 1112 is on the first doping region 1111 , and the second doping region 1112 is close to the surface of the semiconductor substrate 110 .

[0045] In some embodiments, the first groove 101 may be a trapezoidal groove, a rectangular groove, a square groove, an inverted trapezoidal groove, etc., which may be set according to actual conditions.

[0046] In some embodiments, the first sidewall 1011 of the first groove 101 can be set to be adjacent to the active area 111, while the third sidewall (not marked in the figure) of the first groove 101 is in contact with the semiconductor substrate or another active area; wherein, there can be a portion of the semiconductor substrate between the first sidewall 1011 and the active area 111, so that the first sidewall 1011 and the active area 111 are not in contact, but have a certain distance; in another embodiment, the first sidewall 1011 can also be in direct contact with the active area 111, that is, the first sidewall 1011 of the first groove 101 is in contact with the active area 111, and the third sidewall of the first groove 101 is in contact with the semiconductor substrate or another active area, and the first sidewall 1011 is in contact with the semiconductor substrate or another active area. Figure 2 Take the case where the first sidewall 1011 contacts the active region 111 as an example.

[0047] It can be understood that the first side wall 1011 is attached Figure 2 If the first groove 101 is on the right side wall, the third side wall is the left side wall of the first groove 101.

[0048] Furthermore, the depth of the first groove 101 may be the same as the depth of the doped region, that is, the distance from the bottom of the first groove 101 to the bottom of the semiconductor substrate is equal to the distance from the bottom surface of the first doped region 1111 to the bottom of the semiconductor substrate. Alternatively, the depth of the first groove 101 may be slightly smaller than the depth of the doped region, that is, the distance from the bottom of the first groove 101 to the bottom of the semiconductor substrate is slightly smaller than the distance from the bottom surface of the first doped region 1111 to the bottom of the semiconductor substrate. Alternatively, the depth of the first groove 101 may be slightly larger than the depth of the doped region, that is, the distance from the bottom of the first groove 101 to the bottom of the semiconductor substrate is slightly larger than the distance from the bottom surface of the first doped region 1111 to the bottom of the semiconductor substrate.

[0049] Continue reading Figure 2The insulating structure 120 may include a first oxide layer 121 and a dielectric layer 122 . The first oxide layer 121 at least partially covers the first sidewall 1011 of the first groove 101 . The dielectric layer 122 covers the first oxide layer 121 and fills the first groove 101 .

[0050] The material of the first oxide layer 121 may be an oxide material, and the material of the dielectric layer 122 may be a dielectric material.

[0051] In some embodiments, the first oxide layer 121 may cover the entire inner side wall of the first groove 101 , that is, cover the first side wall 1011 , the third side wall and the first bottom wall of the first groove 101 , and then form a dielectric layer 122 on the first oxide layer 121 , so that the dielectric layer 122 may cover the first oxide layer 121 .

[0052] The first sidewall 1011 of the first groove 101 at least contacts the second doping region 1112 , so that the first oxide layer 121 can contact the second doping region 1112 .

[0053] Furthermore, the dielectric layer 122 can also cover the surface of the semiconductor substrate 110, that is, the dielectric layer 122 covers the surface of the semiconductor substrate 110 outside the first groove 101; the first electrode structure 200 covers the dielectric layer 122 on the side of the first groove 101 away from the second doping region 1112, and the first electrode structure 200 is in contact with the dielectric layer 122.

[0054] In some embodiments, a second groove 102 is further formed in the dielectric layer 122 in the first groove 101, and at least a portion of the first electrode structure 200 covers the second sidewall 1021 of the second groove 102. In addition, the second sidewall 1021 of the second groove 102 is parallel to the first sidewall 1011 of the first groove 101, so that at least a portion of the first electrode structure 200 is arranged in parallel with the first oxide layer 121, and at least a portion of the first electrode structure 200 is arranged in parallel with the second doping region 1112.

[0055] Further, the second groove 102 may include a second side wall 1021, a fourth side wall (not marked in the figure) and a second bottom wall (not marked in the figure), wherein the second side wall 1021 of the second groove 102 is arranged in parallel with the first side wall 1011 of the first groove 101, the fourth side wall (not marked in the figure) of the second groove 102 is arranged in parallel with the third side wall (not marked in the figure) of the first groove 101, and the second bottom wall of the second groove 102 is arranged in parallel with the first bottom wall (not marked in the figure) of the first groove 101. In addition, the distance between the second bottom wall of the second groove 102 and the first bottom wall of the first groove 101 can be set according to actual conditions, that is, the depth of the first groove 101 is greater than the depth of the second groove 102, and the specific depth difference can be set according to actual conditions.

[0056] Continue reading Figure 2 , further comprising a second oxide layer 130 , the second oxide layer 130 filling the second groove 102 , so that the second oxide layer 130 is isolated from the dielectric layer 122 by the first electrode structure 200 , and the surface of the second oxide layer 130 can be flush with the first electrode structure 200 on the dielectric layer 122 .

[0057] The material of the second oxide layer 130 may be an oxidized material.

[0058] Continue reading Figure 2 , the gate structure 300 may include a third oxide layer 310, a gate layer 320 and an isolation spacer 330. Among them, at least part of the third oxide layer 310 covers the insulating structure 120 on the second doping region 1112, and at least part of the third oxide layer 310 covers the insulating structure 120 and the first electrode structure 200 in the first groove 101; the gate layer 320 covers the third oxide layer 310, and at least part of the gate layer 320 is located on the second doping region 1112; the isolation spacer 330 covers the sidewalls on both sides of the gate layer 320, and further, the isolation spacer 330 can also cover the sidewalls on both sides of the third oxide layer 310.

[0059] The third oxide layer 310 is made of an oxide material; the gate layer 320 is made of a gate material, such as a polysilicon material; and the isolation spacer 330 is made of an isolation material.

[0060] Specifically, a portion of the third oxide layer 310 covers the dielectric layer 122, the first electrode structure 200, and a portion of the second oxide layer 130 within the first groove 101; another portion of the third oxide layer 310 covers at least a portion of the second doped region 1112, specifically, another portion of the third oxide layer 310 covers the dielectric layer 122 on the second doped region 1112.

[0061] Continue reading Figure 2 , may further include an interlayer dielectric layer 400, covering the first electrode structure 200 and the gate structure 300, wherein a connecting column is formed in the interlayer dielectric layer 400, and the connecting column includes a first connecting column 401 and a second connecting column 402. The first connecting column 401 is connected to the first electrode structure 200, and the second connecting column 402 is connected to the gate structure 300.

[0062] In some embodiments, a doped lead-out region B is further formed in the active region 111, and the doped lead-out region B contacts the second doped region 1112. The corresponding connecting column further includes a third connecting column 403, and the third connecting column 403 is correspondingly connected to the doped lead-out region B. When a gate voltage is applied to the gate structure 300, a depletion region A is formed in the active region 111, and at least a portion of the active region 111 outside the depletion region A serves as a second electrode structure, that is, a depletion region A is formed in the second doped region 1112, and at least a portion of the second doped region 1112 outside the depletion region A serves as a second electrode structure, and the second doped region 1112 contacts the doped lead-out region B, so that the second electrode structure is connected to the outside through the doped lead-out region B through the third connecting column 403.

[0063] Specifically, the first connecting column 401 is connected to the first electrode structure 200, and connects the first electrode structure 200 to an external power supply (Vin) for applying a bias voltage. The second connecting column 402 is connected to the gate structure 300, and connects the gate structure 300 to a power supply (DC) for applying a gate voltage, forming a depletion region A in the second doping region 1112, and at least a portion of the second doping region outside the depletion region serves as a second electrode structure, and the second doping region 1112 is in contact with the doped lead-out region B, therefore, the third connecting column 403 connects the doped lead-out region B to the second electrode structure, so that the second electrode structure is grounded (GND) through the third connecting column 403.

[0064] The working principle is: applying different forward gate voltages on the gate structure can change the initial thickness of the dielectric layer between the first electrode structure and the second electrode structure, that is, change the first thickness A1 of the depletion region A in the vertical direction, and can also change the second thickness A2 of the depletion region A in the horizontal direction. Further, applying a forward voltage on the first electrode structure 200 can change the second thickness A2 of the depletion region A in the horizontal direction from the first sidewall 1011. That is, when the gate voltage is applied, the depletion region A is formed, and the first thickness A1 of the depletion region A in the vertical direction and the second thickness A2 of the depletion region A in the horizontal direction from the first sidewall 1011 of the first groove appear; when the gate voltage is increased, the first thickness A1 can be increased, and even the second thickness A2 can be increased; further, when a forward voltage is applied to the first electrode structure 200, the second thickness A2 can be increased. Therefore, the variable control of the capacitance value of the variable capacitor device can be achieved by controlling the voltage applied to the first electrode structure and the gate voltage applied to the gate structure, wherein the capacitance is the series capacitance corresponding to the initial thickness of the dielectric layer and the first thickness of the depletion region A in the horizontal direction.

[0065] In the present embodiment, a first electrode structure is formed in the first groove of the semiconductor substrate, and at least a portion of the first electrode structure is opposite to the first side wall of the first groove. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region formed in the active region is used as the second electrode structure. This can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and corresponding accuracy of adjusting the capacitance value, thereby improving the performance of subsequent products.

[0066] The present application also provides a method for manufacturing a variable capacitance device.

[0067] See also Figure 3 , Figure 3 It is a flow chart of an embodiment of a method for manufacturing a variable capacitance device in the present application.

[0068] like Figure 3 As shown, the method for manufacturing a variable capacitance device may include the following steps.

[0069] S10. Provide a semiconductor substrate, wherein the semiconductor substrate has an active region, a first groove is formed in the semiconductor substrate on one side of the active region, and an insulating structure is arranged in the first groove.

[0070] The semiconductor body includes a semiconductor substrate.

[0071] Specifically, an active region 111 is formed in the semiconductor substrate 110 , wherein a first doping region 1111 and a second doping region 1112 are formed in the active region 111 ; further, a first groove 101 is formed in the semiconductor substrate 110 , and an insulating structure 120 is formed in the first groove 101 .

[0072] S20, forming a first electrode structure, wherein at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to the first sidewall of the first groove.

[0073] Specifically, a first electrode structure 200 is formed in the first groove 101 to cover the insulating structure 120 in the first groove 101, and at least a portion of the first electrode structure 200 in the first groove 101 is opposite to the first side wall 1011 of the first groove 101. It can be understood that at least a portion of the relative first electrode structure 200 is arranged in parallel with the first side wall 1011 of the first groove 101, and an insulating structure 120 is also arranged between the first electrode structure 200 and the first side wall 1011 of the first groove 101.

[0074] S30, forming a gate structure, wherein at least a portion of the gate structure is disposed on the active region, wherein when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure to form a variable capacitor together with the first electrode structure.

[0075] Among them, at least part of the second doped region 1112 serves as a second electrode structure, that is, when a gate voltage is applied to the gate structure 300, at least part of the second doped region 1112 in the active region 111 forms a depletion region A, and at least part of the second doped region 1112 outside the depletion region A serves as a second electrode structure.

[0076] Specifically, a gate structure 300 is formed on the first groove 101 and the second doping region 1112, so that at least part of the gate structure 300 is located on the second doping region 1112 of the active region 111, and then when a gate voltage is applied to the gate structure 300, at least part of the second doping region 1112 between the first doping region 1111 and the gate structure 300 forms a depletion region A, and then at least part of the second doping region 1112 outside the depletion region A is used as a second electrode structure, and electrons are allowed to flow from the first doping region 1111 to the direction of the gate structure 300.

[0077] In the present embodiment, by forming a first electrode structure in the first groove of the semiconductor substrate, and at least a portion of the first electrode structure is opposite to the first side wall of the first groove, when a gate voltage is applied to the gate structure, a depletion region is formed in the second doping region, and at least a portion of the second doping region outside the depletion region is used as the second electrode structure, which can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and corresponding accuracy of adjusting the capacitance value, thereby improving the performance of subsequent products.

[0078] Hereinafter, a method for manufacturing a variable capacitance device will be described with reference to the accompanying drawings.

[0079] First, a semiconductor substrate is provided, and an active region is formed in the semiconductor substrate, wherein a first doping region and a second doping region are formed in the active region.

[0080] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming the first doping region and the second doping region in the present application.

[0081] like Figure 4As shown, a first doping region 1111 and a second doping region 1112 are formed in an active region 111 of a semiconductor substrate 110, and the first doping region 1111 and the second doping region 1112 constitute a part of the active region 111. The first doping region 1111 is formed in the semiconductor substrate 110, and the second doping region 1112 is close to the surface of the semiconductor substrate 110, and the first doping region 1111 is in contact with the second doping region 1112.

[0082] Then, a first groove 101 is formed in the semiconductor substrate 110 .

[0083] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of forming a first groove in the present application.

[0084] like Figure 5 As shown, in Figure 4 On this basis, a first groove 101 is formed in the semiconductor substrate 110 , and the bottom of the first groove 101 can be flush with the bottom of the first doping region 1111 , or slightly higher than the bottom of the first doping region 1111 , or slightly lower than the bottom of the first doping region 1111 .

[0085] In some embodiments, the first sidewall 1011 of the first groove 101 is adjacent to the active region 111, that is, a portion of the semiconductor substrate 110 may be present between the first sidewall 1011 and the active region 111. In another embodiment, the first sidewall 1011 of the first groove 101 may be in contact with the active region 111, that is, no semiconductor substrate 110 may be present between the first sidewall 1011 and the active region 111.

[0086] Furthermore, an insulating structure 120 is formed in the first groove 101 .

[0087] See also Figure 6 , Figure 6 It is a structural schematic diagram of an embodiment of forming an insulating structure in the present application.

[0088] like Figure 6 As shown, in Figure 5 On the basis of, a first oxide layer 121 is formed in the first groove, and the first oxide layer 121 at least partially covers the first side wall 1011 of the first groove 101, and then a dielectric layer 122 is formed, the dielectric layer 122 covers the first oxide layer 121 and fills the first groove 101, with the first oxide layer 121 and the dielectric layer 122 serving as the insulating structure 120.

[0089] In some embodiments, the dielectric layer 122 may also cover the surface of the active region 111 . Furthermore, the dielectric layer 122 may also cover the entire surface of the semiconductor substrate 110 .

[0090] In some embodiments, a second groove 102 can also be formed in the dielectric layer in the first groove 101, the second side wall of the second groove 102 corresponds to and is parallel to the first side wall 1011 of the first groove 101, the fourth side wall of the second groove 102 corresponds to and is parallel to the third side wall of the first groove 101, and the second bottom wall of the second groove 102 corresponds to and is parallel to the first bottom wall of the first groove 101.

[0091] Furthermore, a first electrode structure 200 is formed.

[0092] See also Figure 7 , Figure 7 It is a structural schematic diagram of an embodiment of forming a first electrode structure in the present application.

[0093] like Figure 7 As shown, in Figure 6 On the basis of this, a first electrode structure 200 is formed in the second groove 102 and on the dielectric layer 122 on the side of the second groove 102 away from the active area 111, so that at least a portion of the first electrode structure 200 covers the insulating structure 120 in the first groove 101, and at least a portion of the first electrode structure 200 is opposite to the first sidewall 1011 of the first groove 101.

[0094] In some embodiments, a second oxide layer 130 may also be formed to cover the first electrode structure 200 in the second groove 102 and fill the second groove 102 , and the second oxide layer 130 may be flush with the first electrode structure 200 on the semiconductor substrate; in other embodiments, the second oxide layer 130 may be flush with the dielectric layer 122 on the semiconductor substrate 110 .

[0095] In some embodiments, when forming the first electrode structure 200, the first electrode structure 200 can also cover the semiconductor substrate 110 of the active area 111, and then before forming the gate structure 300, the first electrode structure 200 of the active area 111 is removed, while the first electrode structure 200 in the second groove 102 and on the side of the semiconductor substrate 110 away from the active area 111 is retained.

[0096] Furthermore, a gate structure 300 is formed.

[0097] See also Figure 8 , Figure 8 It is a structural schematic diagram of an embodiment of forming a gate structure in the present application.

[0098] like Figure 8 As shown, in Figure 7On the basis of the present invention, a third oxide layer 310 is formed to cover the entire semiconductor substrate, and then a gate material is formed on the third oxide layer 310, and then a portion of the gate material and the third oxide layer 310 on the first groove 101 and a portion of the gate material on the active area 111 are removed, and the remaining gate material is used as the gate layer 320, and an isolation sidewall 330 is formed on the sidewalls of both sides of the gate layer 320; so that at least a portion of the third oxide layer 310 covers the insulating structure 120 on the second doped area 1112, and at least a portion of the third oxide layer 310 covers the insulating structure 120 in the first groove 101, the first electrode structure 200 and the second oxide layer 130.

[0099] In some embodiments, ion implantation may be performed in the second doping region 1112 to form a doped lead-out region B, which is in contact with the second doping region 1112. The doped lead-out region B may be a lightly doped region, such as a P-type lightly doped region.

[0100] Furthermore, an interlayer dielectric layer and a connecting column are formed.

[0101] See also Fig. 9 , Fig. 9 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer and a connecting column in the present application.

[0102] like Fig. 9 As shown, in Figure 8 On the basis of the above, an interlayer dielectric layer 400 is formed, the interlayer dielectric layer 400 covers the first electrode structure 200 and the gate structure 300, and a connecting column is formed in the interlayer dielectric layer 400, and the connecting column may include a first connecting column 401 and a second connecting column 402. The first connecting column 401 is connected to the first electrode structure 200, so that the first electrode structure 200 is connected to the power supply (Vin) through the first connecting column 401; the second connecting column 402 is connected to the gate structure 300, so that the gate structure 300 is connected to the power supply (DC) through the second connecting column 402.

[0103] In some embodiments, the connecting column may further include a third connecting column 403, and the third connecting column 403 corresponds to the connected doped lead-out region B. When a gate voltage is applied to the gate structure 300, a depletion region A is formed in the active region 111, and at least a portion of the active region 111 outside the depletion region A serves as a second electrode structure, that is, a depletion region A is formed in the second doped region 1112, and at least a portion of the second doped region 1112 outside the depletion region A serves as a second electrode structure, and the second doped region 1112 contacts the doped lead-out region B, so that the second electrode structure is connected to the outside through the doped lead-out region B through the third connecting column 403. Specifically, the third connecting column 403 can be grounded (GND).

[0104] In the present embodiment, a first electrode structure is formed in the first groove of the semiconductor substrate, and at least a portion of the first electrode structure is opposite to the first side wall of the first groove. When a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region formed in the active region is used as the second electrode structure. This can effectively reduce the area occupied by the capacitor structure, reduce costs, and increase the difficulty and corresponding accuracy of adjusting the capacitance value, thereby improving the performance of subsequent products.

[0105] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A variable capacitance device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has an active region, a first groove is formed on one side of the active region, and an insulating structure is arranged in the first groove; a first electrode structure, wherein at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove; A gate structure, wherein at least a portion of the gate structure is disposed on the active region, wherein when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure to form a variable capacitor with the first electrode structure.

2. The variable capacitance device according to claim 1, wherein: The semiconductor substrate comprises: A semiconductor substrate, wherein the semiconductor substrate has an active region, and a first groove is formed in the semiconductor substrate on one side of the active region, wherein a first doping region and a second doping region are formed in the active region, the first doping region is formed in the semiconductor substrate, the second doping region is close to a surface of the semiconductor substrate, the first doping region is in contact with the second doping region, and the bottom of the first groove extends to at least a portion of the first doping region; The insulating structure fills the first groove and covers the semiconductor substrate.

3. The variable capacitance device according to claim 2, characterized in that: The insulating structure comprises: a first oxide layer, wherein at least a portion of the first oxide layer covers a first sidewall of the first groove; A dielectric layer covers the first oxide layer, fills the first groove, and covers the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and the first electrode structure at least partially covers the second sidewall of the second groove.

4. The variable capacitance device according to claim 3, characterized in that: The first sidewall of the first groove at least contacts the second doped region; The second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is arranged in parallel with the first oxide layer, and at least a portion of the first electrode structure is arranged in parallel with the second doping region.

5. The variable capacitance device according to claim 3, characterized in that: Also includes: A second oxide layer fills the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode structure.

6. The variable capacitance device according to claim 2, wherein: The gate structure comprises: a third oxide layer, wherein at least a portion of the third oxide layer covers the second doping region, and at least a portion of the third oxide layer covers the insulating structure in the first groove and the first electrode structure; a gate layer, the gate layer covering the third oxide layer, and at least a portion of the gate layer is located on the second doping region; The isolation sidewalls cover the sidewalls on both sides of the gate layer.

7. The variable capacitance device according to claim 1, wherein: Also includes: an interlayer dielectric layer, covering the first electrode structure and the gate structure, wherein a connecting column is formed in the interlayer dielectric layer, and the connecting column comprises: a first connecting column and a second connecting column; The first connecting column is connected to the first electrode structure, and the second connecting column is connected to the gate structure.

8. The variable capacitance device according to claim 7, wherein: A doped lead-out region is also formed in the active region, wherein the doped lead-out region is in contact with the second doped region in the active region; The connection pillar further includes a third connection pillar, wherein the third connection pillar is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region via the third connection pillar.

9. A method for manufacturing a variable capacitance device, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate has an active region, a first groove is formed in the semiconductor substrate on one side of the active region, and an insulating structure is provided in the first groove; forming a first electrode structure, wherein at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove; A gate structure is formed, wherein at least a portion of the gate structure is disposed on the active region, wherein when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure to form a variable capacitor with the first electrode structure.

10. The manufacturing method according to claim 9, characterized in that: The semiconductor substrate is provided, comprising: Providing a semiconductor substrate, and forming an active region in the semiconductor substrate, wherein a first doping region and a second doping region are formed in the active region, the first doping region is formed in the semiconductor substrate, the second doping region is close to a surface of the semiconductor substrate, and the first doping region is in contact with the second doping region; forming a first groove, wherein the first groove is located at one side of the active region, wherein a bottom of the first groove extends at least to a depth of at least a portion of the first doped region; An insulating structure is formed, wherein the insulating structure fills the first groove and covers the semiconductor substrate.

11. The manufacturing method according to claim 10, characterized in that: The forming of the insulating structure comprises: forming a first oxide layer, wherein at least a portion of the first oxide layer covers a first sidewall of the first groove; A dielectric layer is formed to cover the first oxide layer, fill the first groove, and cover the semiconductor substrate, wherein a second groove is formed in the dielectric layer in the first groove, and the first electrode structure at least partially covers the second sidewall of the second groove.

12. The manufacturing method according to claim 11, characterized in that: The first sidewall of the first groove at least contacts the second doped region; The second sidewall of the second groove is parallel to the first sidewall, so that at least a portion of the first electrode structure is arranged in parallel with the first oxide layer, and at least a portion of the first electrode structure is arranged in parallel with the second doping region.

13. The manufacturing method according to claim 11, characterized in that: Also includes: A second oxide layer is formed, wherein the second oxide layer fills the second groove, wherein the second oxide layer is isolated from the dielectric layer by the first electrode structure.

14. The manufacturing method according to claim 10, characterized in that: The forming of the gate structure comprises: forming a third oxide layer, wherein at least a portion of the third oxide layer covers the second doping region, and at least a portion of the third oxide layer covers the insulating structure in the first groove and the first electrode structure; forming a gate layer, wherein the gate layer covers the third oxide layer, and at least a portion of the gate layer is located on the second doped region; An isolation sidewall is formed to cover the sidewalls on both sides of the gate layer.

15. The manufacturing method according to claim 9, characterized in that: Also includes: An interlayer dielectric layer is formed to cover the first electrode structure and the gate structure, and a connecting column is formed in the interlayer dielectric layer, and the connecting column includes: a first connecting column and a second connecting column; The first connecting column is connected to the first electrode structure, and the second connecting column is connected to the gate structure.

16. The manufacturing method according to claim 15, characterized in that: Before forming the interlayer dielectric layer, the method further includes: forming a doped lead-out region in the active region, wherein the doped lead-out region contacts the second doped region in the active region; The connection pillar further includes a third connection pillar, wherein the third connection pillar is correspondingly connected to the doped lead-out region, so that the second electrode structure is connected to the outside through the doped lead-out region via the third connection pillar.

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