Capacitor structure, control method thereof and semiconductor device

Abstract

The invention provides a capacitor structure and a control method thereof, and a semiconductor device, and the capacitor structure comprises a substrate in which a second body region is formed; the capacitor comprises a third source / drain electrode region, a fourth source / drain electrode region and a depletion layer, the third source / drain electrode region and the fourth source / drain electrode region are formed in the second body region at intervals, the doping type of the third source / drain electrode region and the doping type of the fourth source / drain electrode region are both opposite to the doping type of the second body region, and the depletion layer is formed between the third source / drain electrode region and the fourth source / drain electrode region. And the depletion layer is formed between the third source / drain region and the second body region and between the fourth source / drain region and the second body region. According to the technical scheme, the capacitor structure can meet different design requirements of devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a capacitor structure and a control method thereof, and a semiconductor device. Background Art

[0002] To improve the uneven distribution of RF signal voltage, feedforward capacitor technology is generally used, that is, an external feedforward capacitor is installed between the gate and the source and drain to regulate the voltage. How to make the feedforward capacitor meet the different design requirements of the device is an urgent problem to be solved. Summary of the invention

[0003] The object of the present invention is to provide a capacitor structure and a control method thereof, and a semiconductor device, so that the capacitor structure meets different design requirements of the device.

[0004] To achieve the above object, the present invention provides a capacitor structure, comprising:

[0005] a substrate having a second body region formed therein;

[0006] A capacitor comprises a third source / drain region, a fourth source / drain region and a depletion layer, wherein the third source / drain region and the fourth source / drain region are formed in the second body region at intervals, and the doping types of the third source / drain region and the fourth source / drain region are opposite to the doping type of the second body region, so that the depletion layer is formed between the third source / drain region and the fourth source / drain region and the second body region.

[0007] Optionally, the capacitor structure also includes a second gate structure, which is formed on the second body region between the third source / drain region and the fourth source / drain region; the width of the depletion layer changes with the potential difference applied to the second body region and the second gate structure, so that the capacitance value of the capacitor changes.

[0008] Optionally, the second gate structure is T-shaped or H-shaped, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the “|” portion of the T-shaped or the “-” portion of the H-shaped.

[0009] Optionally, the capacitor structure further includes:

[0010] The second body contact region is formed in the second body region on the side of the T-type "-" portion away from the third source / drain region and the fourth source / drain region, or is formed in the second body region on the side of the H-type "|" portion away from the third source / drain region and the fourth source / drain region.

[0011] The present invention also provides a method for controlling a capacitor structure, comprising:

[0012] Providing the capacitor structure;

[0013] A potential difference is applied to the capacitive structure so that a capacitor in the capacitive structure has an adjustable capacitance value.

[0014] Optionally, the capacitor structure further includes a second gate structure, wherein the second gate structure is formed on the second body region between the third source / drain region and the fourth source / drain region; and applying a potential difference to the capacitor structure includes:

[0015] A potential difference is applied to the second body region and the second gate structure, so that the width of the depletion layer changes, thereby changing the capacitance value of the capacitor.

[0016] The present invention also provides a semiconductor device, comprising:

[0017] A transistor comprising a first source / drain region, a second source / drain region and a first gate structure;

[0018] A capacitor having an adjustable capacitance value is connected between the first source / drain region and the first gate structure.

[0019] Optionally, the semiconductor device further includes a substrate, the first gate structure is formed on the substrate, and the first source / drain region and the second source / drain region are formed in the substrate on both sides of the first gate structure.

[0020] Optionally, the semiconductor device further comprises a substrate, in which a second body region is formed; the capacitor comprises a third source / drain region, a fourth source / drain region and a depletion layer, the third source / drain region and the fourth source / drain region are alternately formed in the second body region, and the doping types of the third source / drain region and the fourth source / drain region are opposite to the doping type of the second body region, so that the depletion layer is formed between the third source / drain region and the fourth source / drain region and the second body region;

[0021] The third source / drain region is electrically connected to the first gate structure, and the fourth source / drain region is electrically connected to the first source / drain region.

[0022] Optionally, the semiconductor device further includes a second gate structure, wherein the second gate structure is formed on the second body region between the third source / drain region and the fourth source / drain region.

[0023] Optionally, the width of the depletion layer changes with the change of the potential difference applied to the second body region and the second gate structure, so that the capacitance value of the capacitor changes.

[0024] Optionally, the first source / drain region is a source region, and the second source / drain region is a drain region.

[0025] Optionally, the semiconductor device further includes:

[0026] a first resistor, electrically connected to the first gate structure; and / or,

[0027] The second resistor is electrically connected between the first source / drain region and the second source / drain region.

[0028] Optionally, the doping type of the first source / drain region and the second source / drain region is the same as the doping type of the third source / drain region and the fourth source / drain region.

[0029] Optionally, the first gate structure and the second gate structure are T-type or H-type in shape, the first source / drain region and the second source / drain region are located in the substrate on both sides of the “|” portion of the T-type or the “-” portion of the H-type, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the “|” portion of the T-type or the “-” portion of the H-type.

[0030] Optionally, the semiconductor device further includes:

[0031] A first body region is formed in the substrate, the first gate structure is formed on the first body region, and the first source / drain region and the second source / drain region are formed in the first body region on both sides of the T-shaped “|” portion or the H-shaped “-” portion;

[0032] A first body contact region is formed in the first body region at a side of the T-shaped “-” portion away from the first source / drain region and the second source / drain region, or is formed in the first body region at a side of the H-shaped “|” portion away from the first source / drain region and the second source / drain region;

[0033] The second body contact region is formed in the second body region on the side of the T-type "-" portion away from the third source / drain region and the fourth source / drain region, or is formed in the second body region on the side of the H-type "|" portion away from the third source / drain region and the fourth source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a layout of a semiconductor device according to an embodiment of the present invention;

[0035] Figure 2 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown along the AA' direction;

[0036] Figure 3is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

[0037] Among them, Figure 1 to Figure 3 The reference numerals are described as follows:

[0038] 10-substrate; 101-lower substrate; 102-buried insulating layer; 103-semiconductor layer; 11-first gate structure; 12-first source / drain region; 13-second source / drain region; 14-first body contact region; 21-second gate structure; 211-second gate dielectric layer; 22-third source / drain region; 23-fourth source / drain region; 24-second body contact region; 241-second body region; 25-depletion layer; 31-first conductive structure; 32-second conductive structure; 33-conductive plug; 34-conductive interconnect structure. DETAILED DESCRIPTION

[0039] In order to make the purpose, advantages and features of the present invention clearer, the capacitor structure and its control method and the semiconductor device proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, in which a second body region is formed; a capacitor, comprising a third source / drain region, a fourth source / drain region and a depletion layer, wherein the third source / drain region and the fourth source / drain region are formed in the second body region at intervals, and the doping types of the third source / drain region and the fourth source / drain region are opposite to the doping type of the second body region, so that the depletion layer is formed between the third source / drain region and the fourth source / drain region and the second body region.

[0041] See below Figure 1-2 The capacitor structure provided in this embodiment is described in more detail.

[0042] A second body region 241 is formed in the substrate 10 .

[0043] The capacitor includes a third source / drain region 22, a fourth source / drain region 23 and a depletion layer 25. The third source / drain region 22 and the fourth source / drain region 23 are formed alternately in the second body region 241. The doping types of the third source / drain region 22 and the fourth source / drain region 23 are opposite to the doping type of the second body region 241, so that the depletion layer 25 is formed between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241.

[0044] The second body region 241 is a well region formed by ion implantation into the substrate 10 , and the second body region 241 is used to separate the third source / drain region 22 and the fourth source / drain region 23 .

[0045] The third source / drain region 22 is a source region, and the fourth source / drain region 23 is a drain region; or, the fourth source / drain region 23 is a source region, and the third source / drain region 22 is a drain region.

[0046] The capacitor structure also includes a second gate structure 21, which is formed on the second body region 241 between the third source / drain region 22 and the fourth source / drain region 23; the width of the depletion layer 25 changes with the change of the potential difference applied to the second body region 241 and the second gate structure 21, so that the capacitance value of the capacitor changes, that is, the capacitor has an adjustable capacitance value.

[0047] The depletion layer 25 is formed by applying a potential difference between the second body region 241 and the second gate structure 21 .

[0048] The third source / drain region 22 and the fourth source / drain region 23 serve as two plates of the capacitor, and the dielectric layer between the two plates includes the depletion layer 25. The change in the width W of the depletion layer 25 is the change in the thickness of the dielectric layer. The thickness of the dielectric layer changes with the change in the potential difference applied to the second body region 241 and the second gate structure 21. Therefore, the capacitance value of the capacitor can change with the change in the potential difference applied to the second body region 241 and the second gate structure 21. In one embodiment, the greater the potential difference, the greater the width W of the depletion layer 25.

[0049] Applying the required potential difference to the second body region 241 and the second gate structure 21 may include: applying a voltage to one of the second body region 241 and the second gate structure 21 and grounding or floating the other, or applying a voltage to both the second body region 241 and the second gate structure 21 .

[0050] The substrate 10 may be made of any suitable material known to those skilled in the art.

[0051] The substrate 10 may be a bulk substrate or a SOI (Semiconductor On Insulator) substrate. The bulk substrate may be, for example, a commonly used substrate in the semiconductor field such as silicon, germanium, GaN, etc. The SOI substrate may be, for example, a silicon on insulator or a germanium on insulator substrate. The SOI substrate includes, from bottom to top, a lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103.

[0052] In one embodiment, when the substrate 10 is a bulk substrate, if the second body region 241 and the substrate 10 around it have the same doping type, a doping region (not shown) is further formed around the second body region 241 (i.e., the lower surface and side surfaces of the second body region 241) to wrap the second body region 241. The doping region has an opposite doping type to the second body region 241, and the doping region is used to separate the second body region 241 from the substrate 10 around it, so that voltage can be applied to the second body region 241 separately.

[0053] When the substrate 10 is an SOI substrate, the third source / drain region 22 and the fourth source / drain region 23 may be formed at a partial thickness (eg Figure 2 As shown) or in the semiconductor layer 103 of the entire thickness, so that the lower surfaces of the third source / drain region 22 and the fourth source / drain region 23 are not in contact with or in contact with the insulating buried layer 102.

[0054] A second gate dielectric layer 211 is formed between the second gate structure 21 and the second body region 241 .

[0055] The second gate dielectric layer 211 may be a single-layer structure or a structure of at least two stacked layers. The material of the second gate dielectric layer 211 may include at least one of insulating materials such as silicon oxide and high-K (relative dielectric constant) dielectric, where high-K dielectric refers to a material with a relative dielectric constant greater than silicon oxide. The inclusion of high-K dielectric in the second gate dielectric layer 211 can reduce the risk of leakage.

[0056] In one embodiment, the second gate dielectric layer 211 includes a silicon oxide layer and a high-K dielectric layer stacked from bottom to top.

[0057] The second gate structure 21 may be made of metal, polysilicon or other materials.

[0058] In one embodiment, the material of the second gate structure 21 is polysilicon, and when the second gate dielectric layer 211 contains a high-K dielectric, a cap layer (not shown) is further formed between the second gate structure 21 and the second gate dielectric layer 211. The cap layer is used to separate the polysilicon from the high-K dielectric to prevent performance from being affected, such as preventing the Fermi Level Pinning effect from occurring and causing an increase in the operating voltage.

[0059] The second gate structure 21 is in a T-type or H-type shape, and the third source / drain region 22 and the fourth source / drain region 23 are located in the second body region 241 on both sides of the “|” portion of the T-type or the “-” portion of the H-type.

[0060] The capacitor structure also includes: a second body contact region 24, which is formed in the second body region 241 at the “-” portion of the T-type away from the third source / drain region 22 and the fourth source / drain region 23, or, is formed in the second body region 241 at the “|” portion of the H-type away from the third source / drain region 22 and the fourth source / drain region 23.

[0061] In the second gate structure 21, the T-shaped “|” portion or the H-shaped “-” portion acts as a gate, and the T-shaped “-” portion or the H-shaped “|” portion serves to isolate the third source / drain region 22 and the fourth source / drain region 23 from the second body contact region 24, respectively.

[0062] The capacitor structure also includes: a conductive structure, including a conductive interconnect structure 34 and a conductive plug 33. The conductive plug 33 is formed on the third source / drain region 22, the fourth source / drain region 23, the second gate structure 21 and the second body contact region 24. The conductive plug 33 on the third source / drain region 22 is electrically connected to other structures through the conductive interconnect structure 34, the conductive plug 33 on the fourth source / drain region 23 is electrically connected to other structures through the conductive interconnect structure 34, and the conductive plug 33 on the second gate structure 21 and the second body contact region 24 are both electrically connected through the conductive interconnect structure 34.

[0063] From the above content, it can be seen that in the capacitor structure provided by the present invention, since the third source / drain region 22 and the fourth source / drain region 23 form a depletion layer 25 with the second body region 241, the width of the depletion layer 25 changes with the change of the potential difference applied to the second body region 241 and the second gate structure 21, so that the capacitor formed by the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25 has an adjustable capacitance value, thereby enabling the capacitor to meet different design requirements of the device, without setting up multiple capacitors to meet different design requirements of the device, avoiding the capacitor occupying a large area and saving research and development costs.

[0064] An embodiment of the present invention provides a method for controlling a capacitor structure, including:

[0065] The capacitor structure is provided. The composition of the capacitor structure can be found in the above content and will not be repeated here.

[0066] A potential difference is applied to the capacitive structure so that a capacitor in the capacitive structure has an adjustable capacitance value.

[0067] Among them, applying a potential difference to the capacitor structure includes: applying a potential difference to the second body region and the second gate structure so that the width of the depletion layer changes, thereby changing the capacitance value of the capacitor, that is, the capacitor has an adjustable capacitance value, so that the capacitor can meet different design requirements of the device, and there is no need to set up multiple capacitors to meet different design requirements of the device, thereby avoiding the capacitor occupying a large area and saving R&D costs.

[0068] Applying the desired potential difference to the second body region and the second gate structure may include: applying a voltage to one of the second body region and the second gate structure and grounding or floating the other, or applying a voltage to both the second body region and the second gate structure.

[0069] An embodiment of the present invention provides a semiconductor device, comprising: a transistor, comprising a first source / drain region, a second source / drain region and a first gate structure; a capacitor, wherein the capacitor has an adjustable capacitance value and is connected between the first source / drain region and the first gate structure.

[0070] See below Figure 1 to Figure 3 The semiconductor device provided by this embodiment is introduced in more detail.

[0071] The transistor M1 includes a first source / drain region 12 (eg Figure 3 S in), the second source / drain region 13 (e.g. Figure 3 D) and the first gate structure 11 (such as Figure 3 In G), the first gate structure 11 is formed on the substrate 10, and the first source / drain region 12 and the second source / drain region 13 are formed in the substrate 10 on both sides of the first gate structure 11.

[0072] The semiconductor device further includes a first body region (not shown) formed in the substrate 10, the first gate structure 11 is formed on the first body region, and the first source / drain region 12 and the second source / drain region 13 are formed in the first body region on both sides of the first gate structure 11. The first body region is a well region formed by ion implantation into the substrate 10, and the first body region is used to separate the first source / drain region 12 and the second source / drain region 13.

[0073] The doping types of the first source / drain region 12 and the second source / drain region 13 are opposite to the doping type of the first body region. When the doping types of the first source / drain region 12 and the second source / drain region 13 are N-type and the doping type of the first body region is P-type, the transistor M1 is an NMOS transistor; when the doping types of the first source / drain region 12 and the second source / drain region 13 are P-type and the doping type of the first body region is N-type, the transistor M1 is a PMOS transistor.

[0074] The capacitor C1 has an adjustable capacitance value and is connected between the first source / drain region 12 and the first gate structure 11 .

[0075] The semiconductor device further includes a second body region 241 and a second gate structure 21, wherein the second body region 241 is formed in the substrate 10, and the second gate structure 21 is formed on the second body region 241. The second body region 241 is a well region formed by ion implantation into the substrate 10, and the second body region 241 is used to separate the third source / drain region 22 and the fourth source / drain region 23.

[0076] The capacitor C1 includes a third source / drain region 22, a fourth source / drain region 23 and a depletion layer 25. The third source / drain region 22 and the fourth source / drain region 23 are formed in the second body region 241 on both sides of the second gate structure 21. The doping types of the third source / drain region 22 and the fourth source / drain region 23 are opposite to the doping type of the second body region 241, so that the depletion layer 25 is formed between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241.

[0077] The depletion layer 25 is formed by applying a potential difference between the second body region 241 and the second gate structure 21 .

[0078] The substrate 10 may be made of any suitable material known to those skilled in the art.

[0079] The substrate 10 may be a bulk substrate or a SOI (Semiconductor On Insulator) substrate. The bulk substrate may be, for example, a commonly used substrate in the semiconductor field such as silicon, germanium, GaN, etc. The SOI substrate may be, for example, a silicon on insulator or a germanium on insulator substrate. The SOI substrate includes, from bottom to top, a lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103.

[0080] In one embodiment, when the substrate 10 is a bulk substrate, if the second body region 241 and the substrate 10 around it have the same doping type, a doping region (not shown) is further formed around the second body region 241 (i.e., the lower surface and side surfaces of the second body region 241) to wrap the second body region 241. The doping region has an opposite doping type to the second body region 241, and the doping region is used to separate the second body region 241 from the substrate 10 around it, so that voltage can be applied to the second body region 241 separately.

[0081] When the substrate 10 is an SOI substrate, the first source / drain region 12 and the second source / drain region 13 can be formed in a partial thickness or a full thickness of the semiconductor layer 103, so that the lower surfaces of the first source / drain region 12 and the second source / drain region 13 are not in contact with or in contact with the buried insulating layer 102; the third source / drain region 22 and the fourth source / drain region 23 can be formed in a partial thickness (such as Figure 2 As shown) or in the semiconductor layer 103 of the entire thickness, so that the lower surfaces of the third source / drain region 22 and the fourth source / drain region 23 are not in contact with or in contact with the insulating buried layer 102.

[0082] The doping type of the first source / drain region 12 and the second source / drain region 13 is the same as the doping type of the third source / drain region 22 and the fourth source / drain region 23 , and the doping type of the first body region is the same as the doping type of the second body region 241 .

[0083] A first gate dielectric layer (not shown) is formed between the first gate structure 11 and the first body region, and a second gate dielectric layer 211 is formed between the second gate structure 21 and the second body region 241 .

[0084] In one embodiment, the first gate dielectric layer and the second gate dielectric layer 211 are located at the same layer, and the first gate structure 11 and the second gate structure 21 are located at the same layer.

[0085] The first gate dielectric layer and / or the second gate dielectric layer 211 may be a single-layer structure or a structure of at least two stacked layers. The material of the first gate dielectric layer and / or the second gate dielectric layer 211 may include at least one of insulating materials such as silicon oxide and high-K (relative dielectric constant) dielectric, where high-K dielectric refers to a material with a relative dielectric constant greater than silicon oxide. The inclusion of high-K dielectric in the first gate dielectric layer and / or the second gate dielectric layer 211 can reduce the risk of leakage.

[0086] In one embodiment, the first gate dielectric layer and / or the second gate dielectric layer 211 includes a silicon oxide layer and a high-K dielectric layer stacked from bottom to top.

[0087] The material of the first gate structure 11 may include metal or polysilicon, and the material of the second gate structure 21 may include metal or polysilicon.

[0088] In one embodiment, when the material of the first gate structure 11 and / or the second gate structure 21 is polysilicon and the first gate dielectric layer and / or the second gate dielectric layer 211 contains a high-K dielectric, a cap layer (not shown) is further formed between the first gate structure 11 and the first gate dielectric layer and / or between the second gate structure 21 and the second gate dielectric layer 211, and the cap layer is used to separate the polysilicon from the high-K dielectric to prevent performance from being affected, for example, to prevent the Fermi Level Pinning effect from occurring and causing an increase in the operating voltage.

[0089] The first gate structure 11 and the second gate structure 21 are in a T-type or H-type shape, the first source / drain region 12 and the second source / drain region 13 are located in the first body region on both sides of the “|” portion of the T-type or the “-” portion of the H-type, and the third source / drain region 22 and the fourth source / drain region 23 are located in the second body region 241 on both sides of the “|” portion of the T-type or the “-” portion of the H-type.

[0090] The semiconductor device further comprises:

[0091] A first body contact region 14 is formed in the first body region at a T-shaped “-” portion away from the first source / drain region 12 and the second source / drain region 13, or formed in the first body region at a H-shaped “|” portion away from the first source / drain region 12 and the second source / drain region 13;

[0092] The second body contact region 24 is formed in the second body region 241 at the “-” portion of the T-type away from the third source / drain region 22 and the fourth source / drain region 23, or is formed in the second body region 241 at the “|” portion of the H-type away from the third source / drain region 22 and the fourth source / drain region 23.

[0093] In the first gate structure 11 and the second gate structure 21, the T-shaped “|” portion or the H-shaped “-” portion plays the role of the gate of the semiconductor device; in the first gate structure 11, the T-shaped “-” portion or the H-shaped “|” portion plays the role of isolating the first source / drain region 12 and the second source / drain region 13 from the first body contact region 14, respectively; in the second gate structure 21, the T-shaped “-” portion or the H-shaped “|” portion plays the role of isolating the third source / drain region 22 and the fourth source / drain region 23 from the second body contact region 24, respectively.

[0094] The capacitance structure includes the capacitor C1 , the second body region 241 , the second gate structure 21 , the second gate dielectric layer 211 and the second body contact region 24 .

[0095] The semiconductor device further includes a shallow trench isolation structure (not shown) formed in the substrate 10 , and the shallow trench isolation structure is used to isolate the transistor M1 from the capacitor structure.

[0096] The third source / drain region 22 is electrically connected to the first gate structure 11, and the fourth source / drain region 23 is electrically connected to the first source / drain region 12; because the doping types of the third source / drain region 22 and the fourth source / drain region 23 are opposite to the doping type of the second body region 241, a depletion layer 25 is formed between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241, and the width W of the depletion layer 25 changes with the change of the potential difference applied to the second body region 241 and the second gate structure 21, thereby causing the capacitance value of the capacitor C1 formed by the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25 to change.

[0097] The third source / drain region 22 and the fourth source / drain region 23 serve as two plates of the capacitor C1, and the dielectric layer between the two plates includes the depletion layer 25. The change in the width W of the depletion layer 25 is the change in the thickness of the dielectric layer. The thickness of the dielectric layer changes with the change in the potential difference applied to the second body region 241 and the second gate structure 21. Therefore, the capacitance value of the capacitor C1 can change with the change in the potential difference applied to the second body region 241 and the second gate structure 21. In one embodiment, the greater the potential difference, the greater the width W of the depletion layer 25.

[0098] When the semiconductor device is working, in addition to applying a required voltage to the transistor M1 to make the transistor M1 work, a required potential difference is also applied to the second body region 241 and the second gate structure 21 in the capacitor structure so that the capacitor C1 in the capacitor structure has a required capacitance value.

[0099] Wherein, applying voltage to the transistor M1 includes: applying voltage and / or grounding the first gate structure 11, the first body region (the first body contact region 14), the first source / drain region 12, and the second source / drain region 13. For example, a positive voltage or a negative voltage is applied to the first gate structure 11, the first body region (the first body contact region 14) is grounded, and the first source / drain region 12 and the second source / drain region 13 can be used as input and output of electrical signals. In one embodiment, when the semiconductor device is a radio frequency device, the first source / drain region 12 and the second source / drain region 13 can be used as input and output of radio frequency signals.

[0100] Applying the required potential difference to the second body region 241 and the second gate structure 21 in the capacitor structure may include: applying a voltage to one of the second body region 241 and the second gate structure 21 and grounding or floating the other, or applying a voltage to both the second body region 241 and the second gate structure 21.

[0101] It should be noted that, since the third source / drain region 22 is electrically connected to the first gate structure 11, and the fourth source / drain region 23 is electrically connected to the first source / drain region 12, when a voltage is applied to the first gate structure 11 and the first source / drain region 12 in the transistor M1 or when grounding is performed, it is equivalent to applying a voltage to the third source / drain region 22 and the fourth source / drain region 23 or when grounding is performed. Therefore, when a voltage is applied to the second body region 241, it is necessary to consider preventing a positive bias from occurring between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241, that is, preventing the PN junction formed by the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241 from being turned on, thereby preventing the capacitor structure from becoming a resistor structure, thereby preventing the first source / drain region 12 in the transistor M1 from being turned on with the first gate structure 11. For example, when the doping type of the third source / drain region 22 and the fourth source / drain region 23 is P type and the doping type of the second body region 241 is N type, a positive voltage cannot be applied to the third source / drain region 22 and the fourth source / drain region 23 and a negative voltage cannot be applied to the second body region 241, that is, a forward bias cannot be applied; instead, a negative voltage needs to be applied to the third source / drain region 22 and the fourth source / drain region 23 and a positive voltage or grounding needs to be applied to the second body region 241, or, the third source / drain region 22 and the fourth source / drain region 23 are grounded and a positive voltage is applied to the second body region 241, that is, a reverse bias is applied to the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241. Therefore, when the doping type of the third source / drain region 22 and the fourth source / drain region 23 is P-type, only a positive voltage or grounding can be applied to the second body region 241; when the doping type of the third source / drain region 22 and the fourth source / drain region 23 is N-type, only a negative voltage or grounding can be applied to the second body region 241.

[0102] In one embodiment, the first source / drain region 12 is a source region, and the second source / drain region 13 is a drain region. In this case, the third source / drain region 22 is a source region, and the fourth source / drain region 23 is a drain region; or, the fourth source / drain region 23 is a source region, and the third source / drain region 22 is a drain region.

[0103] In one embodiment, the semiconductor device further includes:

[0104] The first resistor R G , electrically connected to the first gate structure 11; and / or,

[0105] The second resistor R SD , electrically connected between the first source / drain region 12 and the second source / drain region 13.

[0106] The first resistor R G The first insulating layer (not shown) and the first conductive structure 31 are formed on the substrate 10 from bottom to top, and the second resistor R SD The second insulating layer 32 is formed on the substrate 10 from bottom to top.

[0107] In one embodiment, the first insulating layer and the second insulating layer are located at the same layer, and the first conductive structure 31 and the second conductive structure 32 are located at the same layer.

[0108] The first conductive structure 31 may be made of metal or polysilicon, and the second conductive structure 32 may be made of metal or polysilicon.

[0109] The first resistor R G and the second resistor R SD As a load, for voltage stabilization. In other embodiments, the semiconductor device may not include the first resistor R G and the second resistor R SD .

[0110] The semiconductor device further comprises:

[0111] A conductive structure, comprising a conductive interconnect structure 34 and a conductive plug 33, wherein the conductive plug 33 is formed on the first source / drain region 12, the second source / drain region 13, the first gate structure 11, the third source / drain region 22, the fourth source / drain region 23 and the second gate structure 21, the conductive plug 33 on the third source / drain region 22 is electrically connected to the conductive plug 33 on the first gate structure 11 through the conductive interconnect structure 34, the conductive plug 33 on the fourth source / drain region 23 is electrically connected to the conductive plug 33 on the first source / drain region 12 through the conductive interconnect structure 34, and the conductive plug 33 on the second gate structure 21 is electrically led out through the conductive interconnect structure 34.

[0112] The conductive plugs 33 are also formed on the first body contact region 14 and the second body contact region 24 , so that the conductive plugs 33 on the first body contact region 14 and the second body contact region 24 can be electrically led out through the conductive interconnection structure 34 , respectively.

[0113] The conductive plugs 33 are also formed on both ends of the first conductive structure 31, so that the conductive plug 33 on one end of the first conductive structure 31 can be electrically connected to the conductive plug 33 on the first gate structure 11 through the conductive interconnection structure 34, and the conductive plug 33 on the other end of the first conductive structure 31 can be electrically led out through the conductive interconnection structure 34; the conductive plugs 33 are also formed on both ends of the second conductive structure 32, so that the conductive plugs 33 on both ends of the second conductive structure 32 can be electrically connected to the conductive plugs 33 on the first source / drain region 12 and the second source / drain region 13 respectively through the conductive interconnection structure 34.

[0114] From the above content, it can be seen that in the semiconductor device provided by the invention, since the capacitor C1 with an adjustable capacitance value is connected between the first source / drain region 12 and the first gate structure 11 in the transistor M1, the capacitor C1 can meet different design requirements of the transistor M1, and there is no need to set up multiple capacitors to meet different design requirements of the device, which avoids the capacitor occupying a large area and saves research and development costs.

[0115] In one embodiment, the doping types of the third source / drain region 22 and the fourth source / drain region 23 in the capacitor C1 are opposite to the doping type of the second body region 241, so that a depletion layer 25 is formed between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241, and the width of the depletion layer 25 changes with the change of the potential difference applied to the second body region 241 and the second gate structure 21, thereby causing the capacitance value of the capacitor C1 formed by the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25 to change. Therefore, by adjusting the potential difference applied to the second body region 241 and the second gate structure 21, the capacitor C1 can have multiple different capacitance values, that is, the capacitor C1 set between the first source / drain region 12 and the first gate structure 11 in the transistor M1 has an adjustable capacitance value.

[0116] When the semiconductor device is a radio frequency switch device, since the capacitor C1 has an adjustable capacitance value, the voltage regulation of the radio frequency switch device is more flexible.

[0117] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A capacitor structure, characterized in that: include: a substrate having a second body region formed therein; A capacitor comprises a third source / drain region, a fourth source / drain region and a depletion layer, wherein the third source / drain region and the fourth source / drain region are formed in the second body region at intervals, and the doping types of the third source / drain region and the fourth source / drain region are opposite to the doping type of the second body region, so that the depletion layer can be formed between the third source / drain region and the fourth source / drain region and the second body region.

2. The capacitor structure according to claim 1, characterized in that: The capacitor structure also includes a second gate structure, which is formed on the second body region between the third source / drain region and the fourth source / drain region; the width of the depletion layer changes with the potential difference applied to the second body region and the second gate structure, so that the capacitance value of the capacitor changes.

3. The capacitor structure according to claim 2, characterized in that: The second gate structure is in a T-type or H-type shape, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the "|" portion of the T-type or the "-" portion of the H-type.

4. The capacitor structure according to claim 3, characterized in that: The capacitor structure further includes: The second body contact region is formed in the second body region on the side of the "-" portion of the T-type away from the third source / drain region and the fourth source / drain region, or is formed in the second body region on the side of the "|" portion of the H-type away from the third source / drain region and the fourth source / drain region.

5. A method for controlling a capacitor structure, characterized in that: include: Providing a capacitor structure as claimed in any one of claims 1 to 4; A potential difference is applied to the capacitive structure so that a capacitor in the capacitive structure has an adjustable capacitance value.

6. The control method of the capacitor structure according to claim 5, characterized in that: The capacitor structure further includes a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region; Applying a potential difference to the capacitive structure comprises: A potential difference is applied to the second body region and the second gate structure, so that the width of the depletion layer changes, thereby changing the capacitance value of the capacitor.

7. A semiconductor device, characterized in that: include: A transistor comprising a first source / drain region, a second source / drain region and a first gate structure; A capacitor having an adjustable capacitance value is connected between the first source / drain region and the first gate structure.

8. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a substrate, the first gate structure is formed on the substrate, and the first source / drain region and the second source / drain region are formed in the substrate on both sides of the first gate structure.

9. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises a substrate, in which a second body region is formed; the capacitor comprises a third source / drain region, a fourth source / drain region and a depletion layer, the third source / drain region and the fourth source / drain region are alternately formed in the second body region, and the doping types of the third source / drain region and the fourth source / drain region are opposite to the doping type of the second body region, so that the depletion layer can be formed between the third source / drain region and the fourth source / drain region and the second body region; The third source / drain region is electrically connected to the first gate structure, and the fourth source / drain region is electrically connected to the first source / drain region.

10. The semiconductor device according to claim 9, wherein: The semiconductor device further includes a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region.

11. The semiconductor device according to claim 10, wherein: The width of the depletion layer changes with the change of the potential difference applied to the second body region and the second gate structure, so that the capacitance value of the capacitor changes.

12. The semiconductor device according to claim 7, wherein: The first source / drain region is a source region, and the second source / drain region is a drain region.

13. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises: a first resistor, electrically connected to the first gate structure; and / or, The second resistor is electrically connected between the first source / drain region and the second source / drain region.

14. The semiconductor device according to claim 9, wherein The doping type of the first source / drain region and the second source / drain region is the same as the doping type of the third source / drain region and the fourth source / drain region.

15. The semiconductor device according to claim 10, wherein: The first gate structure and the second gate structure are in the shape of T-type or H-type, the first source / drain region and the second source / drain region are located in the substrate on both sides of the "|" part of the T-type or the "-" part of the H-type, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the "|" part of the T-type or the "-" part of the H-type.

16. The semiconductor device according to claim 15, wherein: The semiconductor device further comprises: A first body region is formed in the substrate, the first gate structure is formed on the first body region, and the first source / drain region and the second source / drain region are formed in the first body region on both sides of the "|" portion of the T-type or the "-" portion of the H-type; A first body contact region is formed in the first body region at a side of the T-shaped “-” portion away from the first source / drain region and the second source / drain region, or is formed in the first body region at a side of the H-shaped “|” portion away from the first source / drain region and the second source / drain region; The second body contact region is formed in the second body region on the side of the "-" portion of the T-type away from the third source / drain region and the fourth source / drain region, or is formed in the second body region on the side of the "|" portion of the H-type away from the third source / drain region and the fourth source / drain region.

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