Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and can improve the capacitance density of a capacitor in the semiconductor structure, reduce the occupied area of the capacitor and reduce the size of the semiconductor structure. A device stack in the semiconductor structure includes a capacitor and a transistor. The transistor comprises an epitaxial layer, a dielectric layer and a conductive layer. The epitaxial layer is configured as a first polar plate layer of the capacitor; the epitaxial layer is located between the adjacent first isolation structure and second isolation structure, and / or between two adjacent second isolation structures. The dielectric layer is configured as an intermediate dielectric layer between two polar plate layers of the capacitor; the dielectric layer wraps the epitaxial layer and covers the second isolation structure; the surface of one side, away from the semiconductor substrate, of the part, covering the second isolation structure, of the dielectric layer is represented as a groove. The conductive layer is configured as a second pole plate layer of the capacitor; the conductive layer covers the dielectric layer and is filled in the groove.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the technological development of the semiconductor industry, the density of semiconductor devices per unit area is getting higher and higher, and the size of semiconductor devices is constantly shrinking. In a semiconductor structure (such as an integrated circuit) formed by multiple semiconductor elements (such as transistors and capacitors), improving the performance of each semiconductor element has always been an important research direction in the industry. For example, the research on the capacitance density of MOS capacitors and the occupied area of ​​capacitors. As a result, the complexity and process cost of the preparation process of MOS capacitors formed based on the structure of transistors are also the focus of the research process. Summary of the invention

[0003] In view of this, a semiconductor structure and a preparation method thereof provided in an embodiment of the present application can improve the capacitance density of the capacitor in the semiconductor structure, reduce the occupied area of ​​the capacitor, reduce the size of the semiconductor structure, and also reduce the complexity and cost of the manufacturing process of the semiconductor structure.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] On the one hand, an embodiment of the present application provides a semiconductor structure. The semiconductor structure includes: a semiconductor substrate and a device stack. The semiconductor substrate includes a first isolation structure and at least one second isolation structure arranged in an area surrounded by the first isolation structure; the first isolation structure and the second isolation structure are respectively at opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located, one end is exposed from the same side surface of the semiconductor substrate, and the other end is located in the semiconductor substrate.

[0006] The device stack is arranged on one side of the semiconductor substrate, and includes a capacitor and a transistor. The transistor includes: an epitaxial layer, a dielectric layer and a conductive layer.

[0007] The epitaxial layer is disposed on one side surface of the semiconductor substrate and is configured as a first plate layer of the capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures.

[0008] The dielectric layer is arranged on a side of the epitaxial layer away from the semiconductor substrate, and is configured as an intermediate dielectric layer between the two plate layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structure; wherein the surface of the side away from the semiconductor substrate of the portion of the dielectric layer covering the second isolation structure is characterized as a groove.

[0009] The conductive layer is arranged on a side of the dielectric layer away from the semiconductor substrate and is configured as a second plate layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

[0010] In some examples, the first isolation structure surrounds a plurality of second isolation structures arranged at intervals. The second isolation structure is not connected to the first isolation structure; and / or, along a stacking direction perpendicular to the semiconductor substrate and the device stack, one of the opposite ends of the second isolation structure is connected to the first isolation structure; the epitaxial layer is a continuous structure. The conductive layer fills all of the grooves characterized by the surface of the dielectric layer.

[0011] In some examples, the first isolation structure surrounds a plurality of spaced second isolation structures. Along a stacking direction perpendicular to the semiconductor substrate and the device stack, opposite ends of the second isolation structure are connected to the first isolation structure; and the epitaxial layer includes a plurality of spaced epitaxial patterns.

[0012] The dielectric layer covers a plurality of the epitaxial patterns and the second isolation structure between two adjacent epitaxial patterns; and the conductive layer fills all the grooves represented on the surface of the dielectric layer.

[0013] In some examples, the epitaxial layer includes a first electrode region and a second electrode region spaced apart; the first electrode region is coupled to a first transfer structure; and the second electrode region is coupled to a second transfer structure.

[0014] The conductive layer includes a first conductive portion and a second conductive portion connected to each other. The first conductive portion covers the region of the epitaxial layer except for the region coupling the first transfer structure and the second transfer structure. The second conductive portion is disposed on a side of the first isolation structure away from the semiconductor substrate.

[0015] In some examples, the epitaxial layer includes a plurality of spaced epitaxial patterns; the first electrode region includes first sub-electrode regions respectively located in different epitaxial patterns, and the second electrode region includes second sub-electrode regions respectively located in different epitaxial patterns. One first sub-electrode region is coupled to one first switching structure, and the first sub-electrode regions of the plurality of epitaxial patterns are coupled to each other through the plurality of first switching structures. One second sub-electrode region is coupled to one second switching structure, and the second sub-electrode regions of the plurality of epitaxial patterns are coupled to each other through the plurality of second switching structures.

[0016] In some examples, a dimension of the first isolation structure along a direction perpendicular to a plane where the semiconductor substrate is located is greater than a dimension of the second isolation structure along a direction perpendicular to a plane where the semiconductor substrate is located;

[0017] One of the first isolation structures encloses a device region; the semiconductor structure includes a plurality of the device regions, and two adjacent device regions share part of the first isolation structure.

[0018] In some examples, the semiconductor substrate includes a silicon-on-insulator layer.

[0019] In the above semiconductor structure, an epitaxial layer is arranged on one side of the semiconductor substrate, and the epitaxial layer can be used as an active layer of a transistor structure. That is to say, from the perspective of the manufacturing process of the semiconductor structure, the epitaxial layer is made after the semiconductor substrate is formed, rather than using part of the material of the semiconductor substrate as the epitaxial layer in the process of manufacturing the semiconductor substrate. The manufacturing process of the epitaxial layer obtained in this way is simple and the process cost is low. Based on arranging transistors and capacitors on such a semiconductor substrate. Among them, the epitaxial layer (active layer of the transistor) serves as the first plate layer of the capacitor, and the conductive layer (gate layer of the transistor) serves as the second plate layer of the capacitor. In this way, without increasing the thickness of the dielectric layer, that is, without affecting the control ability of the gate of the transistor to the channel region, the epitaxial layer formed based on the multiple spaced second isolation structures can characterize multiple grooves on the surface of the dielectric layer, and the conductive layer can extend continuously along the side edge of the epitaxial layer to cover the area with the grooves. In this way, a part of the conductive layer is also arranged on the side wall of the epitaxial layer, increasing the relative area between the epitaxial layer and the conductive layer, and increasing the capacitance of the capacitor; and, when the capacitance remains unchanged, the occupied area of ​​a capacitor can be reduced, the size of the semiconductor structure can be reduced, and the capacitance density of the semiconductor structure can be improved.

[0020] On the other hand, the present application also provides a method for preparing a semiconductor structure. The preparation method includes forming a semiconductor substrate; the semiconductor substrate includes a first isolation structure and at least one second isolation structure disposed in an area surrounded by the first isolation structure; one end of the first isolation structure and the second isolation structure at opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located is exposed from the same side surface of the semiconductor substrate, and the other end is located inside the semiconductor substrate.

[0021] An epitaxial layer is formed on one side surface of the semiconductor substrate; the epitaxial layer is configured as a first plate layer of a capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures.

[0022] A dielectric layer is formed on a side of the epitaxial layer away from the semiconductor substrate; the dielectric layer is configured as an intermediate dielectric layer between two plate layers of the capacitor; the dielectric layer encapsulates the epitaxial layer and covers the second isolation structure; wherein a surface of a side away from the semiconductor substrate of a portion of the dielectric layer covering the second isolation structure is characterized as a groove.

[0023] A conductive layer is formed on a side of the dielectric layer away from the semiconductor substrate, and the conductive layer is configured as a second plate layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

[0024] In some examples, the forming of the semiconductor substrate includes: forming a first trench and at least one second trench located in an area surrounded by the first trench on an initial semiconductor substrate; the depth of the first trench is greater than the depth of the second trench; the first trench surrounds the second trench. At least one of the two opposite ends of the second trench along a direction perpendicular to the plane where the semiconductor substrate is located is connected to the first trench; or the second trench is spaced apart from the first trench. Dielectric material is deposited in the first trench and the second trench to form the first isolation structure and the second isolation structure to obtain the semiconductor substrate.

[0025] In some examples, the forming of the semiconductor substrate includes: forming an epitaxial layer including a plurality of spaced epitaxial patterns; or forming an epitaxial layer in a continuous structure; the epitaxial layer includes a first electrode region and a second electrode region spaced apart. A first transfer structure coupled to the first electrode region and a second transfer structure coupled to the second electrode region are formed. The conductive layer covers the epitaxial layer except for the region where the first transfer structure and the second transfer structure are coupled.

[0026] The method for preparing the semiconductor structure mentioned above prepares a semiconductor structure as provided in any of the above examples. The technical effect achieved by the method for preparing the semiconductor structure mentioned above is the same as the technical effect of the semiconductor structure provided in any of the above examples, which will not be repeated here. Moreover, in the process of preparing transistors and capacitors by the method for preparing the semiconductor structure provided in any of the above examples, a process of growing an epitaxial layer on a semiconductor substrate is adopted. Compared with the method of increasing the trench depth in the related art, the process difficulty of making the active layer of the transistor can be reduced, the process cost can be reduced, and it can be integrated into the current process of manufacturing the semiconductor structure, and has high compatibility.

[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic top view of a semiconductor structure provided in one embodiment of the present application;

[0029] Figure 2 A schematic top view of a capacitor of a semiconductor structure provided in one embodiment of the present application Figure 1 ;

[0030] Figure 3 A schematic top view of a capacitor of a semiconductor structure provided in one embodiment of the present application Figure 2 ;

[0031] Figure 4 A schematic top view of a capacitor of a semiconductor structure provided in one embodiment of the present application Figure 3 ;

[0032] Figure 5 A schematic top view of a capacitor of a semiconductor structure provided in one embodiment of the present application Figure 4 ;

[0033] Figure 6 for Figure 2 A schematic cross-sectional view of a semiconductor structure along the BB direction is provided;

[0034] Figure 7 for Figure 2 A schematic cross-sectional view of a semiconductor structure along the AA direction is provided;

[0035] Figure 8 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0036] Fig. 9 (a)~ Fig. 9 (g) is a schematic structural cross-sectional diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0037] Fig.10 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0038] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0039] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0040] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0042] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0045] With the technological development of the semiconductor industry, the density of semiconductor devices per unit area is getting higher and higher, and the size of semiconductor devices is shrinking. In integrated circuit (IC) devices formed by multiple semiconductor elements (such as transistors and capacitors), improving the performance of each semiconductor element has always been an important research direction in the industry.

[0046] For example, capacitors may include plate (Metal-Insulator-Metal, MIM) capacitors, finger-insertion (Metal-Oxide-Metal, MOM) capacitors and field effect (Metal-Oxide-Semiconductor, MOS) capacitors. Among them, MOS capacitors are widely used due to their compatibility of preparation process, simple structural design, and small occupied area.

[0047] How to further improve the capacitance density of MOS capacitors and reduce the occupied area of ​​MOS capacitors is one of the important research directions at present. As a result, the complexity and process cost of the preparation process of MOS capacitors formed based on the structure of transistors are also the focus of the research process.

[0048] Based on this, the embodiments of the present application provide a semiconductor structure and a method for preparing the same, which can increase the capacitance density of the MOS capacitor in the semiconductor structure, reduce the occupied area of ​​the MOS capacitor, reduce the size of the semiconductor structure, and also reduce the complexity and cost of the manufacturing process of the semiconductor structure.

[0049] In some embodiments, Figure 1 to Figure 7As shown, an embodiment of the present application provides a semiconductor structure 100. For example, the semiconductor structure 100 can be a chip (Chip), a die (Die), or a wafer (Wafer). It should be noted that the chip (Chip) and the die (Die) can refer to the same structure (the names can be interchangeable), or the die can be a chip that is not packaged. Different levels of chip structures are set according to requirements. For example, the chip Chip, the die Die and the wafer Wafer are three different levels of chip structures. The embodiments provided in the present application are not limited to this, and any semiconductor structure formed with transistors can be implemented using the technology provided in the present application. Subsequent examples all use "semiconductor structure" for illustrative purposes.

[0050] In some examples, such as Figure 1 As shown, the semiconductor structure 100 includes a semiconductor substrate 110 and a device stack 120 . The device stack 120 is disposed on one side of the semiconductor substrate 110 .

[0051] For example, the semiconductor substrate 110 may be a composite layer structure of a multilayer dielectric material and a conductive material including a circuit structure. For example, the semiconductor substrate 110 may include a silicon on insulator (SOI) layer.

[0052] For example, the device stack 120 may include a plurality of transistors. The transistor may include a field-effect transistor (FET). FET includes other transistors such as a metal oxide semiconductor field effect transistor (MOSFET) and a silicon on insulator field effect transistor (SOI FET), which is not specifically limited in the present application and may be set as required. For example, the semiconductor substrate 110 is made of SOI material, and the device stack 120 formed on the semiconductor substrate 110 may include an SOI FET transistor. Among them, the active layer, gate dielectric layer, and gate layer of the field effect transistor may form a MOS capacitor.

[0053] like Figure 1 As shown, the device stack 120 can be divided into a plurality of device regions N, and a plurality of transistors T can be arranged in one device region N, or a single transistor T can be arranged. A MOS capacitor can be formed by a transistor partial layer. The number of transistors T in one device region N can be adjusted under the condition that the control capability of the gate of the transistor T over the channel region is satisfied.

[0054] It should be noted that the "device area" defined in this application is not limited to a specific physical structure, but includes an area of ​​electronic components, which can be divided according to actual conditions, and this application does not impose specific restrictions. In addition, the area size of the device area N can also be adjusted according to the size of the actual semiconductor structure 100. The area sizes of different device areas N can be different, and the number of transistors T in different device areas N can be different. For example, Figure 1 A transistor and a MOS capacitor composed of a partial layer of this transistor can be set in a device area N shown. The MOS capacitor C obtained in this application based on the layer structure of the transistor T mainly sets the structural features of the active layer (i.e., the epitaxial layer mentioned in the subsequent examples, as one plate layer of the capacitor) and the gate layer (i.e., the conductive layer mentioned in the subsequent examples, as another plate layer of the capacitor) of the transistor T without affecting the performance of the transistor, and exemplifies the influence of the relative area size of the two plate layers of the capacitor on the capacitance density and occupied area. The following example is exemplified by the layer structure of the semiconductor structure 100 in a device area N.

[0055] In some examples, such as Figure 1 As shown, the semiconductor substrate 110 includes a first isolation structure 111 and at least one second isolation structure 112 disposed in the area surrounded by the first isolation structure 111. One first isolation structure 111 surrounds one device region N. The semiconductor structure 100 includes a plurality of device regions N, and two adjacent device regions N share part of the first isolation structure 111.

[0056] For example, Figure 2 to Figure 5 As shown, the second isolation structure 112 is not connected to the first isolation structure 111; and / or, along a direction (X or Y) perpendicular to the stacking direction of the semiconductor substrate 110 and the device stack 120, at least one of the two opposite ends of the second isolation structure 112 is connected to the first isolation structure 111. In the following examples, the structures and effects of the epitaxial layer 121, the dielectric layer 122, and the conductive layer 123 are exemplified in combination with the structures of the first isolation structure 111 and the second isolation structure 112.

[0057] For example, Figure 6 As shown, the first isolation structure 111 and the second isolation structure 112 both extend in a direction perpendicular to the plane where the semiconductor substrate 110 is located. In addition, one end of the first isolation structure 111 and the second isolation structure 112 at opposite ends along the direction perpendicular to the plane where the semiconductor substrate 110 is located is exposed from the same side surface of the semiconductor substrate 110, and the other end is located in the semiconductor substrate 110.

[0058] Continue reading Figure 6The first isolation structure 111 may be a shallow trench isolation (STI) structure, and the STI is used to separate the device regions N where different transistors are located (see Figure 1 ). For example, multiple transistors that achieve the same functional effect can be divided into the same device area N, and STI can reduce the interference between transistors T in different device areas N when achieving different functions.

[0059] Furthermore, the second isolation structure 112 may be located within the area enclosed by the first isolation structure 111, and Figure 6 As shown, along the direction Z perpendicular to the plane where the semiconductor substrate 110 is located, the size of the second isolation structure 112 is smaller than the size of the first isolation structure 111, and the second isolation structure 112 is used to separate the active layers of different transistors in the area enclosed by the first isolation structure 111 (i.e., the epitaxial layer 121 mentioned in subsequent examples).

[0060] For example, the materials used for the first isolation structure 111 and the second isolation structure 112 may include oxide insulating materials.

[0061] In some examples, such as Figures 1 to 8 As shown, the device stack 120 is disposed on one side of the semiconductor substrate 110 , and includes a MOS capacitor C and a transistor T.

[0062] like Figure 6 As shown, the transistor T includes an epitaxial layer 121, a dielectric layer 122 and a conductive layer 123. The epitaxial layer 121 is disposed on a surface of a semiconductor substrate 110, configured as an active layer of the transistor T, and as a first plate layer of the capacitor C.

[0063] The dielectric layer 122 is disposed on a side of the epitaxial layer 121 away from the semiconductor substrate 110 , and is configured as a gate dielectric layer of the transistor T, and as an intermediate dielectric layer between two plate layers of the capacitor C.

[0064] The conductive layer 123 is disposed on a side of the dielectric layer 122 away from the semiconductor substrate 110 , and is configured as a gate of the transistor and serves as a second plate layer of the capacitor C.

[0065] Continue reading Figure 6 The epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112 , and / or between two adjacent second isolation structures 112 .

[0066] The epitaxial layer 121 may be located between adjacent first isolation structures 111 and second isolation structures 112. For example, a second isolation structure 112 is provided in the region enclosed by the first isolation structure 111 (i.e., in a device region N). Thus, two epitaxial layers 121 may be provided in the region enclosed by the first isolation structure 111, and each epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112.

[0067] Alternatively, the epitaxial layer 121 may be located between two adjacent second isolation structures 112. For example, at least two second isolation structures 112 are provided in the region enclosed by the first isolation structure 111 (i.e., in one device region N). In this way, the epitaxial layer 121 may be provided only in the region between two adjacent second isolation structures 112 in the region enclosed by the first isolation structure 111. The epitaxial layer 121 may not be provided in the region between the adjacent first isolation structures 111 and the second isolation structures 112.

[0068] Or, if Figure 6 As shown, part of the epitaxial layer 121 may be located between adjacent first isolation structures 111 and second isolation structures 112, and the remaining part may be located between two adjacent second isolation structures 112. For example, at least two second isolation structures 112 are provided in the region enclosed by the first isolation structure 111 (i.e., in one device region N). In this way, the epitaxial layer 121 may be provided in the region between two adjacent second isolation structures 112 and in the region between the adjacent first isolation structure 111 and second isolation structure 112 in the region enclosed by the first isolation structure 111.

[0069] Based on the number of the above-mentioned second isolation structures 112 and the connection method with the first isolation structure 111, the surface area of ​​the epitaxial layer 121 can be increased, the area of ​​the subsequent conductive layer 123 can be increased, and the relative area of ​​the two plates of the MOS capacitor C formed by the epitaxial layer 121 and the conductive layer 123 can be increased.

[0070] Continue reading Figure 6 The dielectric layer 122 covers the epitaxial layer 121 and covers the second isolation structure 112. The surface of the dielectric layer 122 covering the second isolation structure 112 and away from the semiconductor substrate 110 represents a groove 1221.

[0071] For example, the material of the dielectric layer 122 includes one or more insulating materials such as silicon oxynitride SiON, silicon oxide SiO2, silicon nitride SiN or silicon carbide SiC. The dielectric layer 122 is used to insulate the epitaxial layer 121 from the conductive layer 123. In this way, the dielectric layer 122 covers the epitaxial layer 121 on the semiconductor substrate 110, which can prevent the epitaxial layer 121 from being directly electrically connected to the subsequently formed conductive layer 123 under the conductive state. Moreover, the dielectric layer 122 extends from the surface of the epitaxial layer 121 to the surface of the second isolation structure 112 and covers the second isolation structure 112, which can prevent the conductive particles in the conductive layer 123 from diffusing into the second isolation structure 112 after the subsequently formed conductive layer 123 contacts the second isolation structure 112, thereby improving the reliability of the conductive layer 123 subsequently formed on the dielectric layer 122.

[0072] Continue reading Figure 6 , the conductive layer 123 covers the dielectric layer 122 and fills the groove 1221 .

[0073] For example, the conductive layer 123 may be a gate of the transistor T. The conductive layer 123 covers the dielectric layer 122, and the dielectric layer 122 serves as a gate dielectric layer between the active layer and the gate layer in the transistor structure, that is, the conductive layer 123 does not contact the epitaxial layer 121. The conductive layer 123 is arranged to extend along the edge of the epitaxial layer 121, which can increase the relative area between the conductive layer 123 and the epitaxial layer 121, and can not only improve the control capability of the conductive layer 123 over the channel region of the epitaxial layer 121, but also can improve the capacitance density of the two plate layers of the MOS capacitor C using the epitaxial layer 121 and the conductive layer 123.

[0074] For example, the material used for the conductive layer 123 may include one or more of a metal element or compound, a semiconductor material or a conductive polymer. For example, the material used for the conductive layer 123 may include one or more of a conductive element or compound such as gold, silver, copper, aluminum, tin, etc.

[0075] It is understandable that the shape and size of the groove 1221 (ie, the shape and size corresponding to the second isolation structure 112 ) can be set according to actual conditions as long as the material of the dielectric layer 122 and the material of the conductive layer 123 can be filled in the groove 1221 .

[0076] In the semiconductor structure 100, an epitaxial layer 121 is provided on one side of the semiconductor substrate 110, and the epitaxial layer 121 can be used as an active layer of a transistor structure. That is to say, from the perspective of the manufacturing process of the semiconductor structure, the epitaxial layer 121 is manufactured after the semiconductor substrate 110 is formed, rather than using part of the material of the semiconductor substrate 110 as the structure of the epitaxial layer 121 during the manufacturing process of the semiconductor substrate 110. The manufacturing process of the epitaxial layer 121 obtained in this way is simple and the process cost is low. Based on setting a transistor T and a MOS capacitor C on such a semiconductor substrate 110. Among them, the epitaxial layer 121 (the active layer of the transistor T) serves as the first plate layer of the MOS capacitor C, and the conductive layer 123 (the gate layer of the transistor T) serves as the second plate layer of the MOS capacitor C.

[0077] In this way, without increasing the thickness of the dielectric layer 122, that is, without affecting the control capability of the gate of the transistor T over the channel region, the epitaxial layer 121 formed based on the plurality of spaced second isolation structures 112 can represent a plurality of grooves on the surface of the dielectric layer 122, and the conductive layer 123 can extend continuously along the side edge of the epitaxial layer 121, covering the region where the dielectric layer 122 is provided with grooves, so that a portion of the conductive layer 123 is also provided on the side wall of the epitaxial layer 121, increasing the relative area between the epitaxial layer 121 and the conductive layer 123, and increasing the capacitance of the MOS capacitor C; and, in the case of unchanged capacitance, the occupied area of ​​a MOS capacitor C can be reduced, the size of the semiconductor structure 100 can be reduced, and the capacitance density of the semiconductor structure 100 can be improved. Moreover, based on the relative position relationship and structure of each layer in the above-mentioned semiconductor structure 100, it can be integrated into the process of the current semiconductor structure manufacturing process, and has high compatibility.

[0078] In some examples, such as Figure 2 and Figure 3 As shown, the second isolation structure 112 is not connected to the first isolation structure 111. The epitaxial layer 121 is a continuous structure. The conductive layer 123 fills all the grooves 1221 represented on the surface of the dielectric layer 122.

[0079] For example, Figure 2 As shown, the first isolation structure 111 surrounds a plurality of spaced second isolation structures 112. One second isolation structure 112 extends along the first direction X, and along the first direction X, the two opposite ends of the second isolation structure 112 are not connected to the first isolation structure 111; the plurality of second isolation structures 112 are arranged in a row along the second direction Y; the second direction Y intersects the first direction X.

[0080] For example, Figure 3As shown, the first isolation structure 111 surrounds a plurality of spaced second isolation structures 112. The plurality of second isolation structures 112 are arranged in a plurality of rows along a first direction X and in a plurality of columns along a second direction Y; the second direction Y intersects the first direction X. The second isolation structure 112 is not connected to the first isolation structure 111.

[0081] Based on the connection relationship between the second isolation structure 112 and the first isolation structure 111, the epitaxial layer 121 is formed into a continuous structure. In this way, the first transfer structure 1241 and the second transfer structure 1242 can be provided one by one in the subsequent provision, thereby reducing the number of provision of transfer structures, reducing process costs and improving the flexibility of manufacturing transfer structures.

[0082] Furthermore, the conductive layer 123 fills all the grooves 1221 on the surface of the dielectric layer 122. The grooves 1221 corresponding to the positions of the second isolation structures 112 can increase the relative area between the conductive layer 123 and the epitaxial layer 121, thereby increasing the capacitance density.

[0083] In other examples, such as Figure 4 As shown, along a stacking direction (X or Y) perpendicular to the semiconductor substrate 110 and the device stack 120 , one of the two opposite ends of the second isolation structure 112 is connected to the first isolation structure.

[0084] The epitaxial layer 121 is a continuous structure. The conductive layer 123 fills all the grooves 1221 represented on the surface of the dielectric layer 122 .

[0085] For example, Figure 4 As shown, the first isolation structure 111 surrounds a plurality of second isolation structures 112 that are spaced apart. One second isolation structure 112 extends along the second direction Y, and one end of the opposite ends of the second isolation structure 112 along the second direction Y is connected to the first isolation structure 111. The plurality of second isolation structures 112 are arranged in a plurality of rows along the first direction X; the second direction Y intersects the first direction X.

[0086] For example, the cross-sectional shape of the epitaxial layer 121 along the direction perpendicular to the plane where the semiconductor substrate 110 is located may be an “E” shape (see Figure 4 ) or "S" shape.

[0087] Based on the connection relationship between the second isolation structure 112 and the first isolation structure 111, the epitaxial layer 121 is formed into a continuous structure. In this way, the first transfer structure 1241 and the second transfer structure 1242 can be provided one by one in the subsequent provision, thereby reducing the number of provision of transfer structures, reducing process costs and improving the flexibility of manufacturing transfer structures.

[0088] Furthermore, the conductive layer 123 fills all the grooves 1221 on the surface of the dielectric layer 122. The grooves 1221 corresponding to the positions of the second isolation structures 112 can increase the relative area between the conductive layer 123 and the epitaxial layer 121, thereby increasing the capacitance density.

[0089] In some other examples, such as Figure 5 As shown, in the stacking direction (X or Y) of the semiconductor substrate 110 and the device stack 120 , opposite ends of the second isolation structure 112 are connected to the first isolation structure 111 .

[0090] The epitaxial layer 121 includes a plurality of spaced-apart epitaxial patterns 1210 .

[0091] The dielectric layer 122 covers the plurality of epitaxial patterns 1210 and the second isolation structure 112 between two adjacent epitaxial patterns 1210 .

[0092] The conductive layer 123 fills all the grooves 1221 represented on the surface of the dielectric layer 122 .

[0093] For example, Figure 5 As shown, the first isolation structure 111 surrounds a plurality of second isolation structures 112 arranged at intervals. The plurality of second isolation structures 112 are arranged at intervals along the second direction Y. One second isolation structure 112 extends along the first direction X, and along the first direction X, the opposite ends of the second isolation structure 112 are connected to the first isolation structure 111; the second direction Y intersects the first direction X.

[0094] For example, the first isolation structure 111 is in the shape of a square ring, and the second isolation structure 112 is in the shape of a strip, connected to two opposite sides of the first isolation structure 111, and together constitute a fence-shaped structure. Based on the connection relationship between the second isolation structure 112 and the first isolation structure 111, an epitaxial layer 121 is formed to include a plurality of spaced epitaxial patterns 1210. The conductive layer 123 fills all the grooves 1221 characterized by the surface of the dielectric layer 122. A plurality of grooves 1221 corresponding to the position of the second isolation structure 112 can increase the relative area between the conductive layer 123 and the epitaxial layer 121, and increase the capacitance density. In addition, a first transfer structure 1241 and a second transfer structure 1242 can be respectively provided to couple with an epitaxial pattern 1210 in the subsequent process, which is beneficial to increase the electrical performance of the MOS capacitor C.

[0095] In addition to the above-mentioned examples of setting the size and shape of the cross-sectional figure of the second isolation structure 112 along the direction perpendicular to the plane of the semiconductor substrate 110, and its connection method with the first isolation structure 111, to achieve the scheme of adjusting the shape and size of the epitaxial layer 121 formed between the first isolation structure 111 and the second isolation structure 112, and between two adjacent second isolation structures 112, there are other means to increase the top and side areas of the epitaxial layer 121 and increase the relative area between the epitaxial layer 121 and the conductive layer 123. The present application does not make any specific restrictions here and can be set according to actual needs.

[0096] In some examples, combined Figure 2 The semiconductor structure shown in the figure can be determined along the AA cross-sectional view as follows: Figure 7 A structure as shown. Figure 7 As shown, the epitaxial layer 121 includes a first electrode region 1211 and a second electrode region 1212 spaced apart from each other. The first electrode region 1211 is coupled to the first transfer structure 1241 ; the second electrode region 1212 is coupled to the second transfer structure 1242 .

[0097] For example, Figure 7 As shown, the first transfer structure 1241 is disposed on a side of the first electrode region 1211 of the epitaxial layer 121 away from the semiconductor substrate 110 , and is coupled to the first electrode region 1211 .

[0098] The second transfer structure 1242 is disposed on a side of the second electrode region 1212 of the epitaxial layer 121 away from the semiconductor substrate 110 , and is coupled to the second electrode region 1212 .

[0099] In this way, the first electrode region 1211 of the epitaxial layer 121 can be used as the source of the transistor when the first transfer structure 1241 is conductive. The second electrode region 1212 of the epitaxial layer 121 can be used as the drain of the transistor when the second transfer structure 1242 is conductive. The conductive layer 123 serves as the gate of the transistor. In this way, an epitaxial layer 121, a dielectric layer 122 and a portion of the conductive layer 123 in an area opposite to the channel region of the epitaxial layer 121 (located between the first electrode region 1211 and the second electrode region 1212, not shown in the figure) can form a transistor. Among them, the areas opposite to the epitaxial layer 121 and the conductive layer 123 can form a MOS capacitor, the epitaxial layer 121 serves as one plate layer of the MOS capacitor, and the conductive layer 123 serves as another plate layer of the MOS capacitor.

[0100] For example, the materials used for the first transfer structure 1241 and the second transfer structure 1242 may include one or more conductive single substances or compounds such as gold, silver, copper, aluminum, and tin.

[0101] In some examples, such as Figure 5As shown, the conductive layer 123 includes a first conductive portion 1231 and a second conductive portion 1232 that are connected.

[0102] The first conductive portion 1231 covers the region of the epitaxial layer 121 except for the region coupled to the first transfer structure 1241 and the second transfer structure 1242 .

[0103] The second conductive portion 1232 is disposed on a side of the first isolation structure 111 away from the semiconductor substrate 110 .

[0104] For example, in a layer structure of a transistor, the first conductive portion 1231 extends along the arrangement direction Y of the plurality of epitaxial patterns 1210 and covers the plurality of epitaxial patterns 1210 except the first electrode region 1211 and the second electrode region 1212 (see Figure 2 and Figure 7 ) outside the area.

[0105] As another example, the area of ​​the region where the first transfer structure 1241 contacts the epitaxial layer 121 is smaller than the area of ​​the first electrode region 1211, and / or the area of ​​the region where the second transfer structure 1242 contacts the epitaxial layer 121 is smaller than the area of ​​the second electrode region 1212. The dielectric layer 122 deposited on the epitaxial layer 121 can cover the entire epitaxial layer 121, and the portion of the first electrode region 1211 exposed through the through hole that needs to be coupled to the first transfer structure 1241, and the portion of the second electrode region 1212 that needs to be coupled to the second transfer structure 1242. In this way, the formed first conductive portion 1231 can cover the region of the epitaxial layer 121 except for the region where the first transfer structure 1241 and the second transfer structure 1242 are coupled, further increasing the relative area between the epitaxial layer 121 and the conductive layer 123, and increasing the capacitance density.

[0106] The second conductive portion 1232 is disposed on a side of the first isolation structure 111 away from the semiconductor substrate 110. The second conductive portion 1232 can be used to realize electrical connection between the plurality of first conductive portions 1231 and external electronic components. The present application does not impose any specific restrictions on the shape and extension direction of the second conductive portion 1232, nor on the size relationship between the second conductive portion 1232 and the first conductive portion 1231, as long as the second conductive portion 1232 does not overlap with the epitaxial layer 121.

[0107] Continue reading Figure 5 The epitaxial layer 121 includes a plurality of spaced epitaxial patterns 1210 . The first electrode region 1211 includes first sub-electrode regions 1211 a located in different epitaxial patterns 1210 , and the second electrode region 1212 includes second sub-electrode regions 1212 a located in different epitaxial patterns 1210 .

[0108] One first sub-electrode region 1211 a is coupled to one first transfer structure 1241 , and the first sub-electrode regions 1211 a of a plurality of epitaxial patterns 1210 are coupled to each other through a plurality of first transfer structures 1241 .

[0109] One second sub-electrode region 1212 a is coupled to one second transfer structure 1242 , and the second sub-electrode regions 1212 a of a plurality of epitaxial patterns 1210 are coupled to each other through a plurality of second transfer structures 1242 .

[0110] In addition, if Figure 2 to Figure 5 As shown, the device stack 120 also includes a transfer structure 1230 coupled to the conductive layer 123, which is used to couple the conductive layer 123 to a word line (not shown) in the semiconductor structure 100, and transmit an electrical signal to the conductive layer 123 through the word line to realize the control capability of the conductive layer 123 over the transistor. The present application does not impose any specific restrictions on the size, shape, and number of the transfer structure 1230.

[0111] It should be noted that the examples provided in this application do not impose specific restrictions on the specific layer structure and internal conductive signal lines of the semiconductor structure 100, and can be set according to actual needs. The following example illustrates the preparation process of the semiconductor structure 100 based on how to increase the relative area structure of the epitaxial layer 121 and the conductive layer 123 in the MOS capacitor C composed of the epitaxial layer 121 and the conductive layer 123 without affecting the control ability of the conductive layer 123 on the epitaxial layer 121 (i.e., transistor performance) and without increasing the thickness of the dielectric layer 122.

[0112] like Figure 8 to Figure 10 As shown, the embodiment of the present application provides a method S100 to S400 for preparing a semiconductor structure 100 , and the process of this preparation method is more compatible with the process of the semiconductor structure manufacturing method in the related art.

[0113] S100: Figure 8 ,and Fig. 9 (a) and Fig. 9 As shown in (b) of FIG. 1 , a semiconductor substrate 110 is formed. The semiconductor substrate 110 includes a first isolation structure 111 and at least one second isolation structure 112 disposed in a region surrounded by the first isolation structure 111. Figure 6 As shown, one end of the first isolation structure 111 and the second isolation structure 112 at opposite ends along a direction Z perpendicular to the plane of the semiconductor substrate 110 is exposed from the same side surface of the semiconductor substrate 110 , and the other end is located inside the semiconductor substrate 110 .

[0114] S200: Figure 8 and Fig. 9As shown in (c) of FIG. 1 , an epitaxial layer 121 is formed on one side surface of the semiconductor substrate 110. The epitaxial layer 121 is configured as a first plate layer of the MOS capacitor C. The epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112, and / or between two adjacent second isolation structures 112.

[0115] For example, the semiconductor substrate 110 is made of silicon or SOI material, and a semiconductor material can be grown between the first isolation structure 111 and the second isolation structure 112, and / or in a region between two adjacent second isolation structures 112, and ion doping is performed to obtain an epitaxial layer 121. The epitaxial layer 121 can be used as an active layer of a transistor.

[0116] It can be understood that a first isolation structure 111 and a second isolation structure 112 are arranged on the semiconductor substrate 110, and the materials of the first isolation structure 111 and the second isolation structure 112 include dielectric materials. In this way, based on the material properties of the first isolation structure 111 and the second isolation structure 112 and the relative positional relationship between the two, semiconductor materials can be grown on the top surface of the semiconductor substrate 110 and in the area where the top surfaces of the first isolation structure 111 and the second isolation structure 112 are not exposed. The quality of the obtained epitaxial layer 121 is high and will not be formed on the top surface of the first isolation structure 111 or the second isolation structure 112; moreover, the manufacturing process of the epitaxial layer 121 is simple.

[0117] S300: Figure 8 and Fig. 9 As shown in (d) in FIG. 1 , a dielectric layer 122 is formed on a side of the epitaxial layer 121 away from the semiconductor substrate 110; the dielectric layer 122 is configured as an intermediate dielectric layer between two plate layers of the MOS capacitor C. The dielectric layer 122 covers the epitaxial layer 121 and covers the second isolation structure 112. The surface of the side of the dielectric layer 122 covering the second isolation structure 112 away from the semiconductor substrate 110 is characterized as a groove 1221.

[0118] For example, a deposition process is used to deposit a dielectric material on a side of the epitaxial layer 121 away from the semiconductor substrate 110 .

[0119] S400: Figure 8 and Fig. 9 As shown in (e) in FIG. 1 , a conductive layer 123 is formed on a side of the dielectric layer 122 away from the semiconductor substrate 110 , and the conductive layer 123 is configured as a second plate layer of the MOS capacitor C. The conductive layer 123 covers the dielectric layer 122 and fills the groove 1221 .

[0120] For example, a deposition process may be used to deposit a conductive material on a side of the dielectric layer 122 away from the semiconductor substrate 110 and fill the groove 1221 so that the conductive layer 123 can extend along the side of the dielectric layer 122 or the epitaxial layer 121 (eg, Figure 6 As shown in the figure, the epitaxial layer 121 is surrounded on three sides, the relative area between the conductive layer 123 and the epitaxial layer 121 is increased, and the capacitance density of the MOS capacitor composed of the conductive layer 123 and the epitaxial layer 121 is increased.

[0121] For example, the material used for the conductive layer 123 includes one or more of metal elements, semiconductor materials, or conductive polymers. For example, the material used for the conductive layer 123 may include one or more of conductive elements or compounds such as gold, silver, copper, aluminum, and tin.

[0122] In the process of manufacturing the semiconductor structure 100, after forming the semiconductor substrate 110, the epitaxial layer 121 is manufactured. The semiconductor substrate 110 has a first isolation structure 111 and a second isolation structure 112. By growing the epitaxial layer 121 on the semiconductor substrate 110, the channel structure of the transistor (i.e., the active layer of the transistor, including the source and the drain) is obtained, and the structural features of the relative regions of the epitaxial layer 121 and the conductive layer 123 (i.e., the gate of the transistor) are set, so as to improve the control capability of the gate of the transistor over the channel region and improve the performance of the semiconductor structure 100. Compared with the related art method of increasing the trench depth, the process means of growing the epitaxial layer 121 on the semiconductor substrate 110 can reduce the process difficulty of manufacturing the active layer of the transistor, improve the structural yield of the transistor, reduce the process cost, and can be integrated into the current process of manufacturing the semiconductor structure, with high compatibility.

[0123] In some examples, such as Fig. 9 (a) and Fig. 9 (b) in the above, and Fig.10 As shown, the above step S100: forming a semiconductor substrate 110 includes S110.

[0124] S110: forming a first trench 1101 and at least one second trench 1102 in the area enclosed by the first trench 1101 on the initial semiconductor substrate 110'. The depth of the first trench 1101 is greater than the depth of the second trench 1102; the first trench 1101 surrounds the second trench 1102. The second trench 1102 is connected to the first trench 1101 at least at one of the two opposite ends perpendicular to the stacking direction of the semiconductor substrate 110 and the device stack 120; or, the second trench 1102 is spaced apart from the first trench 1101.

[0125] For example, a dry etching or wet etching process may be used to etch the initial semiconductor substrate 110 ′ to form the first trench 1101 . Then, etching is performed again in the area surrounded by the first trench 1101 to form the second trench 1102 .

[0126] S120 : depositing a dielectric material in the first trench 1101 and the second trench 1102 to form a first isolation structure 111 and a second isolation structure 112 , thereby obtaining a semiconductor substrate 110 .

[0127] The relative positional relationship between the first isolation structure 111 formed based on the first trench 1101 and the second isolation structure 112 formed based on the second trench 1102 can be referred to as follows: Figure 2 to Figure 5 The structure shown.

[0128] For example, a chemical vapor deposition (CVD) or spin-on process may be used to fill a dielectric material with a low dielectric constant in the first trench 1101 and the second trench 1102. The dielectric material may include one or more insulating materials such as silicon oxynitride SiON, silicon oxide SiO2, silicon nitride SiN, or silicon carbide SiC.

[0129] For example, by using a spin coating process, dielectric material can be filled into the first trench 1101 and the second trench 1102 in one process, which is beneficial to improving process efficiency. One side surface of the first isolation structure 111 and the second isolation structure 112 formed in this way is flush with one side surface of the semiconductor substrate 110.

[0130] For another example, by using CVD to fill the dielectric material in the first trench 1101 and the second trench 1102, the filling amount of the dielectric material in different trenches can be controlled. For example, after the dielectric material is deposited in the first trench 1101, the surface of one side of the formed first isolation structure 111 is flush with the surface of one side of the semiconductor substrate 110. After the dielectric material is deposited in the second trench, the surface of one side of the formed second isolation structure 112 is lower than the surface of one side of the semiconductor substrate 110. In this way, the side area of ​​the epitaxial layer 121 formed subsequently is increased, which is conducive to increasing the area of ​​the epitaxial layer 121 surrounded by the conductive layer 123 on three sides, increasing the channel control ability of the conductive layer 123 on the transistor, and increasing the relative area between the epitaxial layer 121 and the conductive layer 123, thereby increasing the capacitance density.

[0131] In some examples, such as Fig. 9 (c)~ Fig. 9 (g) in, and Fig.10 As shown, a semiconductor structure 100 is formed, including S210 and S510.

[0132] S210: forming an epitaxial layer 121 including a plurality of spaced epitaxial patterns; or forming an epitaxial layer 121 in a continuous structure. The epitaxial layer 121 includes spaced first electrode regions 1211 and second electrode regions 1212 (see Figure 7 ).

[0133] For example, Figure 2 to Figure 5 As shown, based on the number and arrangement structure of the second trenches 1102, an epitaxial layer 121 is grown in the region between the second isolation structure 112 and the first isolation structure 111. The shape and size of the epitaxial layer 121 can refer to Figure 2 to Figure 5 The continuous grid-like, "E"-shaped or multiple independent strip structures shown.

[0134] S510: forming a first transfer structure 1241 coupled to the first electrode region 1211 and a second transfer structure 1242 coupled to the second electrode region 1212. A conductive material is deposited on one side of the dielectric layer 122 to form a conductive layer 123. The conductive layer 123 covers the epitaxial layer 121 except for the regions coupled to the first transfer structure 1241 and the second transfer structure 1242.

[0135] For example, Fig. 9 (f) and Fig. 9 As shown in (g), an insulating layer 125 is formed on the side of the conductive layer 123 away from the semiconductor substrate 110, and the insulating layer 125 covers multiple epitaxial layers 121 (including the dielectric layer 122 and the top surface of the semiconductor substrate 110). A plurality of through holes are formed on the insulating layer 125, and the plurality of through holes can be filled with conductive materials. Part of the through holes can expose the first electrode region 1211 of the epitaxial layer 121 or a portion of the first electrode region 1211 used to couple with the first transfer structure 1241, so as to form the first transfer structure 1241. Part of the through holes can expose the second electrode region 1212 of the epitaxial layer 121 or a portion of the first electrode region 1211 used to couple with the first transfer structure 1241, so as to form the second transfer structure 1242. And, part of the through holes can expose the portion of the conductive layer 123 located on the first isolation structure 111, so as to form a transfer structure 1230 electrically connected to the conductive layer 123. In this way, the formed first conductive portion 1231 can cover the area of ​​the epitaxial layer 121 except the area coupled to the first transfer structure 1241 and the second transfer structure 1242 , further increasing the relative area between the epitaxial layer 121 and the conductive layer 123 and increasing the capacitance density of the MOS capacitor C.

[0136] The first transfer structure 1241 and the second transfer structure 1242 are also used to couple with different conductive signal lines (not shown in the figure) in the semiconductor structure 100. For example, in the case where the stacked structure of the epitaxial layer 121, the dielectric layer 122 and the conductive layer 123 forms a transistor, under the control of the electrical signal transmitted by the conductive layer 123 (coupled with the transfer structure 1230), the electrical signal transmitted by the conductive signal line coupled to the first transfer structure 1241 can be transmitted to the conductive signal line coupled to the second transfer structure 1242, thereby realizing the function of the transistor.

[0137] It should be noted that the embodiments of the semiconductor structure provided in the present application and the embodiments of the method for manufacturing the semiconductor structure belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the semiconductor structure provided in the embodiments of the present application can already solve the technical problem to be solved by the present application; therefore, the method for manufacturing the semiconductor structure provided in the embodiments of the present application may not be limited by the semiconductor structure provided in the embodiments of the present application, and any semiconductor structure prepared by the method for manufacturing the semiconductor structure provided in the embodiments of the present application is within the scope of protection of the present application.

[0138] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate, comprising a first isolation structure and at least one second isolation structure disposed in a region enclosed by the first isolation structure; The first isolation structure and the second isolation structure have two opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located, one end of each of which is exposed from the same side surface of the semiconductor substrate, and the other end of each of which is located inside the semiconductor substrate; A device stack is arranged on one side of the semiconductor substrate, comprising a capacitor and a transistor; the transistor comprises: an epitaxial layer, disposed on a side surface of the semiconductor substrate, and configured as a first plate layer of the capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures; A dielectric layer is disposed on a side of the epitaxial layer away from the semiconductor substrate and is configured as an intermediate dielectric layer between two plate layers of the capacitor; the dielectric layer covers the epitaxial layer and covers the second isolation structure; wherein a surface of a side of the dielectric layer covering the second isolation structure away from the semiconductor substrate is characterized as a groove; The conductive layer is arranged on a side of the dielectric layer away from the semiconductor substrate and is configured as a second plate layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

2. The semiconductor structure according to claim 1, characterized in that: The first isolation structure surrounds a plurality of second isolation structures arranged at intervals; The second isolation structure is not connected to the first isolation structure; and / or, along a stacking direction perpendicular to the semiconductor substrate and the device stack, one of the two opposite ends of the second isolation structure is connected to the first isolation structure; The epitaxial layer is in a continuous structure; The conductive layer fills all the grooves represented on the surface of the dielectric layer.

3. The semiconductor structure according to claim 1, characterized in that: The first isolation structure surrounds a plurality of second isolation structures arranged at intervals; Along a stacking direction perpendicular to the semiconductor substrate and the device stack, opposite ends of the second isolation structure are connected to the first isolation structure; the epitaxial layer includes a plurality of spaced epitaxial patterns; The dielectric layer covers a plurality of the epitaxial patterns and the second isolation structure between two adjacent epitaxial patterns; and the conductive layer fills all the grooves represented on the surface of the dielectric layer.

4. The semiconductor structure according to claim 2 or 3, characterized in that: The epitaxial layer includes a first electrode region and a second electrode region spaced apart; the first electrode region is coupled to a first switching structure; and the second electrode region is coupled to a second switching structure; The conductive layer includes a first conductive portion and a second conductive portion connected; The first conductive portion covers a region of the epitaxial layer except for a region coupling the first transfer structure and the second transfer structure; The second conductive portion is disposed on a side of the first isolation structure away from the semiconductor substrate.

5. The semiconductor structure according to claim 4, characterized in that: The epitaxial layer includes a plurality of spaced epitaxial patterns; the first electrode region includes first sub-electrode regions respectively located at different epitaxial patterns, and the second electrode region includes second sub-electrode regions respectively located at different epitaxial patterns; One of the first sub-electrode regions is coupled to one of the first switching structures, and a plurality of first sub-electrode regions of the epitaxial patterns are coupled to each other through a plurality of the first switching structures respectively; One second sub-electrode region is coupled to one second switching structure, and the second sub-electrode regions of a plurality of the epitaxial patterns are coupled to each other through a plurality of the second switching structures.

6. The semiconductor structure according to claim 1, characterized in that The dimension of the first isolation structure along a direction perpendicular to the plane where the semiconductor substrate is located is greater than the dimension of the second isolation structure along a direction perpendicular to the plane where the semiconductor substrate is located; One of the first isolation structures encloses a device region; the semiconductor structure includes a plurality of the device regions, and two adjacent device regions share part of the first isolation structure.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor substrate includes a silicon-on-insulator layer.

8. A method for preparing a semiconductor structure, characterized in that: include: forming a semiconductor substrate; The semiconductor substrate comprises a first isolation structure and at least one second isolation structure disposed in a region enclosed by the first isolation structure; One end of the first isolation structure and the second isolation structure at opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located is exposed from the same side surface of the semiconductor substrate, and the other end is located inside the semiconductor substrate; forming an epitaxial layer on a surface of one side of the semiconductor substrate; The epitaxial layer is configured as a first plate layer of a capacitor; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures; forming a dielectric layer on a side of the epitaxial layer away from the semiconductor substrate; The dielectric layer is configured as an intermediate dielectric layer between two plate layers of the capacitor; The dielectric layer covers the epitaxial layer and covers the second isolation structure; wherein a surface of a portion of the dielectric layer covering the second isolation structure away from the semiconductor substrate is characterized as a groove; A conductive layer is formed on a side of the dielectric layer away from the semiconductor substrate, and the conductive layer is configured as a second plate layer of the capacitor; the conductive layer covers the dielectric layer and fills the groove.

9. The preparation method according to claim 8, characterized in that: The forming of the semiconductor substrate comprises: A first trench and at least one second trench located in an area surrounded by the first trench are formed on an initial semiconductor substrate; the depth of the first trench is greater than the depth of the second trench; the first trench surrounds the second trench; wherein at least one of the two opposite ends of the second trench in a direction perpendicular to the plane where the semiconductor substrate is located is connected to the first trench; or the second trench is spaced apart from the first trench; A dielectric material is deposited in the first trench and the second trench to form the first isolation structure and the second isolation structure to obtain the semiconductor substrate.

10. The preparation method according to claim 9, characterized in that: The forming of the semiconductor substrate comprises: Forming an epitaxial layer including a plurality of spaced epitaxial patterns; or forming an epitaxial layer in a continuous structure; the epitaxial layer including spaced first electrode regions and second electrode regions; forming a first transfer structure coupled to the first electrode region and a second transfer structure coupled to the second electrode region; The conductive layer covers the epitaxial layer except for the area coupled to the first transfer structure and the second transfer structure.

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