Carrier storage type trench gate field cut-off semi-super junction IGBT device and preparation method thereof

Abstract

The invention relates to a power semiconductor technology, in particular to a carrier storage type trench gate field cut-off semi-super junction IGBT device and a preparation method thereof.The carrier storage type trench gate field cut-off semi-super junction IGBT device comprises a front cathode gate control MOS structure which is composed of a conductive region, an insulating layer, a conductive layer, a first type doped conductive region, a second type heavily doped conductive region and a first type heavily doped conductive region; the middle region drift region structure is composed of a doped conductive region, a first type conductive region, a second type conductive region and a single impurity drift region; the back anode field cut-off structure is composed of a second type conductive layer, a first type conductive layer and a back conductive layer; a carrier storage structure is introduced on the basis of a traditional trench gate field cut-off semi-super-junction IGBT, the conductivity modulation level of the traditional semi-super-junction IGBT is enhanced, and the compromise relation of the device is optimized.

Description

Technical Field

[0001] The invention relates to power semiconductor technology, and in particular to a carrier storage type trench gate field stop semi-super junction IGBT device and a preparation method thereof. Background Art

[0002] Super-junction Insulated Gate Bipolar Transistor (SJ-IGBT) can utilize the lateral electric field for two-dimensional electric field modulation during the switching process of the device, thus showing smaller switching loss and better V than conventional single impurity drift region IGBT. on -E off However, due to the limitation of the manufacturing process of the superjunction column itself, it is difficult to realize high-voltage superjunction IGBT devices using the full superjunction structure. The semi-superjunction (SemiSJ) technology combines the superjunction column with the single impurity drift region to form a semi-superjunction structure. On the basis of meeting the breakdown voltage requirements of high-voltage devices, it can achieve a certain compromise between the difficulty of process implementation and device performance, thereby reducing the difficulty of process implementation of high-voltage superjunction devices. Summary of the invention

[0003] In order to solve the above problems and optimize the compromise relationship of high-voltage IGBT, the present invention provides a trench gate field-stop (Trench-FS) semi-super junction IGBT device combined with carrier storage (CS) and a preparation method thereof. The device can utilize the existing low-voltage full super junction process platform to realize a semi-super junction IGBT device with a higher voltage level.

[0004] In the first aspect, the present invention provides a carrier storage type slot gate field stop semi-super junction IGBT device, wherein the entire cell is symmetrical about the center line of the cell, and the cell comprises a conductive region 1; two insulating layers 2 located at the bottom of the conductive region 1 and connected to the conductive region 1; each insulating layer 2 is wrapped with a conductive layer 3, and the conductive layer 3 is connected to the insulating layer 2; each insulating layer 2 is provided with a first type doped conductive region 4 connected thereto on the bottom surface; a first type doped conductive region 4 connected thereto is also provided between the two insulating layers 2, and two first type doped conductive regions 4 are provided on the front of the first type doped conductive region 4. A second type heavily doped conductive region 5 and a first type heavily doped conductive region 6; the first type heavily doped conductive region 6 is located between the two second type heavily doped conductive regions 5, and is connected to the conductive region 1, the first type doped conductive region 4, and the second type heavily doped conductive region 5; the two second type heavily doped conductive regions 5 are both connected to the conductive region 1, the insulating layer 2, and the first type doped conductive region 4; the conductive region 1, the insulating layer 2, the conductive layer 3, the first type doped conductive region 4, the second type heavily doped conductive region 5, and the first type heavily doped conductive region 6 together form a front cathode gate-controlled MOS structure;

[0005] The device further includes a doped conductive region 7 located at the bottom surface of the conductive layer 3 and the bottom surface of the first type doped conductive region 4, the doped conductive region 7 is connected to the first type doped conductive region 4; a first type conductive region 8 and a second type conductive region 9 located at the bottom surface of the doped conductive region 7 and connected to the doped conductive region 7, the first type conductive region 8 and the second type conductive region 9 are arranged alternately; a single impurity drift region 10 located at the bottom surface of the first type conductive region 8 and the bottom surface of the second type conductive region 9; wherein the doped conductive region 7 is a carrier storage layer; the doped conductive region 7, the first type conductive region 8, the second type conductive region 9, and the single impurity drift region 10 together constitute a middle region drift region structure;

[0006] The device also includes a second type conductive layer 11 located at the bottom surface of the single impurity drift region 10 and connected thereto, a first type conductive layer 12 located at the bottom surface of the second type conductive layer 11 and connected thereto, and a back conductive layer 13 located at the bottom surface of the first type conductive layer 12 and connected thereto; the second type conductive layer 11, the first type conductive layer 12, and the back conductive layer 13 together constitute a back anode field stop structure.

[0007] In a second aspect, the device provided in the first aspect, the present invention provides a method for preparing a carrier storage type trench gate field stop semi-super junction IGBT device, comprising:

[0008] S1. Prepare the drift region structure in the middle region: form a single impurity drift region on the substrate by epitaxial process; form a super junction column region on the single impurity drift region by multi-layer epitaxy or deep trench etching, wherein the super junction column region is composed of first type conductive regions and second type conductive regions arranged alternately;

[0009] S2. Prepare a front cathode gate-controlled MOS structure: form a doped conductive region on the superjunction column region by epitaxy; then use ion implantation to change the impurity type of the upper part of the doped conductive region to form a first type doped conductive region; etch a longitudinal groove in the first type doped conductive region, and form a first insulating layer on the surface of the first type doped conductive region by thermal growth; deposit a conductive layer on the first insulating layer corresponding to the longitudinal groove, and then deposit a second insulating layer on the conductive layer and the first insulating layer; the first insulating layer and the second insulating layer together constitute an insulating layer; form a second type heavily doped conductive region and a first type heavily doped conductive region in sequence between the two longitudinal grooves by ion implantation; and then form a conductive region by deposition;

[0010] S3. Prepare a back anode field stop structure: sequentially form a second type conductive layer and a first type conductive layer on the back side of the single impurity drift region by thinning, ion implantation, and thermal annealing; and form a back conductive layer on the back side of the first type conductive layer by deposition.

[0011] Beneficial effects of the present invention:

[0012] The device provided by the present invention adopts a first type conductive region 8, a second type conductive region 9 and a single impurity drift region 10 to form a semi-super junction structure, and can use a low-voltage super junction process platform to realize a high-voltage IGBT device. The characteristics of the super junction column can be utilized to a certain extent, reducing the requirements of the high-voltage IGBT device for the super junction column.

[0013] The semi-super junction IGBT device formed by the present invention has a wafer thickness and V on -E ts The compromise relationship is significantly optimized compared to the single impurity drift region IGBT of the same voltage level, and the difficulty of process implementation is significantly reduced compared to the full super junction IGBT, which can provide a compromise solution between the super junction column thickness and device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a schematic structural diagram of a carrier storage type trench gate field stop semi-super junction IGBT device according to an embodiment of the present invention;

[0015] Figure 2 Schematic diagram of the main process flow of an embodiment of the present invention;

[0016] Figure 3 Schematic diagram of the super junction process flow that can be adopted in the present invention;

[0017] Figure 4 is an embodiment to which the present invention relates;

[0018] Among them, 1-conductive region, 2-insulating layer, 3-conductive layer, 4-first type doped conductive region, 5-second type heavily doped conductive region, 6-first type heavily doped conductive region, 7-doped conductive region, 8-first type conductive region, 9-second type conductive region, 10-single impurity drift region, 11-second type conductive layer, 12-first type conductive layer, 13-back conductive layer. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The present invention provides a carrier storage type slot gate field stop semi-super junction IGBT device, such as Figure 1 As shown, the entire cell is symmetrical about the center line of the cell, and the cell includes a conductive area 1; two insulating layers 2 located at the bottom of the conductive area 1 and connected to the conductive area 1; each insulating layer 2 is wrapped with a conductive layer 3, and the conductive layer 3 is connected to the insulating layer 2; a first type doped conductive area 4 connected to it is provided on the bottom of each insulating layer 2; a first type doped conductive area 4 connected to it is also provided between the two insulating layers 2, and there are two second type heavily doped conductive areas 5 and a first type heavily doped conductive area 6 on the front of the first type doped conductive area 4; the first type heavily doped conductive area 6 is located between the two second type heavily doped conductive areas 5 and connected to the conductive area 1, the first type doped conductive area 4, and the second type heavily doped conductive area 5; the two second type heavily doped conductive areas 5 are both connected to the conductive area 1, the insulating layer 2, and the first type doped conductive area 4; the conductive area 1, the insulating layer 2, the conductive layer 3, the first type doped conductive area 4, the second type heavily doped conductive area 5, and the first type heavily doped conductive area 6 together form a front cathode gate-controlled MOS structure;

[0021] The device further includes a doped conductive region 7 located at the bottom surface of the conductive layer 3 and the bottom surface of the first type doped conductive region 4, the doped conductive region 7 is connected to the first type doped conductive region 4; a first type conductive region 8 and a second type conductive region 9 located at the bottom surface of the doped conductive region 7 and connected to the doped conductive region 7, the first type conductive region 8 and the second type conductive region 9 are arranged alternately; a single impurity drift region 10 located at the bottom surface of the first type conductive region 8 and the bottom surface of the second type conductive region 9; wherein the doped conductive region 7 is a carrier storage layer; the doped conductive region 7, the first type conductive region 8, the second type conductive region 9, and the single impurity drift region 10 together constitute a middle region drift region structure;

[0022] The device also includes a second type conductive layer 11 located at the bottom surface of the single impurity drift region 10 and connected thereto, a first type conductive layer 12 located at the bottom surface of the second type conductive layer 11 and connected thereto, and a back conductive layer 13 located at the bottom surface of the first type conductive layer 12 and connected thereto; the second type conductive layer 11, the first type conductive layer 12, and the back conductive layer 13 together constitute a back anode field stop structure.

[0023] Preferably, the insulating layer includes a transverse trench structure and a longitudinal trench structure, and the bottom of the longitudinal trench structure extends into the doped conductive region 7 .

[0024] Preferably, the first type conductive region 8 and the second type conductive region 9 are alternately arranged to form a conductive region, and the periodic width of the conductive region is independent of the periodic width of the front cathode-gated MOS structure; however, the periodic width of the conductive region and the periodic width of the front cathode-gated MOS structure may be equal or unequal.

[0025] Preferably, the doping type of the first type conductive region 8 is different from the doping type of the second type conductive region 9; the doping type of the doped conductive region 7 is the same as the doping type of the first type conductive region 8, or the same as the doping type of the second type conductive region 9. The first type doped conductive region 4 is physically isolated from the first type conductive region 8 and the second type conductive region 9 in structure.

[0026] Preferably, the doping type of the doped conductive region 7 is opposite to the doping type of the first type doped conductive region 4 .

[0027] Preferably, the doping type of the single impurity drift region 10 is the same as the doping type of the first type conductive region 8 , or the same as the doping type of the second type conductive region 9 .

[0028] Preferably, the second type conductive layer 11 is uniformly, non-uniformly or multi-peak doped, and is implemented by epitaxy or ion implantation heating annealing process.

[0029] Preferably, in the present invention, there are two doping types, namely, a first type and a second type, and the first type and the second type of doping types are interchangeable.

[0030] Unless otherwise specified, the conductive material involved in the present invention is a semiconductor or a metal, and the semiconductor material type may be single crystal silicon, polycrystalline silicon, silicon carbide or gallium nitride.

[0031] In one embodiment, the present invention relates to a carrier storage type trench gate field stop semi-super junction IGBT device such as Figure 4As shown, the main conductive impurity is single crystal silicon, the first doping type is P type, and the second doping type is N type. Specifically, it includes a metal conductive region Metal, two insulating oxide layers Oxide connected to the metal conductive region Metal; a heavily doped semiconductor layer Poly connected to the insulating oxide layer Oxide and wrapped by the insulating oxide layer Oxide, a P-type doped conductive region P-body connected to the insulating oxide layer Oxide; an N-type heavily doped conductive region N+ connected to Metal, Oxide, and P-body, and a P-type heavily doped conductive region P+ connected to Metal, P-body, and N+; the above Metal, Oxide, Poly, P-body, N+, and P+ together constitute a positive MOS structure.

[0032] The N-type conductive region N-CS connected to the P-body forms a carrier storage layer; the P-type conductive region P-pillar and the N-type conductive region N-pillar connected to the N-CS and arranged alternately, the P-type conductive region P-pillar and the N-type conductive region N-pillar together form a super junction drift region; the N-type conductive region N-drift (i.e., Figure 4 The N-) in the figure is a lightly doped region, forming a single impurity drift region; the above-mentioned N-CS, P-pillar, N-pillar, and N-drift conductive regions together constitute a semi-superjunction withstand voltage drift region in the middle of the cell.

[0033] It also includes an N-type conductive region N-buffer connected to the N-drift, a P-type conductive region P-collector connected to the N-buffer, and a metal conductive layer Metal connected to the P-collector; the above-mentioned N-buffer, P-collector, and Metal together constitute the field-stop type transparent collector structure on the back. Specifically, the back transparent anode in the present invention is composed of an N-type field resistance layer (i.e., N-buffer) and a P-type collector region (i.e., P-collector), and both layers are formed by ion implantation.

[0034] Specifically, the superjunction drift regions corresponding to the N-pillar and the P-pillar can be realized by a variety of processes, such as: multiple epitaxy combined with ion implantation ( Figure 3 (b)) or deep trench etching combined with backfilling ( Figure 3 (a)).

[0035] The present invention provides a method for preparing a carrier storage type trench gate field stop semi-super junction IGBT device, such as Figure 2 As shown, including:

[0036] S1. Prepare the drift region structure in the middle region: form a single impurity drift region on the substrate by epitaxial process; form a super junction column region on the single impurity drift region by multi-layer epitaxy or deep trench etching, wherein the super junction column region is composed of first type conductive regions and second type conductive regions arranged alternately;

[0037] S2. Prepare a front cathode gate-controlled MOS structure: form a doped conductive region on the superjunction column region by epitaxy; then use ion implantation to change the impurity type of the upper part of the doped conductive region to form a first type doped conductive region; etch a longitudinal groove in the first type doped conductive region, and form a first insulating layer on the surface of the first type doped conductive region by thermal growth; deposit a conductive layer on the first insulating layer corresponding to the longitudinal groove, and then deposit a second insulating layer on the conductive layer and the first insulating layer; the first insulating layer and the second insulating layer together constitute an insulating layer; form a second type heavily doped conductive region and a first type heavily doped conductive region in sequence between the two longitudinal grooves by ion implantation; and then form a conductive region by deposition;

[0038] S3. Prepare a back anode field stop structure: sequentially form a second type conductive layer and a first type conductive layer on the back side of the single impurity drift region by thinning, ion implantation, and thermal annealing; and form a back conductive layer on the back side of the first type conductive layer by deposition.

[0039] The principle of the present invention is described in detail below in conjunction with embodiments:

[0040] The basic principle of the present invention is: by using a semi-superjunction composite structure composed of multi-type impurity superjunction columns and a single-type impurity drift region, combined with slot gate field stop and carrier storage technology, a high-performance high-voltage superjunction device can be realized using a low-voltage superjunction process platform: on the one hand, the process realization difficulty of high-voltage superjunction IGBT devices is reduced; on the other hand, the characteristics of the superjunction can reduce the switching loss of IGBTs, and the compromise relationship of high-voltage superjunction IGBTs is optimized. The characteristics of the device application are: compared with the classic single impurity type drift region IGBT device, the key compromise relationship of the device is significantly optimized by introducing a semi-superjunction structure; compared with the full superjunction IGBT device, the process realization difficulty is reduced. The semi-superjunction IGBT device combined with slot gate field stop and carrier storage technology provides a compromise solution between the performance-process realization difficulty of the classic single impurity type drift region IGBT and the full superjunction IGBT.

[0041] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "rotation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0042] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A carrier storage type trench gate field stop semi-super junction IGBT device, characterized in that: The entire cell is symmetrical about the cell centerline, and the cell comprises a conductive region (1), and two insulating layers (2) located at the bottom of the conductive region (1); each insulating layer (2) is wrapped with a conductive layer (3), and each insulating layer (2) is provided with a first-type doped conductive region (4) at the bottom; a first-type doped conductive region (4) is also provided between the two insulating layers (2), and two second-type heavily doped conductive regions (5) and a first-type heavily doped conductive region (6) are provided on the front of the first-type doped conductive region (4); the first-type heavily doped conductive region (6) is located between the two second-type heavily doped conductive regions (5) and is connected to the conductive region (1); the two second-type heavily doped conductive regions (5) are both connected to the conductive region (1) and the insulating layer (2); the conductive region (1), the insulating layer (2), the conductive layer (3), the first-type doped conductive region (4), the second-type heavily doped conductive region (5), and the first-type heavily doped conductive region (6) together form a front cathode gate-controlled MOS structure; It also includes a doped conductive region (7) located at the bottom surface of the conductive layer (3) and the bottom surface of the first type doped conductive region (4); a first type conductive region (8) and a second type conductive region (9) located at the bottom surface of the doped conductive region (7), the first type conductive region (8) and the second type conductive region (9) being arranged alternately; a single impurity drift region (10) located at the bottom surface of the first type conductive region (8) and the bottom surface of the second type conductive region (9); the doped conductive region (7), the first type conductive region (8), the second type conductive region (9), and the single impurity drift region (10) together form a middle region drift region structure; The invention also comprises a second type conductive layer (11) located at the bottom surface of the single impurity drift region (10), a first type conductive layer (12) located at the bottom surface of the second type conductive layer (11), and a back conductive layer (13) located at the bottom surface of the first type conductive layer (12); the second type conductive layer (11), the first type conductive layer (12), and the back conductive layer (13) together form a back anode field stop structure.

2. A carrier storage type trench gate field stop semi-super junction IGBT device according to claim 1, characterized in that: The insulating layer comprises a transverse groove structure and a longitudinal groove structure, and the bottom of the longitudinal groove structure extends into the doped conductive region (7).

3. A carrier storage type trench gate field stop semi-super junction IGBT device according to claim 1, characterized in that: The first type conductive area (8) and the second type conductive area (9) are alternately arranged to form a conductive area, and the period width of the conductive area is independent of the period width of the front cathode gate-controlled MOS structure.

4. The carrier storage type trench gate field stop semi-super junction IGBT device according to claim 1, characterized in that: The doping type of the first type conductive region (8) is different from the doping type of the second type conductive region (9); the doping type of the doped conductive region (7) is the same as the doping type of the first doping type conductive region (8), or the same as the doping type of the second doping type conductive region (9).

5. The carrier storage type trench gate field stop semi-super junction IGBT device according to claim 1, characterized in that: The doping type of the doped conductive region (7) is opposite to the doping type of the first type doped conductive region (4).

6. The carrier storage type trench gate field stop semi-super junction IGBT device according to claim 1, characterized in that: The doping type of the single impurity drift region (10) is the same as the doping type of the first type conductive region (8), or the same as the doping type of the second type conductive region (9).

7. The carrier storage type trench gate field stop semi-super junction IGBT device according to claim 1, characterized in that: The second type conductive layer (11) is uniformly, non-uniformly or multi-peak doped and is implemented by epitaxy or ion implantation heating annealing process.

8. A method for preparing a carrier storage type trench gate field stop semi-super junction IGBT device according to any one of claims 1 to 7, characterized in that: include: S1. Prepare the drift region structure in the middle region: form a single impurity drift region on the substrate by epitaxial process; form a super junction column region on the single impurity drift region by multi-layer epitaxy or deep trench etching, wherein the super junction column region is composed of first type conductive regions and second type conductive regions arranged alternately; S2. Prepare a front cathode gate-controlled MOS structure: form a doped conductive region on the superjunction column region by epitaxy; then use ion implantation to change the impurity type of the upper part of the doped conductive region to form a first type doped conductive region; etch a longitudinal groove in the first type doped conductive region, and form a first insulating layer on the surface of the first type doped conductive region by thermal growth; deposit a conductive layer on the first insulating layer corresponding to the longitudinal groove, and then deposit a second insulating layer on the conductive layer and the first insulating layer; the first insulating layer and the second insulating layer together constitute an insulating layer; form a second type heavily doped conductive region and a first type heavily doped conductive region in sequence between the two longitudinal grooves by ion implantation; and then form a conductive region by deposition; S3. Prepare a back anode field stop structure: sequentially form a second type conductive layer and a first type conductive layer on the back side of the single impurity drift region by thinning, ion implantation, and thermal annealing; and form a back conductive layer on the back side of the first type conductive layer by deposition.

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