Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. A plurality of insulating dielectric layers are arranged in the surface layer of the first conductive type drift region at intervals, and each trench gate is spaced from the insulating dielectric layer in the first direction, so that hole accumulation can be better formed in the substrate, the internal conductivity modulation effect is enhanced, the resistance is reduced, the forward conduction voltage drop of the device is reduced, and the performance of the device is improved. And when the thickness of the insulating dielectric layer exceeds a critical value, the withstand voltage of the semiconductor device cannot be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] At present, in order to coordinate the contradiction between the on-state characteristics and the off-state and short-circuit characteristics of IGBT (Insulated Gate Bipolar Transistor), a carrier storage technology is used to add a low-doping concentration n-type region on the upper part of the first conductive type drift region to block the extraction of holes by the p-type base region, forming a carrier storage layer (i.e., CS layer), which reduces the forward conduction voltage drop of the device while compromising the contradictory relationship between withstand voltage and forward conduction.

[0003] However, when the thickness of the carrier storage layer in the existing IGBT exceeds a certain critical value, the withstand voltage will drop sharply, affecting the normal operation of the device. Summary of the invention

[0004] The purpose of the present invention is to provide a semiconductor device and a method for preparing the same, so as to better form hole accumulation in the substrate, thereby enhancing the internal conductivity modulation effect, reducing resistance, and lowering the forward conduction voltage drop of the device, and when the thickness of the insulating dielectric layer exceeds a critical value, the withstand voltage of the semiconductor device will not be reduced.

[0005] In order to achieve the above object and other related objects, the present invention provides a semiconductor device, comprising:

[0006] A substrate including a collector region of a second conductivity type and a drift region of a first conductivity type located on the collector region of the second conductivity type;

[0007] A plurality of insulating dielectric layers are arranged in a first direction at intervals in a surface layer of the first conductive type drift region, wherein the first direction is a direction parallel to an upper surface of the first conductive type drift region;

[0008] A base region of a second conductivity type, covering the insulating dielectric layer and extending to cover the first conductivity type drift region between the insulating dielectric layers;

[0009] At least one trench gate, each of the trench gates penetrates the base region of the second conductivity type in a second direction and extends into the drift region of the first conductivity type, each of the trench gates is spaced apart from the insulating dielectric layer in the first direction, and the second direction is perpendicular to the first direction;

[0010] The emitter region of the first conductivity type is located in the base region of the second conductivity type on both sides of the trench gate.

[0011] Optionally, in the semiconductor device, the thickness of the insulating dielectric layer is

[0012] Optionally, in the semiconductor device, when the sum of the width of a single trench gate and the spacing between two adjacent trench gates is 2.4 μm, the width of each insulating dielectric layer is 0.72 μm to 1.1 μm.

[0013] Optionally, in the semiconductor device, a spacing between the insulating dielectric layer and the adjacent trench gate is 0.05 μm to 0.24 μm.

[0014] In order to achieve the above object and other related objects, the present invention also provides a method for preparing a semiconductor device, comprising the following steps:

[0015] Providing a substrate, wherein the substrate has a first conductive type drift region;

[0016] forming a plurality of insulating dielectric layers spaced apart in a first direction inside the first conductive type drift region, wherein the first direction is a direction parallel to an upper surface of the first conductive type drift region;

[0017] forming a base region of a second conductivity type on the insulating dielectric layer, wherein the base region of the second conductivity type also extends to cover the drift region of the first conductivity type between the insulating dielectric layers;

[0018] forming at least one trench gate, each of the trench gates penetrating the base region of the second conductivity type in a second direction and extending into the drift region of the first conductivity type, each of the trench gates being spaced apart from the insulating dielectric layer in the first direction, and the second direction being perpendicular to the first direction;

[0019] An emitter region of the first conductivity type is formed in the base region of the second conductivity type at both sides of the trench gate by an ion implantation process, and a collector region of the second conductivity type is formed at the bottom of the drift region of the first conductivity type.

[0020] Optionally, in the method for preparing the semiconductor device, the thickness of the insulating dielectric layer is

[0022] Optionally, in the method for manufacturing the semiconductor device, the step of forming a plurality of insulating dielectric layers spaced apart in the first direction inside the first conductive type drift region includes:

[0023] forming a hard mask layer on the first conductive type drift region;

[0024] Performing photolithography and etching processes on the hard mask layer to define a plurality of oxygen implantation regions spaced apart;

[0025] An oxygen implantation isolation process is performed on the first conductive type drift region to form an insulating dielectric layer inside the first conductive type drift region corresponding to the oxygen implantation area.

[0026] Optionally, in the method for preparing the semiconductor device, the step of forming a base region of the second conductivity type on the insulating dielectric layer includes:

[0027] Performing an etching process on the first conductive type drift region to form a first trench structure, wherein the first trench structure exposes the insulating dielectric layer;

[0028] Forming a base region of a second conductivity type in the first trench structure by an epitaxial process, wherein the base region of the second conductivity type further extends onto the drift region of the first conductivity type;

[0029] A portion of the thickness of the second conductive type base region is removed to expose the first conductive type drift region.

[0030] Optionally, in the method for preparing the semiconductor device, when the sum of the width of a single trench gate and the spacing between two adjacent trench gates is 2.4 μm, the width of each insulating dielectric layer is 0.72 μm to 1.1 μm.

[0031] Optionally, in the method for preparing the semiconductor device, the spacing between the insulating dielectric layer and the adjacent trench gate is 0.05 μm to 0.24 μm.

[0032] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0033] In the semiconductor device provided by the present invention, an insulating dielectric layer is formed above the first conductive type drift region to block the extraction of holes by the second conductive type base region, thereby indirectly increasing the concentration of carriers inside the first conductive type drift region, enhancing the conductivity modulation effect, reducing the resistance of the first conductive type drift region, and reducing the forward conduction voltage drop of the device.

[0034] Secondly, the insulating dielectric layer of the present invention can take into account both process and design requirements. Since the insulating dielectric layer does not participate in the carrier flow process, the problem of reduced withstand voltage will not occur when the thickness of the insulating dielectric layer exceeds a critical value.

[0035] Moreover, the insulating dielectric layer introduced above the first conductive type drift region through the oxygen injection isolation process of the present invention can be used as an etching stop layer, which can ensure that the second conductive type base region grown by the epitaxial process is in exact contact with the insulating dielectric layer. The insulating dielectric layer can play the best role in blocking the second conductive type base region from extracting holes.

[0036] In addition, the present invention adopts an epitaxial process to grow the second conductive type base region of the semiconductor device, which can well control the size of the second conductive type base region and save process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The structure diagram of the product after the method for preparing a semiconductor device executes step S01;

[0038] Figure 2 The structure diagram of the product after the semiconductor device manufacturing method performs step S02;

[0039] Figure 3 is a schematic structural diagram of a product after the method for preparing a semiconductor device executes step S03;

[0040] Figure 4 is a schematic structural diagram of a product after the method for preparing a semiconductor device executes step S04;

[0041] Figure 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

[0042] Figure 6 is a schematic structural diagram of a product after the method for preparing a semiconductor device according to an embodiment of the present invention executes step S22;

[0043] Figure 7 is a schematic structural diagram of a product after the method for preparing a semiconductor device according to an embodiment of the present invention executes step S23;

[0044] Figure 8 is a schematic structural diagram of a product after the method for preparing a semiconductor device according to an embodiment of the present invention executes step S31;

[0045] Fig. 9 is a schematic structural diagram of a product after the method for preparing a semiconductor device according to an embodiment of the present invention executes step S32;

[0046] Fig.10 is a schematic structural diagram of a product after the method for preparing a semiconductor device according to an embodiment of the present invention executes step S4;

[0047] Fig.11 is a schematic structural diagram of a product after the method for preparing a semiconductor device according to an embodiment of the present invention executes step S5;

[0048] Figure 1 to Figure 4 middle:

[0049] 01-n-type drift region, 02-CS layer, 03-trench gate, 04-p-type base region, 05-p-type collector region, 06-n-type buffer region, 07-n-type emitter region;

[0050] Figures 5 to 11 middle:

[0051] 10 - drift region of first conductivity type, 20 - hard mask layer, 201 - opening, 30 - insulating dielectric layer, 40 - first trench structure, 50 - base region of second conductivity type, 60 - trench gate, 70 - emitter region of first conductivity type, 80 - collector region of second conductivity type, 90 - buffer region. DETAILED DESCRIPTION

[0052] Figure 1 to Figure 4 A method for preparing a semiconductor device is shown, which specifically includes the following steps:

[0053] Step S01: providing a substrate, wherein the substrate has an n-type drift region 01;

[0054] Step S02: forming a CS layer 02 in the n-type drift region 01 by an ion implantation process;

[0055] Step S03: forming a trench gate 03, wherein the trench gate 03 passes through the CS layer 02 from the upper surface of the n-type drift region 01 and extends into the n-type drift region 01 below the CS layer 02;

[0056] Step S04 : performing multiple ion implantation processes to form a p-type base region 04 , an n-type emitter region 07 , a p-type collector region 05 and an n-type buffer region 06 .

[0057] When the thickness of the CS layer 02 in the semiconductor device prepared by steps S01 to S04 exceeds a certain critical value, the withstand voltage will drop sharply, which will affect the normal operation of the device.

[0058] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0059] In order to solve the above problems, the present invention provides a semiconductor device, Figure 5 , which may include:

[0060] A substrate, comprising a collector region 80 of a second conductivity type and a drift region 10 of a first conductivity type located on the collector region 80 of the second conductivity type;

[0061] A plurality of insulating dielectric layers 30 are arranged in a first direction at intervals in a surface layer of the first conductive type drift region 10 , wherein the first direction is a direction parallel to an upper surface of the first conductive type drift region 10 ;

[0062] A second conductive type base region 50 covering the insulating dielectric layer 30 and extending to cover the first conductive type drift region 10 between the insulating dielectric layers 30;

[0063] at least one trench gate 60, each of the trench gates 60 penetrates the second conductive type base region 50 in the second direction and extends to the first conductive type drift region 10 between adjacent insulating dielectric layers 30, each of the trench gates 60 is spaced apart from the insulating dielectric layer 30 in the first direction, and the second direction is perpendicular to the first direction;

[0064] The emitter region 70 of the first conductivity type is located in the base region 50 of the second conductivity type on both sides of the trench gate 60 .

[0065] In this embodiment, the semiconductor device may further include a buffer region 90 located between the collector region 80 of the second conductivity type and the drift region 10 of the first conductivity type.

[0066] In this embodiment, the first conductivity type is opposite to the second conductivity type, that is, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type. For example, when the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type drift region 10 is an n-type drift region, the first conductivity type emitter region 70 is an n-type emitter region, the buffer region 90 is an n-type buffer region, the second conductivity type collector region 80 is a p-type collector region, and the second conductivity type base region 50 is a p-type base region.

[0067] The present invention also provides a method for preparing the semiconductor device described above. Figure 6 to Figure 11 , which may specifically include the following steps:

[0068] Step S1: providing a substrate, wherein the substrate has a first conductive type drift region 10;

[0069] Step S2: forming a plurality of insulating dielectric layers 30 spaced apart in a first direction inside the first conductive type drift region 10 , wherein the first direction is a direction parallel to an upper surface of the first conductive type drift region 10 ;

[0070] Step S3: forming a base region 50 of a second conductivity type on the insulating dielectric layer 30 , wherein the base region 50 of the second conductivity type also extends to cover the drift region 10 of the first conductivity type between the insulating dielectric layers 30 ;

[0071] Step S4: forming at least one trench gate 60, each of the trench gates 60 penetrates the second conductive type base region 50 in the second direction and extends into the first conductive type drift region 10, each of the trench gates 60 is spaced apart from the insulating dielectric layer 30 in the first direction, and the second direction is perpendicular to the first direction;

[0072] Step S5: forming an emitter region 70 of the first conductivity type in the base region 50 of the second conductivity type on both sides of the trench gate 60 by an ion implantation process, and forming a collector region 80 of the second conductivity type at the bottom of the drift region 10 of the first conductivity type.

[0073] See also Figure 6 , perform step S1 to provide a substrate. The substrate provides a process platform for the formation of an IGBT (insulated gate bipolar transistor). In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate can also be a substrate of other materials such as a silicon germanium substrate or a silicon carbide substrate, and the substrate can also be a substrate of other types such as a silicon on insulator substrate.

[0074] In the present embodiment, the substrate has a first conductivity type drift region 10. In the present embodiment, the first conductivity type is opposite to the second conductivity type, that is, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type. Further, the first conductivity type is preferably n-type, and the second conductivity type is preferably p-type. Therefore, the first conductivity type drift region 10 of the present embodiment is preferably an n-type drift region, that is, the doping ions in the first conductivity type drift region 10 are preferably n-type ions, such as P (phosphorus) ions, As (arsenic) ions or Sb (antimony) ions.

[0075] Continue reading Figure 6 and Figure 7 , executing step S2, forming a plurality of insulating dielectric layers 30 spaced apart in a first direction inside the first conductive type drift region 10. Specifically, the step may include:

[0076] Step S21: forming a hard mask layer 20 on the first conductive type drift region 10;

[0077] Step S22: performing photolithography and etching processes on the hard mask layer 20 to define a plurality of oxygen implantation regions;

[0078] Step S23: performing an oxygen implantation isolation process on the first conductive type drift region 10 to form an insulating dielectric layer 30 inside the first conductive type drift region 10 corresponding to the oxygen implantation area.

[0079] See also Figure 6 , perform step S21 to form a hard mask layer 20. In this embodiment, the hard mask layer 20 may be a single-layer or multi-layer stacked structure. When the hard mask layer 20 is a single-layer structure, its material may be silicon oxide, silicon nitride or silicon oxynitride. The hard mask layer 20 in this embodiment is preferably a single-layer silicon nitride. The formation process of the hard mask layer 20 may be a chemical deposition process or a physical deposition process.

[0080] Execute step S22 to define multiple oxygen injection regions. The oxygen injection region in this embodiment is the region where the opening 201 is located, and the opening 201 is formed by forming a photoresist layer on the hard mask layer, photolithography the photoresist layer to form a patterned photoresist layer, and then etching the hard mask layer 20 using the patterned photoresist layer as a mask. The oxygen injection region in this embodiment is preferably multiple, and the multiple oxygen injection regions are arranged at intervals.

[0081] See also Figure 7 , execute step S23, and execute the oxygen injection isolation process. In this embodiment, the insulating dielectric layer 30 is formed by the oxygen injection isolation process, that is, a high-concentration oxygen injection layer is generated under the surface of the first conductive type drift region 10; high-temperature annealing allows the injected oxygen to react with the silicon of the first conductive type drift region 10 to form the insulating dielectric layer 30. During the oxygen injection isolation process, the hard mask layer 20 will block the injection of oxygen, and the oxygen will enter the surface of the first conductive type drift region 10 through the oxygen injection area, that is, the insulating dielectric layer 30 is formed inside the first conductive type drift region 10 corresponding to the oxygen injection area, and its number is the same as the number of the oxygen injection areas, and multiple insulating dielectric layers 30 are spaced in the first direction, and the first direction is a direction parallel to the upper surface of the first conductive type drift region 10. The depth of the insulating dielectric layer 30 can be designed according to the depth of the subsequent second conductive type base region. The material of the insulating dielectric layer 30 can be any insulating material, preferably silicon oxide (SiO2). Since silicon oxide is an insulating material, it can play a role in blocking carriers. The thickness of the insulating dielectric layer 30 is preferably The requirements of process and design can be taken into account at the same time, and since the insulating medium (such as SiO2) does not participate in the carrier flow process, there will be no problem of voltage resistance reduction when the critical value is exceeded. The spacing between adjacent insulating dielectric layers 30 can be set according to the pitch size (repeating unit) of the semiconductor device. The area between adjacent trench gates is defined as the inter-gate region. A single trench gate and an adjacent inter-gate region constitute a repeating unit, that is, the size of the repeating unit can be the sum of the width of a single trench gate 60 and the spacing between two adjacent trench gates 60. For example, when the size of the repeating unit is 2.4μm, the spacing between adjacent insulating dielectric layers 30 is preferably 1.3μm to 1.68μm, which can have an effect better than the traditional structure. In this embodiment, there is a gap between the insulating dielectric layer 30 and the adjacent trench gates, and a small number of electrons and holes can move through the gap (channel) to ensure that the device can be turned on normally. However, due to the obstruction of the insulating dielectric layer 30, the flow channel becomes narrower, and most of the holes will accumulate in the first conductive type drift region 10. The spacing between the insulating dielectric layer 30 and the adjacent trench gates can be set according to the size of the repeating unit of the semiconductor device. For example, when the size of the repeating unit is 2.4 μm, the spacing between the insulating dielectric layer 30 and the adjacent trench gates is preferably 0.05 μm to 0.24 μm, which can be superior to the conventional structure ( Figure 4 The width of each insulating dielectric layer 30 can be set according to the size of the repeating unit of the semiconductor device. For example, when the size of the repeating unit is 2.4 μm, the width of each insulating dielectric layer 30 is preferably 0.72 μm to 1.1 μm, which will have a better effect of improving conductivity modulation and reducing conduction voltage drop. The spacing between adjacent insulating dielectric layers 30 can be set according to the size of the repeating unit of the semiconductor device. For example, when the size of the repeating unit is 2.4 μm, the spacing between adjacent insulating dielectric layers 30 is preferably 1.3 μm to 1.68 μm, which can be superior to the traditional structure ( Figure 4 semiconductor devices).

[0082] Table 1 shows the semiconductor device with an insulating dielectric layer and the conventional structure ( Figure 4 The results obtained by simulation of semiconductor devices are as follows:

[0083] Table 1:

[0084]

[0085] From the simulation results in Table 1, it can be seen that replacing the CS layer with an insulating dielectric layer 30 has no significant effect on parameters such as BV (breakdown voltage) and Vth (threshold voltage); when the Pitch Size is 2.4μm and the width of each insulating dielectric layer 30 is 0.72μm, the corresponding Vce (voltage difference between the collector region and the emitter region) result is almost the same as the Vce result corresponding to the structure containing the CS layer. When the width of each insulating dielectric layer 30 is 1.1μm, the Vce reduction effect is the best, which is reduced by about 10% compared with the structure containing the CS layer. Therefore, when the width of each insulating dielectric layer 30 is 0.72μm to 1.1μm, the effect of improving conductivity modulation and reducing the on-state voltage drop is better than that of the traditional structure. Among them, Vth-15mA represents the threshold voltage of the transistor when the current is 15mA, Vce-15A represents the voltage difference between the collector region and the emitter region of the transistor when the current is 15A, and Vce-100A represents the voltage difference between the collector region and the emitter region of the transistor when the current is 100A. In other embodiments, the Pitch Size may be other values, which may be set specifically according to process requirements.

[0086] See also Figures 8 to 10 , perform step S3 to form a base region 50 of the second conductivity type. In this embodiment, the step of forming the base region 50 of the second conductivity type may include:

[0087] Step S31: performing an etching process on the first conductive type drift region to form a first trench structure 40 , wherein the first trench structure 40 exposes the insulating dielectric layer 30 ;

[0088] Step S32: forming a base region 50 of a second conductivity type in the first trench structure 40 by an epitaxial process, wherein the base region 50 of the second conductivity type also extends onto the drift region 10 of the first conductivity type;

[0089] Step S33 : removing a portion of the thickness of the second conductive type base region 50 to expose the first conductive type drift region 10 .

[0090] See also Figure 8, perform step S31 to form a first trench structure 40. In this embodiment, the first trench structure 40 is formed by an etching process, and the etching stops at the upper surface of the insulating dielectric layer 30, that is, the insulating dielectric layer 30 is used as an etching stop layer in this embodiment, which can ensure that the epitaxial structure (that is, the second conductive type base region 50) grown by the subsequent epitaxial process is just in contact with the insulating dielectric layer 30, and the insulating dielectric layer 30 can play the best effect of blocking the second conductive type base region 50 from extracting holes. The first trench structure 40 exposes the insulating dielectric layer 30 and also exposes the first conductive type drift region 10 between the insulating dielectric layers 30. The etching process of this step is preferably a dry etching process, but is not limited thereto.

[0091] See also Fig. 9 , execute step S32 to form a base region 50 of the second conductivity type. In this embodiment, an epitaxial process is used to form the base region 50 of the second conductivity type. The base region 50 of the second conductivity type fills the first trench structure 40 and extends to the first conductivity type drift region 10 on both sides of the first trench structure 40. In this embodiment, the base region 50 of the second conductivity type is preferably a p-type base region, and specifically can be a base region of Si containing trivalent ions such as B (boron) and AL (aluminum). The thickness of the base region 50 of the second conductivity type can be set according to process requirements. The base region 50 of the second conductivity type in this embodiment is an epitaxial structure, which can well control the size of the base region 50 of the second conductivity type. Compared with the base region 50 of the second conductivity type formed directly by ion implantation, this embodiment does not need to be controlled by diffusion annealing, which can save process costs.

[0092] See also Fig.10 , perform step S33 to remove a portion of the thickness of the second conductive type base region 50 to expose the first conductive type drift region 10. In this embodiment, CMP (chemical mechanical polishing) is preferably used to remove a portion of the thickness of the second conductive type base region 50.

[0093] In other embodiments, the second conductive type base region 50 may be formed by directly performing ion implantation on the first conductive type drift region 10 above the insulating dielectric layer 30 , and this method does not require performing an epitaxial process and a chemical mechanical polishing process.

[0094] Continue reading Fig.10 , perform step S4 to form a trench gate 60. In this embodiment, the trench gate 60 may include a polysilicon gate and a gate oxide layer wrapping the trench gate. The steps of forming the trench gate 60 may include:

[0095] Step S41: using photolithography and etching processes to form at least one second trench structure penetrating through the second conductive type base region 50 in a second direction and extending to the first conductive type drift region 10 between adjacent insulating dielectric layers 30, wherein the bottom of the second trench structure is lower than the bottom of the insulating dielectric layer 30, and the second direction is perpendicular to the first direction;

[0096] Step S42 : sequentially forming a gate oxide layer and a polysilicon gate in the second trench structure to obtain the trench gate 60 .

[0097] Step S41 is performed to form at least one second trench structure. In this embodiment, the specific process of forming the second trench structure may be: forming a photoresist layer on the second conductive type base region 50, and performing photolithography on the photoresist layer to form a patterned photoresist layer; then, etching the second conductive type base region 50 and the first conductive type drift region 10 using the patterned photoresist layer as a mask to form a second trench structure. In this embodiment, the bottom of the second trench structure is lower than the bottom of the insulating dielectric layer 30.

[0098] Execute step S42 to sequentially form a gate oxide layer and a polysilicon gate in the second trench structure. The gate oxide layer and the polysilicon gate may be formed by a chemical deposition process or a physical deposition process, but is not limited thereto. In this embodiment, a gate oxide layer is first deposited in the second trench structure so that the side surface and the bottom surface of the second trench structure are covered with a gate oxide layer; and then the polysilicon gate is deposited. In this embodiment, the material of the gate oxide layer is preferably silicon oxide, but is not limited thereto.

[0099] See also Fig.11 , execute step S5, perform multiple ion implantation processes to form an emitter region 70 of the first conductivity type in the base region 50 of the second conductivity type on both sides of the trench gate 60, and form a collector region 80 of the second conductivity type at the bottom of the drift region 10 of the first conductivity type.

[0100] In this embodiment, the emitter region 70 of the first conductivity type is preferably an n-type emitter region, that is, the doping ions in the emitter region 70 of the first conductivity type are preferably n-type ions, such as P (phosphorus) ions, As (arsenic) ions or Sb (antimony) ions. The collector region 80 of the second conductivity type is preferably a p-type collector region, which forms a hole current when the semiconductor device is turned on, that is, the doping ions in the collector region 80 of the second conductivity type are preferably p-type ions, such as B (boron) ions, Ga (gallium) ions or In (indium) ions.

[0101] In the step of performing multiple ion implantation processes in this embodiment, a buffer zone 90 is formed in the first conductive type drift region 10 above the second conductive type collector region 80. The buffer zone 90 is preferably an n-type buffer zone, that is, the doped ions in the buffer zone 90 are preferably n-type ions, such as P (phosphorus) ions, As (arsenic) ions or Sb (antimony) ions. The buffer zone 90 of this embodiment plays the role of electric field cutoff.

[0102] The multiple ion implantation processes in this embodiment include a front ion implantation process and a back ion implantation process. The emitter region 70 of the first conductivity type is formed by the front ion implantation process, and the collector region 80 of the second conductivity type and the buffer region 90 are formed by the back ion implantation process.

[0103] In summary, it can be seen that the present invention forms an insulating dielectric layer in the surface layer of the first conductive type drift region. The insulating dielectric layer can be used as an etching stop layer and can also block the extraction of holes by the second conductive type base region, thereby indirectly increasing the concentration of carriers inside the first conductive type drift region, enhancing the conductivity modulation effect, reducing the resistance of the first conductive type drift region, and reducing the forward conduction voltage drop of the device. Moreover, since the insulating dielectric layer does not participate in the carrier flow process, there will be no problem of reduced withstand voltage when the thickness of the insulating dielectric layer exceeds the critical value.

[0104] In addition, it is understood that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0105] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, usages and applications described herein, which may vary. It should also be understood that the terms described herein are only used to describe specific embodiments, rather than to limit the scope of the present invention. It must be noted that the singular forms "one", "a kind" and "the" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates the opposite meaning. The structure described herein will be understood to also quote the functional equivalent of the structure. Language that can be interpreted as approximate should be understood as such, unless the context clearly indicates the opposite meaning.

Claims

1. A semiconductor device, characterized in that: include: A substrate including a collector region of a second conductivity type and a drift region of a first conductivity type located on the collector region of the second conductivity type; A plurality of insulating dielectric layers are arranged in a first direction at intervals in a surface layer of the first conductive type drift region, wherein the first direction is a direction parallel to an upper surface of the first conductive type drift region; A base region of a second conductivity type, covering the insulating dielectric layer and extending to cover the first conductivity type drift region between the insulating dielectric layers; At least one trench gate, each of the trench gates penetrates the base region of the second conductivity type in a second direction and extends into the drift region of the first conductivity type, each of the trench gates is spaced apart from the insulating dielectric layer in the first direction, and the second direction is perpendicular to the first direction; The emitter region of the first conductivity type is located in the base region of the second conductivity type on both sides of the trench gate.

2. The semiconductor device according to claim 1, wherein The thickness of the insulating dielectric layer is 3. The semiconductor device according to claim 1, wherein When the sum of the width of a single trench gate and the interval between two adjacent trench gates is 2.4 μm, the width of each insulating dielectric layer is 0.72 μm to 1.1 μm.

4. The semiconductor device according to claim 3, characterized in that The spacing between the insulating dielectric layer and the adjacent trench gate is 0.05 μm to 0.24 μm.

5. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein the substrate has a first conductivity type drift region; forming a plurality of insulating dielectric layers spaced apart in a first direction inside the first conductive type drift region, wherein the first direction is a direction parallel to an upper surface of the first conductive type drift region; forming a base region of a second conductivity type on the insulating dielectric layer, wherein the base region of the second conductivity type also extends to cover the drift region of the first conductivity type between the insulating dielectric layers; forming at least one trench gate, each of the trench gates penetrating the base region of the second conductivity type in a second direction and extending into the drift region of the first conductivity type, each of the trench gates being spaced apart from the insulating dielectric layer in the first direction, and the second direction being perpendicular to the first direction; An emitter region of the first conductivity type is formed in the base region of the second conductivity type at both sides of the trench gate by an ion implantation process, and a collector region of the second conductivity type is formed at the bottom of the drift region of the first conductivity type.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The thickness of the insulating dielectric layer is 7. The method for preparing a semiconductor device according to claim 5, characterized in that: The step of forming a plurality of insulating dielectric layers spaced apart in the first direction inside the first conductive type drift region comprises: forming a hard mask layer on the first conductive type drift region; Performing photolithography and etching processes on the hard mask layer to define a plurality of oxygen implantation regions spaced apart; An oxygen implantation isolation process is performed on the first conductive type drift region to form an insulating dielectric layer inside the first conductive type drift region corresponding to the oxygen implantation area.

8. The method for preparing a semiconductor device according to claim 5, wherein: The step of forming a base region of a second conductivity type on the insulating dielectric layer comprises: Performing an etching process on the first conductive type drift region to form a first trench structure, wherein the first trench structure exposes the insulating dielectric layer; Forming a base region of a second conductivity type in the first trench structure by an epitaxial process, wherein the base region of the second conductivity type further extends onto the drift region of the first conductivity type; A portion of the thickness of the second conductive type base region is removed to expose the first conductive type drift region.

9. The method for preparing a semiconductor device according to claim 5, wherein: When the sum of the width of a single trench gate and the interval between two adjacent trench gates is 2.4 μm, the width of each insulating dielectric layer is 0.72 μm to 1.1 μm.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The spacing between the insulating dielectric layer and the adjacent trench gate is 0.05 μm to 0.24 μm.

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