Preparation method of power device and power device
By etching the trench on the first and second surfaces of the substrate and filling with polysilicon and target materials, the problem of wafer warping is solved, and the product yield and performance of the power device are improved.
Patent Information
- Application Number
- CN202411921034.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-03-28
AI Technical Summary
During the preparation process of existing power devices, the wafer warpage due to the deep trench structure on the front of the wafer, which affects the product yield and performance of the device.
The substrate structure is formed by etching on the first surface of the substrate and filling polysilicon on the basis of the oxide layer; then forming a second trench on the opposite second surface, and filling the target material therein, so that the difference between the material stress of the target material and the material stress of the oxide layer is smaller than a preset threshold value, and finally a drain electrode is formed on the second target surface.
This method can offset the stress changes of the substrate, avoid wafer warping, and improve the product yield and performance of power devices.
Smart Images
Figure CN119730284A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a method for preparing a power device and a power device. Background Art
[0002] Power semiconductor devices, also known as power electronic devices, are semiconductor devices used to handle high voltage and high current, and are mainly used in power conversion and control circuits of power equipment. These devices usually operate at currents of tens to thousands of amperes and voltages of hundreds of volts or more, and are widely used in industries such as industry, automobiles, and communications equipment. During the manufacturing process of current power devices, it is usually necessary to form a deep groove structure on the front side of the wafer, which causes changes in wafer stress and causes wafer warping, thereby affecting the product yield and performance of the device. Summary of the invention
[0003] The present application provides a method for preparing a power device and a power device, which can solve the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer.
[0004] In order to achieve the above objectives, this application adopts the following technical solutions: An embodiment of the present application provides a method for preparing a power device, the method comprising: After etching a plurality of first grooves on the first surface of the substrate, a grooved surface is obtained; After oxidizing the grooved surface to form an oxide layer, a target grooved surface is obtained; After filling the grooves of the target groove-shaped surface with polysilicon, a substrate structure is obtained; forming a gate region and a source region on the substrate structure; After etching a second surface opposite to the first surface to form a plurality of second grooves, a target material is filled in the second grooves to obtain a second target surface, wherein the difference between the material stress of the target material and the material stress of the oxide layer is less than a preset threshold; A drain is formed on the second target surface.
[0005] As a possible implementation manner, etching a plurality of second grooves on a second surface opposite to the first surface includes: Second grooves opposite to each first groove are formed by etching on the second surface according to the etching positions of the first grooves.
[0006] As a possible implementation manner, if the oxide layer is silicon dioxide, filling the second trench with a target material includes: filling the second trench with silicon dioxide; Alternatively, a metal material is filled in the second trench, and the difference between the material stress of the metal material and the material stress of silicon dioxide is less than a preset threshold; Alternatively, the second trench is first oxidized to form a layer of silicon dioxide and then filled with the metal material.
[0007] As a possible implementation manner, forming a gate region and a source region on the substrate structure includes: After etching the groove position of the first surface of the substrate structure, an etched surface is obtained; After forming an isolation layer at the groove position of the etched surface, an isolation surface is obtained; After forming a gate oxide layer on the isolation surface, and filling polysilicon at the groove position on the gate oxide layer, a plurality of gate regions are formed; The source region is formed under the gate oxide layer.
[0008] As a possible implementation manner, after forming the source region under the gate oxide layer, the method further includes: After forming a passivation layer on the gate oxide layer, an etching hole is formed in the passivation layer to obtain a hole etching surface, wherein the etching hole is connected to the source region; A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source region through the etching hole.
[0009] As a possible implementation manner, forming the source region under the gate oxide layer includes: A first conductive type body region is first formed in the substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.
[0010] As a possible implementation manner, the depth of the second groove is the same as the depth of the first groove, and the depth is 2-10 um.
[0011] As a possible implementation manner, the opening width of the second groove is the same as the opening width of the first groove, and the opening width is 0.5-1 um.
[0012] As a possible implementation manner, a pitch of the second grooves is the same as a pitch of the first grooves.
[0013] As a possible implementation manner, an extending direction of the second groove is the same as an extending direction of the first groove.
[0014] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0015] In a second aspect of an embodiment of the present application, a power device is provided, the power device comprising: A substrate structure, the substrate structure comprising: a target grooved surface, the grooves of the target grooved surface being filled with silicon dioxide, wherein the target grooved surface is prepared by etching a first surface of a substrate to form a plurality of first grooves, and then oxidizing the grooved surface to form an oxide layer; A gate region and a source region, wherein the gate region and the source region are formed on the substrate structure; A drain electrode, wherein the drain electrode is formed on a second target surface, wherein the second target surface is obtained by etching a second surface of the substrate to form a plurality of second grooves, and filling the second grooves with a target material; The second surface is opposite to the first surface, and a difference between a material stress of the target material and a material stress of the oxide layer is smaller than a preset threshold.
[0016] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: The method for preparing a power device provided in an embodiment of the present application comprises the following steps: after etching a plurality of first grooves on the first surface of the substrate, a grooved surface is obtained; after oxidizing the grooved surface to form an oxide layer, a target grooved surface is obtained; after filling the grooves of the target grooved surface with polysilicon, a substrate structure is obtained; a gate region and a source region are formed on the substrate structure; after etching a plurality of second grooves on the second surface opposite to the first surface, a target material is filled in the second groove to obtain a second target surface, wherein the difference between the material stress of the target material and the material stress of the oxide layer is less than a preset threshold value; and a drain is formed on the second target surface. In this way, the stress of the first groove etched on the first surface of the substrate on the substrate can be offset, and the stress of the oxide layer on the first surface of the substrate on the substrate can be offset, thereby solving the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer, and further improving the product yield and product performance of the power device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A flow chart of a method for preparing a power device provided in an embodiment of the present application; Figure 2 A schematic diagram of a longitudinal section of a power device provided in an embodiment of the present application.
[0018] Reference numerals: 1-silicon dioxide, 2-polysilicon, 3-metal material, 4-gate region, 5-source region, 6-isolation layer, 7-gate oxide layer, 8-passivation layer, 9-metal electrode, 10-drain. DETAILED DESCRIPTION
[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0020] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0021] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.
[0022] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0023] The present application provides a method for preparing a power device, such as Figure 1 As shown, the method comprises the following steps: Step 101: After etching a plurality of first grooves on a first surface of a substrate, a grooved surface is obtained.
[0024] Step 102: After oxidizing the grooved surface to form an oxide layer, a target grooved surface is obtained.
[0025] Step 103 : After filling the grooves of the target grooved surface with polysilicon, a substrate structure is obtained.
[0026] Step 104: forming a gate region and a source region on the substrate structure.
[0027] Step 105, after etching a second surface opposite to the first surface to form a plurality of second grooves, a target material is filled in the second grooves to obtain a second target surface, and the difference between the material stress of the target material and the material stress of the oxide layer is less than a preset threshold.
[0028] Step 106: forming a drain on the second target surface.
[0029] The substrate is used as a carrier of the power device and mainly plays a supporting role. The substrate can be made of silicon, germanium or germanium silicon. In this embodiment, the substrate is preferably made of silicon, which is the most common, cheap and stable semiconductor material.
[0030] The substrate has a first surface and a second surface opposite to each other, wherein the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The first surface includes a plurality of first grooves, and the gate region and the source region of the power device are formed on the first surface. The second surface includes a plurality of second grooves, and the drain of the power device is formed on the surface at the opening position of the second groove.
[0031] Optionally, a conductive layer may be formed on the surface of the opening of the second trench, and the conductive layer may be used as the drain of the power device, wherein the target material is filled in the second trench until it is connected to the conductive layer.
[0032] Optionally, the depth of the second groove is the same as that of the first groove, and the depth is 2-10 um. The opening width of the second groove is the same as that of the first groove, and the opening width is 0.5-1 um. The spacing of the second groove is the same as that of the first groove, and the extension direction of the second groove is the same as that of the first groove.
[0033] Optionally, polysilicon is filled in the grooves of the target groove-shaped surface, and the filled polysilicon can be used as a shielding gate of the power device.
[0034] The difference between the material stress of the target material filled in the second groove and the material stress of the oxide layer is less than a preset threshold value. The preset threshold value can be set according to the degree to which the substrate is deformed due to the stress of different materials acting on the substrate, and this embodiment of the application does not specifically limit this.
[0035] Optionally, if the oxide layer is silicon dioxide, filling the second trench with a target material includes: Fill the second trench with silicon dioxide; or fill the second trench with metal material, and the difference between the material stress of the metal material and the material stress of silicon dioxide is less than a preset threshold; or first oxidize the second trench to form a layer of silicon dioxide and then fill it with the metal material.
[0036] Among them, the metal material can be a pure metal material or an alloy material, as long as the difference between the material stress of the metal material and the material stress of silicon dioxide is less than a preset threshold, and the embodiment of the present application does not make any specific limitation on this.
[0037] Furthermore, second grooves are formed on the second surface according to the etching positions of the first grooves, and are opposite to each of the first grooves.
[0038] That is, a second trench symmetrical to the first trench can be etched according to the first trench, the pitch of the second trench is the same as the pitch of the first trench, and the extension direction of the second trench is the same as the extension direction of the first trench.
[0039] It can be understood that by preparing a groove on the second surface of the substrate opposite to the first surface and filling the groove on the second surface with a material whose material stress is not much different from that of the silicon dioxide, the stress of the first groove etched on the first surface of the substrate on the substrate can be offset, and the stress of the oxide layer on the first surface of the substrate on the substrate can be offset, thereby solving the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer, and further improving the product yield and product performance of the power device. In addition, if the groove on the second surface is filled with metal and the drain of the power device is connected to the filled metal, the contact area of the power device can be increased, thereby reducing the internal resistance of the power device.
[0040] Optionally, the process of forming a gate region and a source region on the substrate structure in step 104 includes: After etching the groove position of the first surface of the substrate structure, an etched surface is obtained; After forming an isolation layer at the groove position of the etched surface, an isolation surface is obtained; After forming a gate oxide layer on the isolation surface, and filling polysilicon at the groove position on the gate oxide layer, a plurality of gate regions are formed; The source region is formed under the gate oxide layer.
[0041] Specifically, the process of forming the source region under the gate oxide layer may be: A first conductive type body region is first formed in the substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.
[0042] Optionally, after forming the source region under the gate oxide layer, the method further includes: After forming a passivation layer on the gate oxide layer, an etching hole is formed in the passivation layer to obtain a hole etching surface, and the etching hole is connected to the source region; a metal electrode is formed on the hole etching surface, and the metal electrode is connected to the source region through the etching hole.
[0043] It should be noted that a plurality of etching holes are formed by etching in the passivation layer, and each etching hole is connected to a corresponding source region.
[0044] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0045] The method for preparing a power device provided in an embodiment of the present application comprises the following steps: after etching a plurality of first grooves on the first surface of the substrate, a grooved surface is obtained; after oxidizing the grooved surface to form an oxide layer, a target grooved surface is obtained; after filling the grooves of the target grooved surface with polysilicon, a substrate structure is obtained; a gate region and a source region are formed on the substrate structure; after etching a plurality of second grooves on the second surface opposite to the first surface, a target material is filled in the second groove to obtain a second target surface, wherein the difference between the material stress of the target material and the material stress of the oxide layer is less than a preset threshold value; and a drain is formed on the second target surface. In this way, the stress of the first groove etched on the first surface of the substrate on the substrate can be offset, and the stress of the oxide layer on the first surface of the substrate on the substrate can be offset, thereby solving the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer, and further improving the product yield and product performance of the power device.
[0046] The present application embodiment provides a power device, which is prepared by using any one of the power device preparation methods provided in the present application embodiment. Figure 2 As shown, the power device includes: A substrate structure, the substrate structure comprising: a target grooved surface, the grooves of the target grooved surface being filled with polysilicon 2, wherein the target grooved surface is prepared by etching a first surface of a substrate to form a plurality of first grooves, and then oxidizing the grooved surface to form an oxide layer; A gate region 4 and a source region 5, wherein the gate region 4 and the source region 5 are formed on the substrate structure; A drain electrode 10, wherein the drain electrode 10 is formed on a second target surface, wherein the second target surface is obtained by etching a second surface of the substrate to form a plurality of second grooves, and filling the second grooves with a target material; The second surface is opposite to the first surface, and a difference between a material stress of the target material and a material stress of the oxide layer is smaller than a preset threshold.
[0047] Optionally, an etching position of a second groove in the second surface corresponds to a first groove.
[0048] Optionally, if the oxide layer is silicon dioxide 1 , the target material is silicon dioxide 1 , or metal material 3 , or silicon dioxide 1 and metal material 3 .
[0049] It should be noted that Figure 2 The example in which the oxide layer is silicon dioxide 1 and the target material is silicon dioxide 1 and metal material 3 is used for illustration.
[0050] Optionally, the power device further includes: An etched surface, wherein the etched surface is obtained by etching the groove position of the first surface of the substrate structure; A gate region 4, wherein the gate region 4 is prepared by forming an isolation layer 6 at the groove position of the etched surface to obtain an isolation surface, forming a gate oxide layer 7 on the isolation surface, and filling the groove position on the gate oxide layer 7 with gate polysilicon; A source region 5 , wherein the source region 5 is located in the substrate below the gate oxide layer 7 .
[0051] Optionally, the power device further includes: A hole-etched surface, wherein the hole-etched surface is obtained after forming a passivation layer 8 on the gate oxide layer 7 and then forming an etched hole in the passivation layer 8, wherein the etched hole is connected to the source region 5; A metal electrode 9 is formed on the surface of the hole etching, and the metal electrode 9 is connected to the source region 5 through the etching hole.
[0052] Optionally, the source region 5 includes: a first conductivity type body region and a second conductivity type doped region located on the first conductivity type body region.
[0053] Optionally, the depth of the second groove is the same as the depth of the first groove, and the depth is 2-10 um.
[0054] Optionally, the opening width of the second groove is the same as the opening width of the first groove, and the opening width is 0.5-1 um.
[0055] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0056] Regarding the specific limitations of the power device, reference may be made to the limitations of the method for preparing the power device in the embodiments of the present application, and no further details will be given here.
[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
[0058] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.
Claims
1. A method for preparing a power device, characterized in that: The method comprises: After etching a plurality of first grooves on the first surface of the substrate, a grooved surface is obtained; After oxidizing the grooved surface to form an oxide layer, a target grooved surface is obtained; After filling the grooves of the target groove-shaped surface with polysilicon, a substrate structure is obtained; forming a gate region and a source region on the substrate structure; After etching a second surface opposite to the first surface to form a plurality of second grooves, a target material is filled in the second grooves to obtain a second target surface, wherein the difference between the material stress of the target material and the material stress of the oxide layer is less than a preset threshold; A drain is formed on the second target surface.
2. The method according to claim 1, characterized in that The etching of a second surface opposite to the first surface to form a plurality of second grooves comprises: Second grooves opposite to each first groove are formed by etching on the second surface according to the etching positions of the first grooves.
3. The method according to claim 1, characterized in that If the oxide layer is silicon dioxide, filling the second trench with a target material comprises: filling the second trench with silicon dioxide; Alternatively, a metal material is filled in the second trench, and the difference between the material stress of the metal material and the material stress of silicon dioxide is less than a preset threshold; Alternatively, the second trench is first oxidized to form a layer of silicon dioxide and then filled with the metal material.
4. The method according to claim 1, characterized in that: The forming of a gate region and a source region on the substrate structure comprises: After etching the groove position of the first surface of the substrate structure, an etched surface is obtained; After forming an isolation layer at the groove position of the etched surface, an isolation surface is obtained; After forming a gate oxide layer on the isolation surface, and filling polysilicon at the groove position on the gate oxide layer, a plurality of gate regions are formed; The source region is formed under the gate oxide layer.
5. The method according to claim 4, characterized in that After forming the source region under the gate oxide layer, the method further comprises: After forming a passivation layer on the gate oxide layer, an etching hole is formed in the passivation layer to obtain a hole etching surface, wherein the etching hole is connected to the source region; A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source region through the etching hole.
6. The method according to claim 4, characterized in that The forming of the source region under the gate oxide layer comprises: A first conductive type body region is first formed in the substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.
7. The method according to claim 1, characterized in that The depth of the second groove is the same as that of the first groove, and the depth is 2-10 um. The opening width of the second groove is the same as that of the first groove, and the opening width is 0.5-1 um.
8. The method according to claim 1, characterized in that The pitch of the second grooves is the same as the pitch of the first grooves, and the extending direction of the second grooves is the same as the extending direction of the first grooves.
9. The method according to claim 6, characterized in that The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.
10. A power device, characterized in that: The power device comprises: A substrate structure, the substrate structure comprising: a target grooved surface, the grooves of the target grooved surface being filled with silicon dioxide, wherein the target grooved surface is prepared by etching a first surface of a substrate to form a plurality of first grooves, and then oxidizing the grooved surface to form an oxide layer; A gate region and a source region, wherein the gate region and the source region are formed on the substrate structure; A drain electrode, wherein the drain electrode is formed on a second target surface, wherein the second target surface is obtained by etching a second surface of the substrate to form a plurality of second grooves, and filling the second grooves with a target material; The second surface is opposite to the first surface, and a difference between a material stress of the target material and a material stress of the oxide layer is smaller than a preset threshold.