Manufacturing method of HDP-type shield gate trench-type MOSFET

Abstract

The invention discloses a manufacturing method of an HDP-type shield gate trench-type MOSFET, and relates to the technical field of semiconductors. A grid electrode and a shielding grid electrode region are defined on the hard mask, source electrode polycrystalline silicon is etched for the first time in the groove region, the etching depth is smaller than the design depth, and the mask plate is removed after etching is completed. Subsequently, wet etching is carried out on the field dielectric layer, the source polycrystalline silicon is etched for the second time, the current etching depth is equal to the field dielectric layer etched by the wet method, and meanwhile, the sum of the two times of source polycrystalline silicon etching depths is equal to the designed source polycrystalline silicon etching depth of the device; subsequently filling a grid electrode and a source electrode isolation layer, growing a grid oxide layer, continuously filling grid electrode polycrystalline silicon, and then etching the grid electrode polycrystalline silicon; and defining a p-body region and a source region by using a P-body mask and a source region mask. According to the manufacturing method, the problem that cavities are formed in the grid electrode and the source electrode isolation oxide layer in the HDP type SGT manufacturing process is effectively solved, the cavities are filled with grid electrode polycrystalline silicon due to the fact that the cavities are too large, the area is floating from the device structure, and the device has the mistaken opening risk.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a HDP shielded gate trench MOSFET. Background Art

[0002] The MOSFET manufacturing process usually deposits a layer of silicon oxide on the epitaxial layer as a hard mask, and then uses photolithography and etching processes to make deep trenches. A thick oxide film grows in the deep trenches. This oxide film is usually called a field oxide layer. Subsequently, polysilicon is filled, and a portion of the polysilicon on the surface and in the trench is removed to form a shielding gate, and the field oxide layer is etched using a wet method.

[0003] Since wet etching is isotropic etching, part of the oxide layer in contact with the corrosive liquid will be corroded away. Here, field oxide layer corrosion has also considered dry etching, which can be roughly understood as gas etching, that is, the plasma bombardment method etches away the oxide layer. This process method brings a large degree of plasma damage, which is unacceptable to the device, so this process method is usually not used. After wet etching, the trench sidewall will retain a 200-300A field oxide layer (because the HDP process forms a barrier oxide layer, which causes a certain degree of damage to silicon. In order to reduce the risk of silicon damage, a certain thickness of field oxide will be retained. The thickness of the field oxide retention depends on the HDP process filling capability and device size design), which is used for the barrier oxide layer formed by the subsequent HDP process method. Assuming that the field oxide layer thickness is 1500A, 300A is retained after etching. Fig.10 , about 1200A will be consumed in the Z direction, and about 1000A of field oxygen will be consumed in the Y direction. As shown in the figure, there are two areas in the transition area between the gate and the source. The difficulty of filling these two areas with the HDP process is about 3.5~4 times that of the CELL area, which usually far exceeds the filling capacity of the HDP process, so the two areas will not be filled with the HDP oxide layer. Subsequently, the HDP oxide layer is partially removed, and some wet process processes during the removal process will further enlarge the two unfilled areas, causing the subsequent gate polysilicon to be filled into this area.

[0004] To address the above problems, the current common solutions include: 1. Adding a mask when removing the field oxide layer will slightly reduce the horizontal line etching rate. However, when the field oxide layer of the high-voltage product is thicker, the effect of adding a mask will become worse and worse. Although this method can solve the problem of filling voids to a certain extent, the series of expenses brought about by adding a mask also make this solution less cost-effective.

[0005] 2. After etching the gate polysilicon, the polysilicon in the deeper active area is difficult to remove due to the existence of voids. Therefore, a mask is added simultaneously. This mask protects the active area, exposing the voids, and the polysilicon is removed by dry etching. When this solution is dry-etched to remove the polysilicon filling the voids, even with a high etching selectivity, a certain thickness of the gate oxide layer will be consumed. If a large amount of polysilicon needs to be removed in this step, when the gate oxide layer is consumed, a large amount of silicon will be etched, resulting in damage to the device structure.

[0006] Therefore, the two traditional solutions have lost some competitiveness and have certain failure risks. Therefore, on the basis of controlling the preparation cost, solving the filling risk caused by excessive lateral and longitudinal corrosion during the wet process and realizing industrialized production are technical problems that need to be solved urgently in the industry. Summary of the invention

[0007] In view of the above problems, the present invention provides a method for manufacturing a HDP shielded gate trench MOSFET which can effectively avoid the generation of voids and further improve the stability of static parameters and dynamic parameters of the device.

[0008] A method for manufacturing a HDP shielded gate trench MOSFET comprises the following steps: Step 1, etching the epitaxial layer to form a plurality of deep trenches; Step 2, growing a field oxide layer covering the deep trench on the epitaxial layer; Step 3, filling the deep trench with shield gate polysilicon to form source polysilicon, and performing a first etching on the shield gate polysilicon in the source region to etch the highest interface of the shield gate polysilicon to be flush with the highest point of the field oxide layer interface; Step 4, performing a second etching on the shield gate polysilicon in the source region, the etching depth being equal to the final designed etching depth of the device minus the thickness of the field oxide layer; Step 5: wet etching, finally retaining a 200-300A field oxide layer in the trench and on the top of the trench, exposing the top of the shield gate polysilicon; Step six, performing a third etching on the shielding gate polysilicon in the source region and the step corner region at the end, and the etching depth is the thickness of the field oxide layer.

[0009] Specifically, after etching in step three, the highest point of the source is flush with the surface of the field oxide layer.

[0010] Specifically, it also includes: Step seven, after the shield gate is defined, HDP oxide is filled. After filling, the excess HDP oxide is removed using the CMP process. The active area is defined using a mask to form a gate and source isolation oxide layer. Finally, gate oxide is deposited and gate polysilicon is filled.

[0011] Specifically, after step seven is completed, it also includes: Step eight, using the P-body and source area masks to define the p-body area and source area, respectively, perform P-body and source area implantation, and finally use the mask to define the contact holes.

[0012] Specifically, the contact holes include terminal trench contact holes, shielding gate contact holes, gate contact holes and source contact holes.

[0013] Specifically, it also includes step nine, growing a top metal, then etching the top metal, and finally performing a passivation treatment to form a complete MOSFET structure.

[0014] Beneficial effects of the present invention: The prior art has improved the manufacturing process of the shielding gate and the method for forming the shielding gate and the gate isolation oxide layer. The source is formed and etched according to the existing traditional process. After etching, the highest point of the source polysilicon is flush with the field oxide layer. Continue to check and clean after etching, and measure the thickness of the field oxide layer consumed by etching. Use a mask to define the etched part of the source polysilicon, perform the first source polysilicon etching, remove the field oxide layer after removing the mask, and the depth of the polysilicon etched in this step is the device design depth minus the thickness of the field oxide layer. Finally, the source polysilicon is etched again, and the depth of this etching is the thickness of the field oxide layer removed after the first etching. In this way, the shielding gate is defined by two polysilicon etchings, and the filling risk caused by the horizontal and vertical excessive corrosion of the wet process is greatly solved. There is almost no phenomenon of different depth-to-width ratios of filling in different areas in the traditional process. Through reasonable process matching and advanced process technology development, the upper limit of the process capability of the HDP type MOSFET and the stable process window are improved without increasing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of the deep groove area. Figure 2 is a schematic diagram of the growth field oxide layer structure; Figure 3 is a schematic diagram of a shield gate polysilicon structure filled in a deep trench; Figure 4 yes Figure 3 A partial enlarged schematic diagram after filling in the middle; Figure 5 This is a schematic diagram of the first etching of the shield gate polysilicon structure; Figure 6 It is a schematic diagram of the local method after etching in the figure; Figure 7 It is a schematic diagram of the structure of removing the field oxide layer in the top area; Figure 8 yes Figure 7 Schematic diagram of the method structure in the middle A area; Fig. 9 It is a schematic diagram of the structure of step seven; Fig.10 yes Fig. 9 Schematic diagram of the enlarged structure of a local area; Fig.11 is a schematic diagram of the hole etching structure; Fig.12 is a schematic diagram of the growth top metal structure; Fig.13 This is the BV_250uA tape-out verification picture; Fig.14 It is a failure analysis and hot spot location diagram; Fig.15 It is a schematic diagram of FIB analysis; Fig.16 It is a chip tape-out picture of the preparation method of the present invention; In the figure, 100 is the substrate, 200 is the epitaxial layer, 300 is the deep trench, 400 is the field oxide layer, 500 is the shielding gate polysilicon, 600 is the gate polysilicon, 710 is the terminal trench contact hole, 720 is the shielding gate contact hole, 730 is the gate contact hole, 740 is the source contact hole, 810 is the definition of the source region, and 820 is the definition of the gate region. DETAILED DESCRIPTION

[0016] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0017] The traditional HDP shielded gate trench MOSFET manufacturing method was used for tape-out verification. After tape-out, it was found that the BV_250uA of some dies was low. The specific data was reflected by processing and mapping as follows: like Fig.13 As shown, the red die is the BV_250uA failure. After failure analysis, the hotspot location is found to be Fig.14 Middle red rectangle location.

[0018] like Fig.15As shown, after performing FIB analysis on the cross section, it was found that gate polysilicon existed in the cavities that were not filled with HDP oxide on both sides of the source polysilicon, which are the rectangular areas in the figure.

[0019] Reference below Figure 1-12 describe the invention; A method for manufacturing a HDP shielded gate trench MOSFET comprises the following steps: Step 1: A plurality of deep trenches 300 are formed by etching the epitaxial layer 200 using a mask. Figure 1 As shown; The epitaxial layer 200 is disposed on the substrate 100; Step 2: growing a field oxide layer 400 covering the deep trench 300 on the epitaxial layer 200, such as Figure 2 As shown; Step 3: fill the deep trench 300 with shielding gate polysilicon 500, form the source and etch it according to the existing conventional process. It is best if the highest point of the source is flush with the surface of the field oxide layer 400 after etching. Figure 3-4 As shown, the first etching of the shielding gate polysilicon 500 in the source region is to etch the highest interface of the shielding gate polysilicon 500 to be flush with the highest point of the interface of the field oxide layer 400.

[0020] Step 4: For the source region ( Figure 5 The shield gate polysilicon 500 at the two deep trenches 300 on the right side of the middle is etched for the second time, and the etching depth is equal to the final designed etching depth of the device minus the thickness of the field oxide layer 400, as shown in FIG. Figure 5-6 As shown; Step 5: Figure 7 As shown, the field oxide layer 400 in the top region is removed to expose the top of the shielding gate polysilicon 500; In this case, the field oxide layer 400 is etched down to a position close to the top surface of the epitaxial layer 200. The field oxide layer 400 on the side of the source region is etched down to a position not higher than the top surface of the source shielding gate polysilicon. The field oxide layer 400 is removed to ensure that a certain thickness of the field oxide layer 400 is retained on the side wall of the deep trench 300. Since plasma will damage silicon during the HDP oxide layer deposition process, retaining a certain thickness of the field oxide layer 400 will protect the silicon and prevent damage in subsequent processes.

[0021] Step 6: Perform a third etching on the shield gate polysilicon 500 in the source region and the step corner region at the end, and the etching depth is the thickness of the field oxide layer 400; The step corner area is Figure 8In the area wrapped by the yellow line at the middle step, part of the shield gate polysilicon 500 that is higher than the field oxide layer 400 is completely etched away. By etching the source area and the nearby shield gate polysilicon twice, the shield gate is defined. The final two etching depths are the shield gate height designed for the device.

[0022] The two areas that are difficult to fill with the traditional HDP process are Figure 8 At the yellow shielding gate polysilicon 500, after removing the polysilicon here through this solution, the depth of HDP oxide filling remains unchanged, and the width increases by more than three times, so there will be no filling problem. The morphology here is the same as other locations. Because the shielding gate polysilicon 500 is etched at the highest point above the silicon interface for the first time, Figure 8 In the process, while removing the polysilicon in the Y direction, the polysilicon in the Z direction will also be consumed. Therefore, after the Y direction area is finally removed, the highest point of the polysilicon interface in the Z direction area is almost flush with the highest point of the silicon interface, and the Z reverse interface cannot be too much lower than the silicon interface. If the interface is too low, there will be a risk of hole miss, so the process here is also crucial.

[0023] Step 7: After the shield gate is defined, HDP oxide (HDP: High-Density Plasma process) is filled, and the excess HDP oxide is removed by CMP process. The subsequent steps are the same as the traditional manufacturing method, using a mask to define the active area, forming a gate and source isolation oxide layer, and finally depositing gate oxide and filling the gate polysilicon 600. Figure 9-10 As shown; Step 8: Figure 11-12 As shown, this step is the same as the traditional manufacturing step. The P-body and source regions are defined using the P-body and source region masks, and the P-body and source region are implanted separately. Finally, the contact holes are defined using the mask (such as Fig.11 As shown, the contact holes include a terminal trench contact hole 710, a shielding gate contact hole 720, a gate contact hole 730, and a source contact hole 740), and hole etching and hole injection are performed. Fig.11 It can be clearly observed from the circled area that since there is no void here, the state of the PN node here is consistent with that of the adjacent parts, and there is no difference in depth.

[0024] Step 9: This step is the same as the traditional junction manufacturing process. The top metal is grown, then the top metal is etched, and finally the passivation treatment is performed to form a complete MOSFET structure. Fig.12 As shown, the top 810 is used to define the source region, and 820 is used to define the gate region. Fig.12 It is the final structure of the present invention (excluding ILD, top metal and passivation layer structure).

[0025] The above solution has been verified by multiple tape-outs of products with different voltage platforms and different pitch sizes. The HDP shielded gate MOSFET that continues to be tape-outed with this method has been repeatedly verified. The polish analysis method is used to collect the final morphology of different products. Compared with the traditional process, there is no void in the same area, such as Fig.16 shown.

[0026] In summary, the source is formed and etched according to the existing traditional process. After etching, the highest point of the source is higher than the silicon surface or flush with the field oxide layer. This is the best, and the highest point cannot exceed the thickness of the field oxide layer. Continue to check and clean after etching, and measure the thickness of the field oxide layer at the same time. Use the mask to define the part of the source polysilicon to be etched, and perform the first source polysilicon etching. After removing the mask, remove the field oxide layer. The length of the polysilicon etched in this step is the device design length minus the thickness of the field oxide layer. Finally, the source polysilicon is etched again. The length of this etching is the thickness of the field oxide layer removed after the first etching. In this way, the shielding gate is defined by two polysilicon etchings. It should be noted that the etching gas composition needs to be adjusted for the second etching. Compared with the first etching, the lateral etching rate is increased, and the vertical etching rate is relatively slow. Since there is no void here, when the P-body and source are injected later, the original traditional solution will cause abnormal depth of the P-body and source injection node due to the void. The voids are of different sizes, which will cause the depth of the node to be different. When the device performance rises to a certain level, the excessively deep and uneven PN node here will be a major unstable factor. The mask is then used to define the PW area, hole area, metal area, passivation layer area, etc., so as to form the complete structure of the MOSFET.

[0027] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a HDP shielded gate trench MOSFET, characterized in that: The following steps are involved: Step 1: etching the epitaxial layer (200) to form a plurality of deep trenches (300); Step 2: growing a field oxide layer (400) covering the deep trench (300) on the epitaxial layer (200); Step three, filling the shielding gate polysilicon (500) in the deep trench (300) to form source polysilicon, and performing a first etching on the shielding gate polysilicon (500) in the source region to etch the highest interface of the shielding gate polysilicon (500) to be flush with the highest interface of the field oxide layer (400); Step 4, performing a second etching on the shield gate polysilicon (500) in the source region, wherein the etching depth is equal to the final designed etching depth of the device minus the thickness of the field oxide layer (400); Step 5: wet etching, finally retaining a 200-300A field oxide layer (400) in the trench and on the top of the trench, exposing the top of the shielding gate polysilicon (500); Step six, performing a third etching on the shielding gate polysilicon (500) in the source region and the step corner region at the end, wherein the etching depth is equal to the thickness of the field oxide layer (400).

2. A method for manufacturing a HDP shielded gate trench MOSFET according to claim 1, characterized in that: After etching in step three, the highest point of the source is flush with the surface of the field oxide layer (400).

3. A method for manufacturing a HDP shielded gate trench MOSFET according to claim 1, characterized in that: Also includes: Step 7: After the shielding gate is defined, HDP oxide is filled, and the excess HDP oxide is removed by CMP process. The active area is defined by using a mask, a gate and source isolation oxide layer is formed, and finally gate oxide is deposited and gate polysilicon is filled (600).

4. A method for manufacturing a HDP shielded gate trench MOSFET according to claim 3, characterized in that: After step seven is completed, it also includes: Step eight, using the P-body and source area masks to define the p-body area and source area, respectively, perform P-body and source area implantation, and finally use the mask to define the contact holes.

5. A method for manufacturing a HDP shielded gate trench MOSFET according to claim 4, characterized in that: The contact holes include a terminal groove contact hole (710), a shielding grid contact hole (720), a gate contact hole (730) and a source contact hole (740).

6. A method for manufacturing a HDP shielded gate trench MOSFET according to claim 4, characterized in that: The method also includes step nine, growing a top metal layer, then etching the top metal layer, and finally performing a passivation treatment to form a complete MOSFET structure.

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