Field effect transistor device with high gate oxide intensity and preparation method

Abstract

The invention discloses a field effect transistor device with high gate oxide intensity and a preparation method, and relates to the technical field of semiconductors. A layer of high-K dielectric material with a dielectric constant higher than that of SiO2 is prepared on the top surface of a SiC Drift layer of a JFET (Junction Field Effect Transistor) region, the materials can comprise Al2O3, TiO2, ZrO2, HfO2 and the like, and the high-dielectric constant material is more difficult to be subjected to electric breakdown, so that the high-K dielectric can better improve the gate oxide strength of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, and the long-term stable use of the device is improved. However, because the high-K dielectric cannot be formed by directly growing in an oxidation mode like SiO2 and can only be prepared in a deposition mode, in order to avoid the situation that the conduction performance of the device becomes poor after a gate pole is opened, a SiO2 gate oxide layer still grows above a channel region in an oxidation mode, so that the conduction performance of the device is not excessively influenced, and the reliability of the device is improved. And meanwhile, the gate oxide strength of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a field effect transistor device with high gate oxide strength and a preparation method thereof. Background Art

[0002] With the development of society and the innovation of technology, the requirements for electronic components in many fields such as automobiles and photovoltaic energy storage are becoming more and more stringent. In the past, traditional Si-based power devices occupied almost all scenarios in these application fields, but at present, Si-based power devices have been difficult to meet the needs of these rapidly developing applications. In order to solve this bottleneck, the third-generation wide bandgap semiconductor power devices represented by SiC have excellent performance, which can make the system have higher transmission energy efficiency, and are therefore considered to be the core products in the future in the fields of high voltage, high temperature, and high frequency applications.

[0003] Compared with Si MOSFET and SiIGBT, SiC MOSFET can have both good static conduction and dynamic switching performance due to the advantages of device structure and its own materials. It is very popular in the 800V electrical architecture platform of new energy vehicles and high-power application scenarios of photovoltaics, and has begun to replace Si-based devices on a large scale. However, SiC MOSFET also has disadvantages. The gate oxide layer of SiC MOSFET is directly grown by oxidation. However, since the material contains C elements, the grown SiO2 oxide layer has a large interface state density and many defects, and it is difficult to withstand high electric field strength. If the design is improper, it is easy to cause the gate oxide layer to break down and fail during use. This is also a major problem that has always plagued SiC MOSFET. Therefore, how to improve the gate oxide strength of SiC MOSFET is a technical problem that needs to be solved urgently in this case. Summary of the invention

[0004] In view of the above problems, the present invention provides a field effect transistor device with high gate oxide strength and a preparation method thereof, which does not affect the conduction performance of the device too much and improves the gate oxide strength of the device at the same time.

[0005] The technical solution of the present invention is: A method for preparing a field effect transistor device with high gate oxide strength comprises the following steps: S100, forming a SiC Drift layer on the top surface of the SiC Sub layer by epitaxial deposition; S200, forming a P-body region on the top surface of the SiC Drift layer by ion implantation; S300, forming an NP region and a PP region in sequence on the top surface of the P-body region by ion implantation, and activating the implanted regions of the P-body region, the NP region and the PP region by high temperature annealing; S400, forming a gate oxide layer on the top surfaces of the SiC Drift layer, the P-body region and the NP region by dry oxygen oxidation growth; S500, forming a high-K dielectric layer on the top surface of the SiC Drift layer and the gate oxide layer at the JFET region by deposition; S600, forming a Poly layer on the top surface of the gate oxide layer and the high-K dielectric by depositing polysilicon; S700, forming an isolation dielectric layer on the top surface of the NP region and the Poly layer by oxide deposition; S800, forming an ohmic contact alloy layer on the top surface of the NP region and the PP region by sputtering or depositing Ni metal followed by thermal annealing; S900 , forming a front electrode metal layer on top surfaces of the isolation dielectric layer and the ohmic contact alloy layer by metal sputtering.

[0006] Specifically, in step S100 , the thickness of the SiC Sub layer is 120um-450um, and the thickness of the SiC Drift layer is 5um-15um.

[0007] Specifically, in step S200, the depth of the P-body region is 0.5um-2um, and the doping concentration is 1E17-5E18cm -2 .

[0008] Specifically, in step S300, the depth of the NP region is 0.2um-1.5um, and the doping concentration is 1E18-5E19cm -2 .

[0009] Specifically, in step S300, the depth of the PP region is 0.2um-2um, and the doping concentration is 1E18-5E19cm -2 .

[0010] Specifically, in step S500, the thickness of the gate oxide layer is 40nm-60um.

[0011] Specifically, in step S500, the high-K dielectric material includes Al2O3, TiO2, ZrO2 or HfO2.

[0012] Specifically, in step S900, the top surfaces of the isolation dielectric layer and the ohmic contact alloy layer are sputtered by Ti and AlCu to form a front electrode metal layer.

[0013] Specifically, the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

[0014] A field effect transistor device with high gate oxide strength, comprising a SiC Sub layer (1), a SiC Drift layer, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; The SiC Drift layer is provided with: A pair of P-body regions are provided, each extending downward from the top surface of the SiC Drift layer; a JFET region is formed between the pair of P-body regions; A pair of NP regions are provided, each extending downward from the top surface of the P-body region and having a spacing between them and the bottom surface of the P-body region; A pair of PP regions are provided, each extending downward from the top surface of the P-body region and connected to the NP region; a gap is provided between the bottom surface of the PP region and the bottom surface of the P-body region; A pair of gate oxide layers are provided, which are respectively located on the top surfaces of the SiC Drift layer, the P-body region and the NP region; A high-K dielectric is disposed on the top surface of the pair of gate oxide layers, and the bottom surface of the middle region thereof is connected to the SiC Drift layer; A Poly layer, disposed on the top surface of the gate oxide layer and the high-K dielectric; The isolation dielectric layer is disposed on the Poly layer, and its side portion extends downward to connect with the NP region.

[0015] The present invention aims at the problem that the top surface gate oxide layer of the JFET region of the planar SiC MOSFET device is prone to breakdown. By preparing a layer of high-K dielectric material with a higher dielectric constant than SiO2 on the top surface of the SiC Drift layer in the JFET region, these materials may include Al2O3, TiO2, ZrO2, HfO2, etc. Since the high dielectric constant material is more difficult to be electrically broken down, the high-K dielectric can better improve the gate oxygen strength of the SiC MOSFET device, thereby improving the long-term stable use of the device. However, since the high-K dielectric cannot be directly grown and formed by oxidation like SiO2, it can only be prepared by deposition and other methods. In order to avoid the conduction performance of the device from deteriorating after the gate is turned on, an oxidation method is still used to grow a layer of SiO2 gate oxide layer above the channel region, which neither affects the conduction performance of the device too much nor improves the gate oxygen strength of the device at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of SiC MOSFET of the present invention; Figure 2 is a structural schematic diagram of step S100 of the present invention; Figure 3 is a schematic structural diagram of step S200 of the present invention; Figure 4 is a schematic structural diagram of step S300 of the present invention; Figure 5 is a schematic structural diagram of step S400 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a schematic diagram of the structure of step S1100 of the present invention; In the figure, 1 is SiC Sub, 2 is SiCDrift, 3 is P-body region, 4 is NP region, 5 is PP region, 6 is gate oxide layer, 7 is high-K dielectric, 8 is Poly layer, 9 is isolation dielectric layer, 10 is ohmic contact alloy layer, and 11 is front electrode metal layer. DETAILED DESCRIPTION

[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0018] A field effect transistor device with high gate oxide strength comprises the following steps: S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition; In step S100 , the thickness of the SiC Sub layer 1 is 120um-450um, and the thickness of the SiC Drift layer 2 is 5um-15um.

[0019] S200, forming a P-body region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation; The depth of the P-body region 3 in step S200 is 0.5um-2um, and the doping concentration is 1E17-5E18cm -2 .

[0020] S300, forming an NP region 4 on the top surface of the P-body region 3 by N ion implantation; The depth of the NP region 4 in step S300 is 0.2um-1.5um, and the doping concentration is 1E18-5E19cm -2 .

[0021] S400, forming a PP region 5 connected to the NP region 4 on the top surface of the P-body region 3 by Al ion implantation; The depth of the PP region 5 in step S400 is 0.2um-2um, and the doping concentration is 1E18-5E19cm -2 .

[0022] S500, activating and forming the implanted regions of the P-body region 3, the NP region 4 and the PP region 5 by high temperature annealing; The high temperature annealing condition in step S500 is 1600°C-1900°C.

[0023] S600, forming a gate oxide layer 6 on the top surfaces of the SiC Drift layer 2, the P-body region 3 and the NP region 4 by dry oxygen oxidation growth; The thickness of the gate oxide layer 6 in step S600 is 40nm-60um.

[0024] S700, forming a layer of high-K dielectric 7 (a material having a higher dielectric constant than the gate oxide layer 6) on the top surface of the SiC Drift layer 2 and the gate oxide layer 6 at the JFET region by deposition; The material of the high-K dielectric 7 in step S700 is mainly metal oxide or alloy, such as Al2O3, TiO2, ZrO2 or HfO2.

[0025] S800, forming a Poly layer 8 on the top surfaces of the gate oxide layer 6 and the high-K dielectric 7 by polysilicon deposition; S900, forming an isolation dielectric layer 9 on the top surfaces of the NP region 4 and the Poly layer 8 by oxide deposition; S1000, forming an ohmic contact alloy layer 10 on the top surfaces of the NP region 4 and the PP region 5 by sputtering or depositing Ni metal followed by thermal annealing; The Ni metal thickness in step S1000 is 0.3um-1um.

[0026] S1100, on the top surface of the isolation dielectric layer 9 and the ohmic contact alloy layer 10 is formed by sputtering Ti and AlCu metals on the front electrode metal layer 11; In step S1100 , the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

[0027] A field effect transistor device with high gate oxide strength comprises a SiC Sub layer 1, a SiCDrift layer 2, an ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top; The SiC Drift layer 2 is provided with: A pair of P-body regions 3 are provided, each extending downward from the top surface of the SiC Drift layer 2; a JFET region is formed between the pair of P-body regions 3; A pair of NP regions 4 are provided, each extending downward from the top surface of the P-body region 3 and having a gap between them and the bottom surface of the P-body region 3; A pair of PP regions 5 are provided, each extending downward from the top surface of the P-body region 3 and connected to the NP region 4; a gap is provided between the bottom surface of the PP region 5 and the bottom surface of the P-body region 3; A pair of gate oxide layers 6 are provided, which are respectively located on the top surfaces of the SiC Drift layer 2, the P-body region 3 and the NP region 4; A high-K dielectric 7 is disposed on the top surface of a pair of gate oxide layers 6, and the bottom surface of the middle region thereof is connected to the SiC Drift layer 2; The Poly layer 8 is arranged on the top surface of the gate oxide layer 6 and the high-K dielectric 7; a groove is provided on the top edge, because the middle bottom of the Poly layer 8 is a high-K dielectric, and the high-K dielectric is formed by deposition, and its thickness is thicker than the gate oxide layer 6, so the bottom of the Poly layer 8 is high in the middle and narrow on both sides, resulting in the formation of a shape of high in the middle and narrow on both sides after the Poly layer 8 is deposited.

[0028] The isolation dielectric layer 9 is disposed on the Poly layer 8 , and its side portion extends downward to connect with the NP region 4 .

[0029] The outer sides of the isolation dielectric layer 9 are respectively connected to the front electrode metal layer 11 and the ohmic contact alloy layer 10 , and the inner sides are respectively connected to the gate oxide layer 6 and the Poly layer 8 .

[0030] The bottom surface of the ohmic contact alloy layer 10 is connected to the NP region 4 and the PP region 5 respectively.

[0031] The present invention prepares a layer of high-K dielectric material with a higher dielectric constant than SiO2 on the top surface of the SiC Drift layer in the JFET region of the device. Since the high dielectric constant material is more difficult to be electrically broken down, the high-K dielectric can better improve the gate oxygen strength of the device. However, since the high-K dielectric cannot be directly grown by oxidation like SiO2, it can only be prepared by deposition and other methods. In order to avoid the conduction performance of the device being deteriorated after the gate is turned on, an oxidation method is still used to grow a layer of SiO2 gate oxide layer above the channel region, which does not affect the conduction performance of the device too much and improves the gate oxygen strength of the device at the same time.

Claims

1. A method for preparing a field effect transistor device with high gate oxide strength, characterized in that: The steps include: S100, forming a SiC Drift layer (2) on the top surface of the SiC Sub layer (1) by epitaxial deposition; S200, forming a P-body region (3) on the top surface of the SiC Drift layer (2) by ion implantation; S300, forming an NP region (4) and a PP region (5) in sequence on the top surface of the P-body region (3) by ion implantation, and activating the implanted regions of the P-body region (3), the NP region (4) and the PP region (5) by high temperature annealing; S400, forming a gate oxide layer (6) on the top surfaces of the SiC Drift layer (2), the P-body region (3) and the NP region (4) by dry oxygen oxidation growth; S500, forming a layer of high-K dielectric (7) on the top surface of the SiC Drift layer (2) and the gate oxide layer (6) at the JFET region by deposition; S600, forming a Poly layer (8) on the top surfaces of the gate oxide layer (6) and the high-K dielectric (7) by means of polysilicon deposition; S700, forming an isolation dielectric layer (9) on the top surface of the NP region (4) and the Poly layer (8) by oxide deposition; S800, forming an ohmic contact alloy layer (10) on the top surface of the NP region (4) and the PP region (5) by Ni metal sputtering or deposition followed by thermal annealing; S900, forming a front electrode metal layer (11) on the top surfaces of the isolation dielectric layer (9) and the ohmic contact alloy layer (10) by metal sputtering.

2. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S100 , the thickness of the SiC Sub layer (1) is 120 um-450 um, and the thickness of the SiC Drift layer (2) is 5 um-15 um.

3. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S200, the depth of the P-body region (3) is 0.5um-2um, and the doping concentration is 1E17-5E18cm -2 .

4. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S300, the depth of the NP region (4) is 0.2um-1.5um, and the doping concentration is 1E18-5E19cm -2 .

5. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S300, the depth of the PP region (5) is 0.2um-2um, and the doping concentration is 1E18-5E19cm -2 .

6. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S500, the thickness of the gate oxide layer (6) is 40nm-60um.

7. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S500, the high-K dielectric (7) material includes Al2O3, TiO2, ZrO2 or HfO2.

8. The method for preparing a field effect transistor device with high gate oxide strength according to claim 1, characterized in that: In step S900, the top surfaces of the isolation dielectric layer and the ohmic contact alloy layer are sputtered by Ti and AlCu to form a front electrode metal layer.

9. The method for preparing a field effect transistor device with high gate oxide strength according to claim 8, characterized in that: The thickness of Ti metal is 0.1um-0.6um, and the thickness of AlCu metal is 2um-5um.

10. A field effect transistor device with high gate oxide strength, prepared by the method for preparing a field effect transistor device with deep high gate oxide strength according to any one of claims 1 to 9, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), an Ohmic contact alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with: A pair of P-body regions (3) are provided, each extending downward from the top surface of the SiC Drift layer (2); a JFET region is formed between the pair of P-body regions (3); A pair of NP regions (4) are provided, each extending downward from the top surface of the P-body region (3) and having a spacing between the NP regions (4) and the bottom surface of the P-body region (3); A pair of PP regions (5) are provided, each extending downward from the top surface of the P-body region (3) and connected to the NP region (4); a gap is provided between the bottom surface of the PP region (5) and the bottom surface of the P-body region (3); A pair of gate oxide layers (6) are provided, and are respectively located on the top surfaces of the SiC Drift layer (2), the P-body region (3), and the NP region (4); A high-K dielectric (7) is disposed on the top surfaces of a pair of gate oxide layers (6), wherein the bottom surface of a central region thereof is connected to the SiC Drift layer (2); A Poly layer (8) disposed on the top surface of the gate oxide layer (6) and the high-K dielectric (7); An isolation dielectric layer (9) is disposed on the Poly layer (8), with a side portion extending downward to connect with the NP region (4).

Images