Preparation method of trench gate SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) capable of reducing gate-oxide electric field

Abstract

The invention relates to the technical field of semiconductors, in particular to a preparation method of a trench gate SiC MOSFET capable of reducing a gate-oxide electric field, according to the preparation method, a source electrode is made into an inclined trench, then P-type doping is injected to form an inclined P well shielding region, the inclined shielding region can shield the electric field to reduce a peak electric field at the gate-oxide bottom and can guide current to flow away obliquely and downwards, and therefore the gate-oxide electric field can be reduced; the utilization rate of the second epitaxial layer is improved; the first electric field absorption layer and the second electric field absorption layer utilize different directions of the same mask plate, the number of the mask plates is saved, the electric field absorption layers can further reduce the peak electric field at the bottom of the gate oxide layer, the saturation current density of the device can be reduced under the condition that the on-resistance is not increased, and the short-circuit tolerance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a trench gate SiC MOSFET capable of reducing a gate oxide electric field. Background Art

[0002] As a third-generation semiconductor material, silicon carbide (SiC) has many advantages such as large bandgap, high melting point, low dielectric constant, high breakdown field strength, high saturated electron drift rate, high thermal conductivity and stable chemical properties. Compared with conventional silicon devices at the same voltage, silicon carbide power devices can have higher doping concentration and thinner drift layer thickness, thereby achieving lower on-resistance.

[0003] There are some problems with the application of trench gate in SiC MOSFET. When the device is reverse biased, an electric field spike will appear at the bottom of the gate oxide, resulting in a decrease in the breakdown reliability of the device at the bottom of the gate oxide. In the latest technology, there are methods to reduce the electric field at the bottom of the gate oxide, such as patent CN116759454A, which uses a P well to surround one side of the gate trench to shield the electric field; such as patent CN116936620A, which uses an epitaxial P layer to surround both sides of the gate trench and sets up a current channel; such as patent CN117894802A, which designs an array P buried layer; such as patent CN116072710B, which designs a P buried layer in the epitaxial layer and a P buried layer under the gate; such as patent CN116344588A, which designs a P buried layer at the epitaxial layer; such as patent CN117174756A, which designs a multi-layer P shielding area under the gate and under the P-type base region; such as patent US 9761706B2, designs a P-type buried layer in the epitaxial layer; for example, patent US11367775B1 uses an alternating epitaxial injection method to design a very deep P-type shielding layer; for example, patent US11600701B2 uses a P-well to surround the bottom of the gate trench; and the present invention uses the same mask to perform multiple epitaxy and injection in different directions to form a multi-layer staggered electric field absorption layer, and injects P-type doping into the oblique source trench to form an oblique P-well shielding area, thereby avoiding the injection of high-energy ions. The above operations greatly reduce the peak electric field at the bottom of the gate oxide, improve the device reliability, and reduce the saturation current density while ensuring that the on-resistance remains unchanged, thereby improving the short-circuit tolerance of the device. Summary of the invention

[0004] The purpose of the present invention is to provide a method for preparing a trench gate SiC MOSFET with reduced gate oxide electric field, which is used to solve the problem of electric field spikes appearing at the bottom of the gate oxide when the trench gate structure is reverse biased, and reduces the device saturation current density and improves the device short-circuit tolerance.

[0005] The technical solution of the present invention is achieved in this way: A method for preparing a trench gate SiC MOSFET for reducing gate oxide electric field, comprising: growing an epitaxial layer on a semiconductor substrate to form a first epitaxial layer, and then performing P-type doping under the blocking of an electric field absorption layer mask to form a first electric field absorption layer; growing an epitaxial layer on the first epitaxial layer to form a second epitaxial layer, and then rotating the electric field absorption layer mask by 90 degrees, and performing P-type doping under the blocking of the electric field absorption layer mask to form a second electric field absorption layer; growing an epitaxial layer on the second epitaxial layer to form a third epitaxial layer, performing P-type doping on the third epitaxial layer to form a P-type base region, and performing P-type doping on the third epitaxial layer to form a second epitaxial layer; N-type heavy doping is performed on the epitaxial layer to form an N+ source region; trench etching is performed under the blocking of the source trench mask to form an inclined source trench, and then P-type heavy doping is performed to form an inclined P-well shielding region; trench etching is performed under the blocking of the gate trench mask to form a gate trench, and gate oxide is grown on the inner surface of the gate trench, and then part of the upper surface layer of the gate trench mask is grinded, and polysilicon is deposited after grinding; excess polysilicon is removed, and then field oxygen is grown, and then excess field oxygen is removed, and then source ohmic contact region deposition and drain ohmic contact region deposition are performed.

[0006] Optionally, the first electric field absorbing layer and the second electric field absorbing layer overlap in the longitudinal direction and do not contact each other.

[0007] Optionally, the implantation energy of the P-type base region is higher than that of the N+ source region, that is, the junction depth of the P-type base region is deeper than that of the N+ source region, and the concentration of the N+ source region is higher than that of the P-type base region.

[0008] Optionally, the junction depth of the slanted P-well shield region is deeper than the gate trench.

[0009] Optionally, the semiconductor substrate is an N-type heavily doped silicon carbide substrate.

[0010] The beneficial effects of the present invention are: The present invention makes the source electrode into an oblique groove, and then injects P-type doping to form an oblique P-well shielding area. The oblique shielding area can not only shield the electric field and reduce the peak electric field at the bottom of the gate oxide, but also guide the current to flow obliquely downward, thereby improving the utilization rate of the second epitaxial layer; the first electric field absorption layer and the second electric field absorption layer use different directions of the same mask, saving the number of masks, and the electric field absorption layer can further reduce the peak electric field at the bottom of the gate oxide layer and can also reduce the saturation current density of the device without increasing the on-resistance, thereby improving the short-circuit tolerance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 This is a schematic diagram of the structure after the first electric field absorption layer is generated in step S01 of embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure after the second electric field absorption layer is generated in step S02 of embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure after the P-type base region and the N+ source region are formed in step S03 of embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure after the oblique source trench is etched in step S04 of embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure after the gate trench is etched in step S05 of embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the structure of gate oxide and polysilicon growth in step S06 of embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the structure of field oxygen growth in step S06 of Example 1 of the present invention; Figure 8 It is a schematic diagram of the structure after the source ohmic contact region and the drain ohmic contact region are deposited in step S06 of embodiment 1 of the present invention; Fig. 9 A schematic diagram of a trench gate structure according to an embodiment of the present invention; Fig.10 It is a schematic diagram of the structure after step S01 and step S02 in embodiment 1 of the present invention are performed alternately for multiple times.

[0013] Figure Number: 1-semiconductor substrate; 2-first epitaxial layer; 3-electric field absorption layer mask; 4-first electric field absorption layer; 5-second epitaxial layer; 6-second electric field absorption layer; 7-third epitaxial layer; 8-P-type base region; 9-N+ source region; 10-source trench mask; 11-oblique source trench; 12-oblique P-well shielding region; 13-gate trench mask; 14-gate trench; 15-gate oxide; 16-polysilicon; 17-field oxide; 18-source ohmic contact region; 19-drain ohmic contact region. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0015] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0016] Embodiment 1:

[0017] This embodiment is used to provide a method for preparing a trench gate SiC MOSFET for reducing gate oxide electric field, comprising: Step S01: Figure 1 As shown, an epitaxial layer is grown on a semiconductor substrate 1, the semiconductor substrate 1 is an N-type heavily doped silicon carbide substrate, to form a first epitaxial layer 2, and then P-type doping is performed under the blocking of an electric field absorption layer mask 3 to form a first electric field absorption layer 4; Step S02: Figure 2 As shown, an epitaxial layer is grown on the first epitaxial layer 2 to form a second epitaxial layer 5, and then the electric field absorption layer mask 3 is rotated 90°, and P-type doping is performed under the blocking of the electric field absorption layer mask 3 to form a second electric field absorption layer 6, and the first electric field absorption layer 4 and the second electric field absorption layer 6 are overlapped in the longitudinal direction and do not contact each other; Step S03: Figure 3 As shown, an epitaxial layer is grown on the second epitaxial layer 5 to form a third epitaxial layer 7, P-type doping is performed on the third epitaxial layer 7 to form a P-type base region 8, and N-type heavy doping is performed on the third epitaxial layer 7 to form an N+ source region 9. The injection energy of the P-type base region 8 is higher than that of the N+ source region 9, that is, the junction depth of the P-type base region 8 is deeper than that of the N+ source region 9, and the concentration of the N+ source region 9 is higher than that of the P-type base region 8; Step S04: Figure 4-5 As shown, trench etching is performed under the blocking of the source trench mask 10 to form an inclined source trench 11, and then P-type heavy doping is performed to form an inclined P-well shielding region 12; Step S05: Figure 5As shown, trench etching is performed under the blocking of the gate trench mask 13 to form a gate trench 14, and gate oxide 15 is grown on the inner surface of the gate trench 14, and then part of the upper surface layer of the gate trench mask 13 is polished, and polysilicon 16 is deposited after polishing. Secondly, it should be noted that the junction depth of the inclined P-well shielding region 12 is deeper than that of the gate trench 14; Step S06: Figure 6-9 As shown, the excess polysilicon 16 is removed, and then the field oxide 17 is grown, and then the excess field oxide 17 is removed, and then the source ohmic contact region 18 and the drain ohmic contact region 19 are deposited.

[0018] Secondly, in this embodiment, if Fig.10 As shown, step S01 and step S02 can be repeated as needed, that is, epitaxy and electric field absorption layer injection are performed alternately to obtain a multi-layer electric field absorption layer superposition to improve the electric field at the bottom of the device gate oxide. Step S01 and step S02 only involve one mask, and only the direction of the mask is changed, which greatly saves the number of masks.

[0019] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for preparing a trench gate SiC MOSFET for reducing gate oxide electric field, characterized in that: include: Growing an epitaxial layer on a semiconductor substrate (1) to form a first epitaxial layer (2), and then performing P-type doping under the blocking of an electric field absorption layer mask (3) to form a first electric field absorption layer (4); Growing an epitaxial layer on the first epitaxial layer (2) to form a second epitaxial layer (5), then rotating the electric field absorption layer mask (3) by 90 degrees, and performing P-type doping under the blocking of the electric field absorption layer mask (3) to form a second electric field absorption layer (6); Growing an epitaxial layer on the second epitaxial layer (5) to form a third epitaxial layer (7), performing P-type doping on the third epitaxial layer (7) to form a P-type base region (8), and performing N-type heavy doping on the third epitaxial layer (7) to form an N+ source region (9); Performing trench etching under the blocking of the source trench mask (10) to form an inclined source trench (11), and then performing P-type heavy doping to form an inclined P-well shielding region (12); Performing trench etching under the blocking of the gate trench mask (13) to form a gate trench (14), growing gate oxide (15) on the inner surface of the gate trench (14), then grinding a portion of the upper surface layer of the gate trench mask (13), and depositing polysilicon (16) after grinding; Excess polysilicon (16) is removed, and then field oxygen (17) is grown, and then excess field oxygen (17) is removed, followed by deposition of a source ohmic contact region (18) and a drain ohmic contact region (19).

2. The method for preparing a trench gate SiC MOSFET for reducing gate oxide electric field according to claim 1, characterized in that: The first electric field absorbing layer (4) and the second electric field absorbing layer (6) are overlapped in the longitudinal direction and do not contact each other.

3. The method for preparing a trench gate SiC MOSFET with reduced gate oxide electric field according to claim 1, characterized in that: The injection energy of the P-type base region (8) is higher than that of the N+ source region (9), that is, the junction depth of the P-type base region (8) is deeper than that of the N+ source region (9), and the concentration of the N+ source region (9) is higher than that of the P-type base region (8).

4. The method for preparing a trench gate SiC MOSFET with reduced gate oxide electric field according to claim 1, characterized in that: The junction depth of the inclined P-well shielding region (12) is deeper than that of the gate trench (14).

5. The method for preparing a trench gate SiC MOSFET with reduced gate oxide electric field according to claim 1, characterized in that: The semiconductor substrate (1) is an N-type heavily doped silicon carbide substrate.

Images