GaN-based transistor structure for inhibiting hole accumulation and preparation method thereof
By designing a hole extraction region in a GaN-based transistor, the holes accumulated in the III-N composite buffer layer are diffused to the substrate or extracted through grounding, the problem of hole accumulation in GaN power electronics is solved, and the stability and reliability of the device are improved.
Patent Information
- Application Number
- CN202411643328.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-03-28
AI Technical Summary
When GaN power electronic devices operate in a closed state, local electric field spikes caused by high drain voltages lead to a large number of electrons and holes, which seriously affects the long-term stability and reliability of the device.
A GaN-based transistor structure is designed, including a substrate layer, an III-N composite buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top. A hole extraction area is provided in the III-N composite buffer layer. The hole extraction area can diffuse accumulated holes into the substrate or extract it out through ground to suppress hole accumulation.
It effectively suppresses the accumulation of holes in the buffer layer of GaN-based transistors, improves the long-term stability and reliability of the device, and has relatively simple process and low material cost.
Smart Images
Figure CN119730295A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power electronic device structure and manufacturing thereof, in particular to a GaN-based transistor structure capable of suppressing hole accumulation and a preparation method thereof. Background Art
[0002] Since the early 1990s, the research focus of compound semiconductor electronic devices has shifted to wide bandgap semiconductor devices. Wide bandgap materials represented by gallium nitride (GaN) are the third generation of semiconductor materials after silicon (Si) and gallium arsenide (GaAs). GaN has a larger bandgap width (3.4eV), stronger critical breakdown field strength and higher electron migration rate, and has superior properties such as high frequency, high efficiency, high power, high voltage resistance, high temperature resistance and strong radiation resistance. It is a key core material and electronic component supporting the independent innovation development and transformation and upgrading of industries such as the new generation of mobile communications, new energy vehicles, high-speed rail trains, and energy Internet. Therefore, it has received extensive attention from researchers at home and abroad. It has huge advantages and potential in power electronic power devices and high-frequency power devices, and has become the focus of global semiconductor technology and industry competition.
[0003] When GaN power electronic devices are working in the off state, the drain bias voltage is high, and the electric lines are more concentrated where the gate electrode is close to the drain electrode, resulting in a higher local electric field peak. This causes the electrons in the two-dimensional electron gas channel to obtain higher energy, intensifying the collision between internal electrons and lattice atoms, thereby generating a large number of electrons and holes. The holes are sputtered to the buffer layer below the channel layer and accumulate, seriously affecting the long-term stability and reliability of the device.
[0004] To this end, we propose a GaN-based transistor structure that inhibits hole accumulation and a preparation method thereof, which inhibits the accumulation of holes in the buffer layer of the GaN-based transistor and improves the stability and reliability of the device. Summary of the invention
[0005] In order to make up for the shortcomings of the prior art, the present invention provides the following technical solutions: a GaN-based transistor structure for inhibiting hole accumulation, comprising a substrate layer, a III-N composite buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top, a source electrode and a drain electrode are arranged at both ends of the surface of the barrier layer, a gate electrode is arranged between the source electrode and the drain electrode, the channel layer and the barrier layer are made of III-N material, the channel layer and the barrier layer form a heterojunction, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface formed by the channel layer and the barrier layer and on the side close to the channel layer, as a conductive channel of the GaN-based transistor, a hole extraction region is arranged in the III-N composite buffer layer, the hole extraction region is located near the gate electrode and on the side close to the drain electrode, the material of the substrate layer is P-type doped, and the thickness is 50-1200μm, the hole extraction region can diffuse the holes accumulated in the III-N composite buffer layer into the substrate, or extract them out through the grounded substrate, thereby inhibiting the hole accumulation in the composite buffer layer caused by the high drain voltage during off-state operation.
[0006] Preferably, both the source electrode and the drain electrode form ohmic contacts with the two-dimensional electron gas channel in the channel layer.
[0007] Preferably, a cap layer is provided between the gate electrode and the barrier layer, which has a depletion effect on the two-dimensional electron gas in the channel layer to realize the enhancement mode operation of the GaN-based transistor. The material of the cap layer is GaN or InGaN, and the doping impurity is Mg with a doping concentration of 1x10 18 -1x10 21 cm -3 .
[0008] Preferably, the III-N composite buffer layer comprises three layers, which are, from bottom to top, a nucleation layer, a transition layer and a buffer layer;
[0009] The material of the nucleation layer is AlN or GaN with a thickness of 50-300nm, the material of the transition layer is AlGaN with a thickness of 200-1000nm, the material of the buffer layer is GaN or AlGaN with a thickness of 100nm-10μm, and the nucleation layer, transition layer and buffer layer are unintentionally doped.
[0010] Preferably, the material of the hole extraction region is GaN, or AlGaN, or InGaN, which is P-type doped, and the doping impurity is Mg, and the doping concentration is 1x10 18 -1x10 21 cm -3 .
[0011] Preferably, the material of the channel layer is GaN or InGaN, with a thickness of 50-500 nm; the material of the barrier layer is AlGaN, with an Al component of 0.1-0.3, a thickness of 5-50 nm, and no intentional doping.
[0012] Preferably, the structures of the source electrode and the drain electrode are Ti / Al and other metals, or TiN / Al and other metals from bottom to top;
[0013] The gate electrode is Ni and other metals, or Ti and other metals, or TiN and other metals from bottom to top.
[0014] A method for preparing a GaN-based transistor structure for inhibiting hole accumulation comprises the following steps:
[0015] Step 1: substrate cleaning;
[0016] Step 2: epitaxially growing a III-N composite buffer layer on the substrate layer 1;
[0017] Step 3: Etching a portion of the III-N composite buffer layer;
[0018] Step 4: growing P-GaN material in the area etched in step 3;
[0019] Step 5: sequentially growing a GaN channel layer and an AlGaN barrier layer on the surface of the structure obtained in step 4;
[0020] Step 6: Prepare a source electrode and a drain electrode, and perform high temperature annealing, so that both the source electrode and the drain electrode simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer and the AlGaN barrier layer;
[0021] Step 7: On the surface of the AlGaN barrier layer, a gate electrode is prepared to obtain a GaN-based transistor structure.
[0022] Beneficial Effects
[0023] Compared with the prior art, the present invention provides a GaN-based transistor structure for suppressing hole accumulation and a preparation method thereof, which has the following beneficial effects:
[0024] 1. When GaN power electronic devices are working in the off state, the drain bias voltage is high, and the electric lines are more concentrated where the gate electrode is close to the drain electrode, resulting in a higher local electric field spike, which makes the electrons in the two-dimensional electron gas channel obtain higher energy, intensifies the collision between internal electrons and lattice atoms, and thus generates a large number of electrons and holes. The holes are sputtered to the buffer layer under the channel layer and accumulate, which seriously affects the long-term stability and reliability of the device.
[0025] 2. The hole extraction zone introduced in the present invention can diffuse the holes accumulated in the III-N composite buffer layer into the substrate, or extract them through the grounded substrate, thereby suppressing the accumulation of holes in the composite buffer layer caused by the high drain voltage during off-state operation, and improving the long-term stability and reliability of the device.
[0026] 3. The method for preparing a GaN-based transistor that suppresses hole accumulation provided by the present invention is compatible with the original process, the process preparation is relatively simple, and the cost of the materials used is low, which can significantly improve the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 This is a front view of a GaN-based transistor structure for suppressing hole accumulation and a method for preparing the same with a cap layer according to the present invention;
[0028] Figure 2 A top view of a GaN-based transistor structure for suppressing hole accumulation and a method for preparing the same according to the present invention;
[0029] Figure 3 A front view of a GaN-based transistor structure for suppressing hole accumulation and a method for preparing the same according to the present invention;
[0030] Figure 4 This is a diagram of the preparation steps of a GaN-based transistor structure for suppressing hole accumulation and a preparation method thereof according to the present invention.
[0031] In the figure: 1. substrate layer; 2. III-N composite buffer layer; 3. hole extraction region; 4. channel layer; 5. barrier layer; 6. source electrode; 7. drain electrode; 8. gate electrode; 11. cap layer; 21. nucleation layer; 22. transition layer; 23. buffer layer. DETAILED DESCRIPTION
[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0033] Embodiment 1:
[0034] See also Figure 1 , Figure 2A GaN-based transistor structure for inhibiting hole accumulation comprises a substrate layer 1, a III-N composite buffer layer 2, a channel layer 4 and a barrier layer 5 which are sequentially arranged from bottom to top, a source electrode 6 and a drain electrode 7 are arranged at both ends of the surface of the barrier layer 5, a gate electrode 8 is arranged between the source electrode 6 and the drain electrode 7, the channel layer 4 and the barrier layer 5 are made of III-N materials, the channel layer 4 and the barrier layer 5 form a heterojunction, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface formed by the channel layer 4 and the barrier layer 5 and on the side close to the channel layer 4 as a conductive channel of the GaN-based transistor, a hole extraction region 3 is arranged in the III-N composite buffer layer 2, the hole extraction region 3 is located near the gate electrode 8 and close to the drain electrode 7, the material of the substrate layer 1 is P-type doped, and the thickness is 50-1200μm.
[0035] For example, both the source electrode 6 and the drain electrode 7 form an ohmic contact with the two-dimensional electron gas channel in the channel layer 4 .
[0036] For example, a cap layer 11 is provided between the gate electrode 8 and the barrier layer 5, which has a depletion effect on the two-dimensional electron gas in the channel layer 4, thereby realizing the enhancement mode operation of the GaN-based transistor. The material of the cap layer 11 is GaN or InGaN, and the doping impurity is Mg, and the doping concentration is 1x10 18 -1x10 21 cm -3 .
[0037] Preferably, the material of the cap layer 11 is GaN, the doping impurity is Mg, and the doping concentration is 5x1019cm -3 .
[0038] For example, the III-N composite buffer layer 2 includes three layers, namely, a nucleation layer 21, a transition layer 22 and a buffer layer 23 from bottom to top; the material of the nucleation layer 21 is AlN or GaN, with a thickness of 50-300nm; the material of the transition layer 22 is AlGaN, with a thickness of 200-1000nm; the material of the buffer layer 23 is GaN or AlGaN, with a thickness of 100nm-10μm; the nucleation layer 21, the transition layer 22 and the buffer layer 23 are unintentionally doped.
[0039] Preferably, the material of the nucleation layer 21 is AlN, with a thickness of 200 nm; preferably, the material of the transition layer 22 is AlGaN, with a thickness of 800 nm; preferably, the material of the buffer layer 23 is GaN, with a thickness of 4000 nm.
[0040] For example, the material of the hole extraction region 3 is GaN, or AlGaN, or InGaN, which is P-type doped, and the doping impurity is Mg, and the doping concentration is 1x10 18 -1x10 21 cm -3 .
[0041] Preferably, the material of the hole extraction region 3 is GaN, which is P-type doped, and the doping impurity is Mg, and the doping concentration is 3x10 19 cm -3 .
[0042] For example, the material of the channel layer 4 is GaN or InGaN, and the thickness is 50-500 nm;
[0043] Preferably, the material of the channel layer 4 is GaN, and the thickness is 200 nm;
[0044] For example, the material of the barrier layer 5 is AlGaN, the Al component is 0.1-0.3, the thickness is 5-50nm, and it is not intentionally doped;
[0045] Preferably, the material of the barrier layer 5 is AlGaN, with a composition of 0.15, a thickness of 20 nm, and no intentional doping;
[0046] For example, the structures of the source electrode 6 and the drain electrode 7 are Ti / Al and other metals, or TiN / Al and other metals from bottom to top;
[0047] Preferably, the structures of the source electrode 6 and the drain electrode 7 are Ti / Al / Ni / Au from bottom to top;
[0048] For example, the gate electrode 8 is Ni and other metals, or Ti and other metals, or TiN and other metals from bottom to top;
[0049] Preferably, the gate electrode 8 is Ni / Au from bottom to top.
[0050] Embodiment 2:
[0051] This embodiment provides a method for preparing a GaN transistor for suppressing hole accumulation, comprising the following steps:
[0052] Step 1: substrate cleaning;
[0053] Step 2: growing a III-N composite buffer layer 2 on the substrate layer 1 by using a metal organic chemical vapor deposition (MOCVD) method;
[0054] Step 3: performing coating, pre-baking, exposure and development operations on the III-N composite buffer layer 2 to prepare a photoresist pattern;
[0055] Step 4: using the photoresist pattern prepared in step 3 as a mask, etching away the III-N composite buffer layer 2 without the mask;
[0056] Step 5: Surface cleaning;
[0057] Step 6: Grow P-GaN material in the area etched in step 4 by using metal organic chemical vapor deposition (MOCVD) method;
[0058] Step 7: sequentially growing a GaN channel layer 4 and an AlGaN barrier layer 5 on the surface of the structure by using a metal organic chemical vapor deposition (MOCVD) method;
[0059] Step 8: At both ends of the surface of the AlGaN barrier layer 5, a source electrode 6 and a drain electrode 7 are prepared by vacuum evaporation or magnetron sputtering, and high-temperature annealing is performed. The source electrode 6 and the drain electrode 7 simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the AlGaN barrier layer 5;
[0060] Step 9: In the middle of the surface of the AlGaN barrier layer 5 parallel to the left side of the P-GaN material, a gate electrode 8 is prepared by vacuum evaporation or magnetron sputtering process. The gate electrode 8 forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the AlGaN barrier layer 5, thereby obtaining a GaN transistor structure.
[0061] In the example, the III-N composite buffer layer 2 in step 2 is grown from bottom to top in sequence by metal organic chemical vapor deposition (MOCVD) to form a nucleation layer 21, a transition layer 22 and a buffer layer 23;
[0062] In the example, the etching in step 4 is performed using a semiconductor material etcher ICP;
[0063] For example, the high temperature annealing in step 8 is a thermal annealing treatment performed in a N2 atmosphere at 830-900°C for 20-60s.
[0064] Embodiment 3:
[0065] See also Figure 2 , Figure 3 , a GaN-based transistor structure for inhibiting hole accumulation, includes a substrate layer 1 and a III-N composite buffer layer 2 arranged in sequence from bottom to top, the central area of the III-N composite buffer layer 2 is a P-GaN material, a GaN channel layer 4 and an AlGaN barrier layer 5, a source electrode 6 and a drain electrode 7 are arranged at both ends of the surface of the AlGaN barrier layer 5, and a gate electrode 8 is arranged in the middle of the surface parallel to the left side of the P-GaN material.
[0066] The GaN channel layer 4 and the AlGaN barrier layer 5 form a heterojunction, and a two-dimensional electron gas channel is formed at the heterojunction interface formed by the GaN channel layer 4 and the AlGaN barrier layer 5 and on a side close to the GaN channel layer 4;
[0067] The source electrode 6 and the drain electrode 7 both form an ohmic contact with the two-dimensional electron gas channel, and the gate electrode 8 forms a Schottky contact with the two-dimensional electron gas channel.
[0068] The material of the substrate layer 1 is P-Si, and the thickness is 800 μm;
[0069] The III-N composite buffer layer 2 includes three layers, namely, a nucleation layer 21, a transition layer 22 and a buffer layer 23 from bottom to top. The material of the nucleation layer 21 is AlN with a thickness of 60nm, the material of the transition layer 22 is AlGaN with a thickness of 500nm, and the material of the buffer layer 23 is AlGaN with a thickness of 300nm. The nucleation layer 21, the transition layer 22 and the buffer layer 23 are unintentionally doped.
[0070] The central area of the III-N composite buffer layer 2 is P-GaN material;
[0071] The material of the GaN channel layer 4 is GaN, and the thickness is 200 nm;
[0072] The material of the AlGaN barrier layer 5 is AlGaN, and the thickness is 30 nm;
[0073] The structures of the source electrode 6 and the drain electrode 7 are Ti / Al / Ni / Au from bottom to top, and the thicknesses are 20 / 120 / 40 / 50 nm.
[0074] The gate electrode 8 is TiN / Au from bottom to top, and the thickness is 50 / 200 nm respectively.
[0075] Embodiment 4:
[0076] See also Figure 4 , a method for preparing a GaN-based transistor structure for inhibiting hole accumulation, comprising the following steps:
[0077] Step 1: Substrate cleaning: P-Si substrate layer 1 is placed at a high temperature of 1000°C and hydrogen is introduced into the reaction chamber to clean the pollutants on the surface;
[0078] Step 2: A III-N composite buffer layer 2 is grown on the P-Si substrate layer 1 by a metal organic chemical vapor deposition (MOCVD) method, and a nucleation layer 21, a transition layer 22 and a buffer layer 23 are grown in sequence from bottom to top by a metal organic chemical vapor deposition (MOCVD) method, that is, a 60 nm thick aluminum nitride nucleation layer 21 is first grown on the substrate layer 1 by a MOCVD method at a low temperature of 500° C., and then the temperature is raised to 1000° C., and a transition layer 22 is grown on the nucleation layer 21 by a MOCVD method, and a 500 nm thick AlGaN transition layer 22 is grown, and then a 300 nm thick AlGaN buffer layer 23 is grown on the transition layer 22;
[0079] Step 3: performing coating, pre-baking, exposure and development operations on the III-N composite buffer layer 2 to prepare a photoresist pattern;
[0080] Step 4: using the photoresist pattern prepared in step 3 as a mask, etching away the III-N composite buffer layer 2 without the mask, with an etching depth of 860 nm;
[0081] Step 5: Surface cleaning: the structure prepared in step 4 was ultrasonically cleaned in acetone for 10 minutes, and then ultrasonically cleaned in isopropanol for 5 minutes with the ultrasonic power set at 2KW. Finally, it was cleaned with deionized water and dried with nitrogen.
[0082] Step 6: Grow 860nm P-GaN material in the area etched in step 4 by using metal organic chemical vapor deposition (MOCVD) method;
[0083] Step 7: A GaN channel layer 4 and an AlGaN barrier layer 5 are sequentially grown on the surface of the structure by using a metal organic chemical vapor deposition (MOCVD) method. First, a GaN channel layer 4 with a thickness of 200 nm is grown by using the MOCVD method at a temperature of 1000° C., and then an AlGaN barrier layer 5 with a thickness of 30 nm is epitaxially grown on the channel layer 4.
[0084] Step 8: At both ends of the surface of the AlGaN barrier layer 5, a vacuum evaporation process is used, that is, a multilayer of metal Ti / Al / Ni / Au is grown in the area in the device by electron beam evaporation, which is 20nm thick Ti, 120nm thick Al, 40nm thick Ni, and 50nm thick Au from bottom to top. After peeling, the source electrode 6 and the drain electrode 7 are formed, and high-temperature annealing is performed in a N2 atmosphere at 840°C for 30s. The source electrode 6 and the drain electrode 7 both form ohmic contacts with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 5;
[0085] Step 9: In the middle of the surface of the AlGaN barrier layer 5 parallel to the left side of the P-GaN material, a gate electrode 8 of a combination of TiN / Au is prepared again by electron beam evaporation, wherein the thickness of TiN is 50nm and the thickness of Au is 200nm. After peeling, a gate electrode 8 is formed. The gate electrode 8 forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 5, thereby obtaining a GaN transistor structure.
[0086] Embodiment 5:
[0087] See also Figure 3A GaN-based transistor structure for inhibiting hole accumulation comprises a substrate layer 1 and a III-N composite buffer layer 2 arranged in sequence from bottom to top, wherein the central region of the III-N composite buffer layer 2 is a P-GaN material, a GaN channel layer 4 and an AlGaN barrier layer 5, a source electrode 6 and a drain electrode 7 are arranged at both ends of the surface of the AlGaN barrier layer 5, and a gate electrode 8 is arranged in the middle of the surface parallel to the left side of the P-GaN material.
[0088] The GaN channel layer 4 and the AlGaN barrier layer 5 form a heterojunction, and a two-dimensional electron gas channel is formed at the heterojunction interface formed by the GaN channel layer 4 and the AlGaN barrier layer 5 and on a side close to the GaN channel layer 4;
[0089] The source electrode 6 and the drain electrode 7 both form an ohmic contact with the two-dimensional electron gas channel, and the gate electrode 8 forms a Schottky contact with the two-dimensional electron gas channel.
[0090] The material of the substrate layer 1 is P-Si, and the thickness is 1000 μm;
[0091] The III-N composite buffer layer 2 includes three layers, namely, a nucleation layer 21, a transition layer 22 and a buffer layer 23 from bottom to top. The material of the nucleation layer 21 is AlN with a thickness of 100 nm, the material of the transition layer 22 is AlGaN with a thickness of 500 nm, and the material of the buffer layer 23 is AlGaN with a thickness of 200 nm. The nucleation layer 21, the transition layer 22 and the buffer layer 23 are unintentionally doped.
[0092] The central area of the III-N composite buffer layer 2 is P-GaN material;
[0093] The material of the GaN channel layer 4 is GaN, and the thickness is 400 nm;
[0094] The material of the AlGaN barrier layer 5 is AlGaN, and the thickness is 50 nm;
[0095] The structures of the source electrode 6 and the drain electrode 7 are Ti / Al / Ni / Au from bottom to top, and the thicknesses are 20 / 120 / 40 / 50 nm.
[0096] The gate electrode 8 is TiN / Au from bottom to top, and the thickness is 50 / 200 nm respectively.
[0097] Embodiment 6:
[0098] A method for preparing a GaN-based transistor structure for inhibiting hole accumulation comprises the following steps:
[0099] Step 1: Substrate cleaning: P-Si substrate layer 1 is placed at a high temperature of 1000°C and hydrogen is introduced into the reaction chamber to clean the pollutants on the surface;
[0100] Step 2: A III-N composite buffer layer 2 is grown on the P-Si substrate layer 1 by a metal organic chemical vapor deposition (MOCVD) method, and a nucleation layer 21, a transition layer 22 and a buffer layer 23 are grown in sequence from bottom to top by a metal organic chemical vapor deposition (MOCVD) method, that is, a 100 nm thick aluminum nitride nucleation layer 21 is first grown on the substrate layer 1 by a MOCVD method at a low temperature of 500° C., and then the temperature is raised to 1000° C., and a transition layer 22 is grown on the nucleation layer 21 by a MOCVD method, and a 500 nm thick AlGaN is grown, and then a 200 nm thick AlGaN buffer layer 23 is grown on the transition layer 22;
[0101] Step 3: performing coating, pre-baking, exposure and development operations on the III-N composite buffer layer 2 to prepare a photoresist pattern;
[0102] Step 4: using the photoresist pattern prepared in step 3 as a mask, etching away the III-N composite buffer layer 2 without the mask, with an etching depth of 800 nm;
[0103] Step 5: Surface cleaning: the structure prepared in step 4 was ultrasonically cleaned in acetone for 10 minutes, and then ultrasonically cleaned in isopropanol for 5 minutes with the ultrasonic power set at 2KW. Finally, it was cleaned with deionized water and dried with nitrogen.
[0104] Step 6: Grow 800nm of P-GaN material in the area etched in step 4 by using metal organic chemical vapor deposition (MOCVD) method;
[0105] Step 7: A GaN channel layer 4 and an AlGaN barrier layer 5 are sequentially grown on the surface of the structure by using a metal organic chemical vapor deposition (MOCVD) method. First, a GaN channel layer 4 with a thickness of 400 nm is grown by using the MOCVD method at a temperature of 1000° C., and then an AlGaN barrier layer 5 with a thickness of 50 nm is epitaxially grown on the channel layer 4.
[0106] Step 8: At both ends of the surface of the AlGaN barrier layer 5, a vacuum evaporation process is used, that is, a multilayer of metal Ti / Al / Ni / Au is grown in the area in the device by electron beam evaporation, which is 20nm thick Ti, 120nm thick Al, 40nm thick Ni, and 50nm thick Au from bottom to top. After peeling, the source electrode 6 and the drain electrode 7 are formed, and high-temperature annealing is performed in a N2 atmosphere at 860°C for 30s. The source electrode 6 and the drain electrode 7 both form ohmic contacts with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 5;
[0107] Step 9: In the middle of the surface of the AlGaN barrier layer 5 parallel to the left three sides of the P-GaN material, a gate electrode 8 of a TiN / Au combination is prepared again by electron beam evaporation, wherein the thickness of TiN is 50nm and the thickness of Au is 200nm. After peeling, a gate electrode 8 is formed. The gate electrode 8 forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 5, thereby obtaining a GaN transistor structure.
[0108] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.
[0109] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A GaN-based transistor structure for suppressing hole accumulation, characterized in that: The invention comprises a substrate layer (1), a III-N composite buffer layer (2), a channel layer (4) and a barrier layer (5) which are arranged in sequence from bottom to top; a source electrode (6) and a drain electrode (7) are arranged at both ends of the surface of the barrier layer (5); a gate electrode (8) is arranged between the source electrode (6) and the drain electrode (7); the channel layer (4) and the barrier layer (5) are made of III-N material; the channel layer (4) and the barrier layer (5) form a heterojunction; a two-dimensional electron gas (2 DEG) is used as a conductive channel of a GaN-based transistor. A hole extraction region (3) is arranged in a III-N composite buffer layer (2). The hole extraction region (3) is located near a gate electrode (8) and close to a drain electrode (7). The material of the substrate layer (1) is P-type doped and has a thickness of 50-1200 μm. The hole extraction region (3) can diffuse holes accumulated in the III-N composite buffer layer (2) into the substrate or extract them through a grounded substrate, thereby suppressing hole accumulation in the composite buffer layer caused by a high drain voltage during off-state operation.
2. A GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: The source electrode (6) and the drain electrode (7) both form ohmic contact with the two-dimensional electron gas channel in the channel layer (4).
3. A GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: A cap layer (11) is provided between the gate electrode (8) and the barrier layer (5); the material of the cap layer (11) is GaN or InGaN, and the doping impurity is Mg, and the doping concentration is 1×10 18 -1x10 21 cm -3 .
4. A GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: The III-N composite buffer layer (2) comprises three layers, which are, from bottom to top, a nucleation layer (21), a transition layer (22) and a buffer layer (23); The material of the nucleation layer (21) is AlN or GaN, with a thickness of 50-300 nm, the material of the transition layer (22) is AlGaN, with a thickness of 200-1000 nm, and the material of the buffer layer (23) is GaN or AlGaN, with a thickness of 100 nm-10 μm. The nucleation layer (21), the transition layer (22) and the buffer layer (23) are not intentionally doped.
5. A GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: The material of the hole extraction region (3) is GaN, or AlGaN, or InGaN, which is P-type doped, and the doping impurity is Mg, and the doping concentration is 1x10 18 -1x10 21 cm -3 .
6. A GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: The material of the channel layer (4) is GaN or InGaN, and the thickness is 50-500nm; The barrier layer (5) is made of AlGaN, with an Al component of 0.1-0.3 and a thickness of 5-50 nm, and is not intentionally doped.
7. A GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: The structures of the source electrode (6) and the drain electrode (7) are Ti / Al and other metals, or TiN / Al and other metals from bottom to top; The gate electrode (8) is composed of Ni and other metals, or Ti and other metals, or TiN and other metals from bottom to top.
8. A method for preparing a GaN-based transistor structure for suppressing hole accumulation according to claim 1, characterized in that: The following steps are involved: Step 1: substrate cleaning; Step 2: epitaxially growing a III-N composite buffer layer (2) on the substrate layer 1; Step 3: etching a portion of the III-N composite buffer layer (2); Step 4: growing P-GaN material in the area etched in step 3; Step 5: sequentially growing a GaN channel layer (4) and an AlGaN barrier layer (5) on the surface of the structure obtained in step 4; Step 6: preparing a source electrode (6) and a drain electrode (7), and performing high temperature annealing, so that the source electrode (6) and the drain electrode (7) simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer (4) and the AlGaN barrier layer (5); Step 7: On the surface of the AlGaN barrier layer (5), a gate electrode (8) is prepared to obtain a GaN-based transistor structure.