MOSFET device, preparation method thereof and pixel circuit

Abstract

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, a preparation method thereof and a pixel circuit. The MOSFET device comprises a substrate; forming a well region with a first doping type on the substrate; the well region comprises an active region and trench structures arranged on two opposite sides of the active region; the gate structure is arranged above the active region; the active region comprises a lightly doped drain region and a lightly doped source region which are arranged on two opposite sides of the gate structure and have the second doping type; the lightly doped drain region is provided with a heavily doped drain region with a second doping type; the lightly doped source region is provided with a heavily doped source region with a second doping type; the first side of the heavily doped region is flush with the trench structure, and a gap is formed between the second side of the heavily doped region and the gate structure; a depletion injection region with a first doping type is arranged in the gap; the first side of the depletion injection region is flush with the second side of the heavily doped region; a gap is also formed between the second side of the depletion injection region and the gate structure. According to the technical scheme provided by the invention, the leakage current of the MOSFET device can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of metal-oxide semiconductor field effect transistors, and in particular to a MOSFET device and a preparation method thereof, and a pixel circuit. Background Art

[0002] The pixel circuit design of Mini-LED or Micro-OLED display panels used in the micro-display field requires the use of ultra-low leakage medium-voltage MOS devices, because excessive leakage current of medium-voltage MOS devices can easily lead to abnormal bright and dark spots in the Micro-OLED display panel.

[0003] Therefore, developing medium-voltage MOS devices with ultra-low leakage performance has become a core issue, and reducing the leakage performance of medium-voltage MOS devices involves the optimization design of their drain electric field distribution. The peak drain electric field of conventional medium-voltage MOS devices is often located in the area where the gate and drain overlap (gate / drain overlap) and close to the channel surface. The peak electric field located here is not conducive to reducing the leakage current of medium-voltage devices. Therefore, it is necessary to design a new source-drain structure to improve the electric field distribution in the gate / drain overlap area as much as possible, so that the electric field gathered here is dispersed to the substrate, reducing the peak electric field here. Summary of the invention

[0004] The embodiment of the present invention provides a MOSFET device and a manufacturing method thereof, and a pixel circuit to reduce the leakage current of the MOSFET device.

[0005] In a first aspect, an embodiment of the present invention provides a MOSFET device, including: a substrate;

[0006] The substrate forms a well region with a first doping type; the well region includes an active region and trench structures arranged on opposite sides of the active region; a gate structure is arranged above the active region;

[0007] The active region comprises a lightly doped drain region and a lightly doped source region having a second doping type, which are arranged on opposite sides of the gate structure; the lightly doped drain region is provided with a heavily doped drain region having a second doping type; the lightly doped source region is provided with a heavily doped source region having a second doping type;

[0008] The first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; a drain depletion injection region with a first doping type is provided in the first gap; the first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure;

[0009] The first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure; a source depletion injection region with a first doping type is provided in the third gap; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; and a fourth gap is formed between the second side of the source depletion injection region and the gate structure.

[0010] In a second aspect, an embodiment of the present invention provides a method for preparing a MOSFET device, which is used to form the MOSFET device provided by any embodiment of the present invention, comprising:

[0011] providing a substrate;

[0012] Ion implantation is performed on the substrate to form a well region having a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region;

[0013] Performing ion implantation on the active region to form a lightly doped drain region and a lightly doped source region having a second doping type;

[0014] A gate structure is formed above the active region; the lightly doped drain region and the lightly doped source region are respectively disposed on opposite sides of the gate structure;

[0015] A heavily doped drain region is formed in the lightly doped drain region by ion implantation; a heavily doped source region is formed in the lightly doped source region by ion implantation; a first side of the heavily doped drain region is flush with the trench structure, and a first gap is formed between the second side of the heavily doped drain region and the gate structure; a first side of the heavily doped source region is flush with the trench structure, and a third gap is formed between the second side of the heavily doped source region and the gate structure;

[0016] A drain depletion injection region with a first doping type is formed in the first gap by ion implantation; a first side of the drain depletion injection region is flush with a second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; a source depletion injection region with a first doping type is formed in the third gap by ion implantation; a first side of the source depletion injection region is flush with a second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure.

[0017] In a third aspect, an embodiment of the present invention further provides a pixel circuit, comprising: a MOSFET device provided by any embodiment of the present invention.

[0018] In the present invention, the MOSFET device includes a substrate and a gate structure above the substrate in sequence, wherein the substrate includes a well region having a first doping type, the well region includes an active region and a trench structure arranged on opposite sides of the active region, and the gate structure is arranged above the active region. The active region includes a lightly doped drain region and a lightly doped source region of a second doping type on opposite sides of the gate structure. The lightly doped drain region is provided with a heavily doped drain region having a second doping type, and the lightly doped source region is provided with a heavily doped source region having a second doping type. It should be noted that the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; a drain depletion injection region having a first doping type is provided in the first gap; the first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; the first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure; a source depletion injection region having the first doping type is provided in the third gap; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure. In this embodiment, a gap is formed between the heavily doped region and the gate structure, and a depletion injection region is formed in the gap, that is, a drain depletion injection region and a source depletion injection region. The drain depletion injection region can completely deplete the lightly doped drain region surrounding it and close to the channel, and no free electrons exist. The source depletion injection region between the heavily doped source region and the gate structure can completely deplete the lightly doped source region surrounding it and close to the channel, and no free electrons exist. Then, the electric field distribution in the overlapping area between the gate structure and the lightly doped drain region is more uniform, and the peak electric field of the medium voltage device is moved as far as possible toward the substrate direction, thereby improving the leakage current performance of the MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a MOSFET device provided by an embodiment of the present invention;

[0020] Figure 2 A schematic structural diagram of a comparative example of a MOSFET device provided in an embodiment of the present invention;

[0021] Figure 3 for Figure 2 Schematic diagram of electric field distribution of a comparative example of a MOSFET device;

[0022] Figure 4 A schematic diagram of the structure of another MOSFET device provided by an embodiment of the present invention;

[0023] Figure 5 A schematic flow chart of a method for preparing a MOSFET device provided in an embodiment of the present invention;

[0024] Figure 6 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0026] Figure 1 A schematic diagram of the structure of a MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, an embodiment of the present invention provides a MOSFET device, including: a substrate 11;

[0027] The substrate 11 forms a well region 12 having a first doping type; the well region 12 includes an active region 121 and trench structures 17 disposed on opposite sides of the active region 121; a gate structure 13 is disposed above the active region 121;

[0028] The active region 121 includes a lightly doped drain region 122 and a lightly doped source region 123 having the second doping type, which are arranged on opposite sides of the gate structure 13; the lightly doped drain region 122 is provided with a heavily doped drain region 124 having the second doping type; the lightly doped source region 123 is provided with a heavily doped source region 125 having the second doping type;

[0029] The first side of the heavily doped drain region 124 is flush with the trench structure 17, and a first gap is formed between the second side of the heavily doped drain region 124 and the gate structure 13; a drain depletion injection region 126 having a first doping type is disposed in the first gap; the first side of the drain depletion injection region 126 is flush with the second side of the heavily doped drain region 124; and a second gap is formed between the second side of the drain depletion injection region 126 and the gate structure 13;

[0030] The first side of the heavily doped source region 125 is flush with the trench structure 17, and the second side of the heavily doped source region 125 forms a third gap with the gate structure 13; a source depletion injection region 127 with a first doping type is arranged in the third gap; the first side of the source depletion injection region 127 is flush with the second side of the heavily doped source region 125; and a fourth gap is formed between the second side of the source depletion injection region 127 and the gate structure 13.

[0031] In the present invention, the MOSFET device includes a substrate and a gate structure above the substrate in sequence, wherein the substrate includes a well region having a first doping type, the well region includes an active region and a trench structure arranged on opposite sides of the active region, and the gate structure is arranged above the active region. The active region includes a lightly doped drain region and a lightly doped source region of a second doping type on opposite sides of the gate structure. The lightly doped drain region is provided with a heavily doped drain region having a second doping type, and the lightly doped source region is provided with a heavily doped source region having a second doping type. It should be noted that the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; a drain depletion injection region having a first doping type is provided in the first gap; the first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; the first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure; a source depletion injection region having the first doping type is provided in the third gap; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure. In this embodiment, a gap is formed between the heavily doped region and the gate structure, and a depletion injection region is formed in the gap, that is, a drain depletion injection region and a source depletion injection region. The drain depletion injection region can completely deplete the lightly doped drain region surrounding it and close to the channel, and no free electrons exist. The source depletion injection region between the heavily doped source region and the gate structure can completely deplete the lightly doped source region surrounding it and close to the channel, and no free electrons exist. Then, the electric field distribution in the overlapping area between the gate structure and the lightly doped drain region is more uniform, and the peak electric field of the medium voltage device is moved as far as possible toward the substrate direction, thereby improving the leakage current performance of the MOSFET device.

[0032] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] like Figure 1As shown, the MOSFET device includes a substrate 11, and the substrate 11 is a silicon substrate. In other embodiments, it can also be a substrate of other suitable materials. A well region 12 can be formed on the substrate 11. Specifically, a well region 12 with a first doping type can be formed on the substrate 11 by ion implantation. The first doping type can be P-type or N-type. After that, a groove structure 17 can be formed on the well region 12 by trenching or etching, and the well region 12 can include an active region 121 with a first doping type and a groove structure 17 on opposite sides of the active region 121. When multiple MOSFET devices are provided on the same substrate 11, the groove structure 17 is used to isolate the active regions 121 of different MOSFET devices. A gate structure 13 is formed on the active region 121, that is, the gate structure 13 is arranged above the active region 121 away from the substrate 11. Optionally, the gate structure 13 may include a gate dielectric layer 131 and a gate layer 132 that are sequentially arranged away from the substrate 11. It should be noted that in this embodiment, “the gate structure 13 is located above the active area 121” means that a layer of gate structure 13 is set close to the surface of the active area 121. In addition, “above” in other positions in this embodiment also specifically refers to setting a new film layer on the surface of the current film layer, rather than at the top or bottom of the current film layer.

[0034] A lightly doped drain region 122 and a lightly doped source region 123 of a second doping type are formed in the active region 121, and in a plane parallel to the substrate 11, the lightly doped drain region 122 and the lightly doped source region 123 are respectively arranged on opposite sides of the gate structure 13. When forming the lightly doped drain region 122, the process of forming the lightly doped drain region 122 and the lightly doped source region 123 can adopt a process such as spin coating, and a photoresist is formed above the active region 121 away from the substrate 11, and then the photoresist is exposed by a photomask. After exposure, the photoresist is developed by a corresponding developer to remove the photoresist located on the lightly doped drain region 122 and the lightly doped source region 123, so as to expose the lightly doped drain region 122 and the lightly doped source region 123, and then ion implantation is adopted to dope the lightly doped drain region 122 and the lightly doped source region 123 to form a P-type lightly doped drain region or an N-type lightly doped drain region, and other regions will not be doped due to the shielding of the photoresist.

[0035] It should be noted that if the well region 12 is a P-type well region, the doping type of the lightly doped drain region 122 and the lightly doped source region 123 is N-type; if the well region 12 is an N-type well region, the doping type of the lightly doped drain region 122 and the lightly doped source region 123 is P-type. On this basis, the lightly doped drain region 122 is provided with a heavily doped drain region 124 having a second doping type, and the lightly doped source region 123 is provided with a heavily doped source region 125 having a second doping type, and the doping concentration of the heavily doped drain region 124 is greater than that of the lightly doped drain region 122, and the doping concentration of the heavily doped source region 125 is greater than that of the lightly doped source region 123. After the gate voltage is applied to the gate structure 13, a lateral channel parallel to the substrate 11 is formed between the heavily doped drain region 124 and the heavily doped source region 125, thereby realizing the conduction of the MOSFET device.

[0036] Among them, the lightly doped drain region 122 is also provided with a drain depletion injection region 126 having a first doping type; the drain depletion injection region 126 is provided between the heavily doped drain region 124 and the gate structure 13; the lightly doped source region 123 is also provided with a source depletion injection region 127 having a first doping type; the source depletion injection region 127 is provided between the heavily doped source region 125 and the gate structure 13. It should be noted that there is a gap between the heavily doped drain region 124 and the gate structure 13, and in this embodiment, the gap can be called the first gap, and the first gap is also provided with the drain depletion injection region 126. Similarly, the third gap between the heavily doped source region 125 and the gate structure 13 is also provided with a source depletion injection region 127, and both the drain depletion injection region 126 and the source depletion injection region 127 are of the first doping type. It should be noted that after the drain depletion injection region 126 and the source depletion injection region 127 are formed, a second gap still exists between the drain depletion injection region 126 and the gate structure 13, and a fourth gap still exists between the source depletion injection region 127 and the gate structure 13. When the MOSFET device is in the off state, the carriers existing in the lateral channel between the heavily doped drain region 124 and the heavily doped source region 125 can be consumed by the drain depletion injection region 126 and the source depletion injection region 127 whose doping types are opposite to those of the heavily doped drain region 124 and the heavily doped source region 125. The depletion injection region can completely deplete the lightly doped drain region surrounding it and close to the channel, so that the free carriers in the lightly doped drain region 122 and the lightly doped source region 123 are completely depleted, so that the electric field distribution in the overlapping area between the gate structure and the lightly doped drain region is more uniform, and the peak electric field of the medium voltage device is moved as far as possible toward the substrate direction, thereby improving the leakage current performance of the MOSFET device.

[0037] Continue to refer Figure 1Optionally, the MOSFET device may further include: a sidewall 18; the sidewall 18 is disposed in the second gap and the fourth gap on opposite sides of the gate structure 13; the first side of the sidewall 18 of the second gap is flush with the second side of the drain depletion injection region 126; the first side of the sidewall 18 of the fourth gap is flush with the second side of the source depletion injection region 127; in a plane parallel to the substrate 11, there is no overlapping area between the sidewall 18 and the drain depletion injection region 126 and the source depletion injection region 127. In a plane parallel to the substrate 11, there is an overlapping area between the lightly doped drain region 122 and the gate structure 13; there is an overlapping area between the lightly doped source region 123 and the gate structure 13, so as to facilitate the realization of a conducting channel between the lightly doped drain region 122 and the lightly doped source region 123 under the control of the gate structure 13. In this embodiment, the sidewall 18 may be disposed around the gate structure 13. Optionally, the sidewall 18 may be prepared by a dry etching process, which may be made of silicon dioxide material, and may also play a good isolation role. The provision of the sidewall 18 in this embodiment is beneficial to further reduce the leakage current and parasitic capacitance for a small-sized MOSFET device. In addition, when forming the drain depletion injection region 126 and the source depletion injection region 127 by a doping process, the sidewall 18 and the gate structure 13 can be used as masks for preparation, so there is no overlapping area between the sidewall 18 and the drain depletion injection region 126 and the source depletion injection region 127.

[0038] Figure 2 A schematic structural diagram of a comparative example of a MOSFET device provided in an embodiment of the present invention. Figure 3 for Figure 2 Schematic diagram of electric field distribution of comparative example of MOSFET device in . The MOSFET device includes a substrate 11', a well region 12' formed on the substrate 11', and a gate structure 13'. The well region 12' includes an active region 121' and a trench structure 17' on opposite sides of the active region 121'. The active region 121' on opposite sides of the gate structure 13' is provided with a lightly doped drain region 122' and a lightly doped source region 123' having a second doping type. A heavily doped drain region 124' and a heavily doped source region 125' are provided on opposite sides of the gate structure 13'. However, a drain depletion injection region and a source depletion injection region are not provided, and the heavily doped drain region 124' and the heavily doped source region 125' are both extended to be flush with the side wall 18', that is, no gap is provided between the heavily doped drain region 124' and the side wall 18', and no gap is provided between the heavily doped source region 125' and the side wall 18'. However, as Figure 3 As shown, Figure 2 The peak electric field of ultra-low leakage medium voltage devices is often located in the overlap region between the gate and the drain and close to the channel surface. Figure 3The horizontal axis is the horizontal position, the vertical axis is the vertical position, and in the electric field distribution diagram, lighter grayscale colors represent larger energy values, and darker grayscale colors represent smaller energy values. Figure 3 The peak of the medium electric field is located in the overlap region A1 between the gate and the drain. The peak electric field located here is not conducive to reducing the two main leakage currents that constitute the leakage current of the medium voltage device: the junction leakage of the drain to the lightly doped drain region 122' and the gate-induced leakage current (GIDL leakage). Because it is necessary to improve the electric field distribution in the overlap region between the gate and the drain (gate / drain overlap) as much as possible, Figure 1 In the MOSFET device provided by the present embodiment shown in the figure, a gap is set between the heavily doped drain region 124 and the side wall 18 to layout the drain depletion injection region 126, and a gap is set between the heavily doped source region 125 and the side wall 18 to layout the source depletion injection region 127. The drain depletion injection region 126 and the source depletion injection region 127 can disperse the electric field concentrated on the surface to the substrate as much as possible, so that the peak electric field located there is reduced.

[0039] Continue to refer Figure 1 Optionally, the MOSFET device may further include: a drain metal silicide 15, a gate metal silicide 14 and a source metal silicide 16; the gate metal silicide 14 is disposed above the gate structure 13; the drain metal silicide 15 is disposed above the heavily doped drain region 124 and a portion of the drain depletion injection region 126; the source metal silicide 16 is disposed above the heavily doped source region 125 and a portion of the source depletion injection region 127. There is a gap between the drain metal silicide 15 and the sidewall 18; there is a gap between the source metal silicide 16 and the sidewall 18. The drain metal silicide 15, the gate metal silicide 14 and the source metal silicide 16 may be metal layers, which are used to electrically connect to the light-emitting element or other MOSFET devices on the display panel to realize the signal transmission function of the MOSFET device. Because there is a gap between the drain metal silicide 15 and the side wall 18, and a gap between the source metal silicide 16 and the side wall 18, the above gap increases the drain expansion resistance of the MOSFET device, which can improve the electric field distribution gradient in the overlapping area between the gate and the drain, especially near the contact surface between the active area 121 and the gate structure 13, and reduce the maximum electric field there, thereby achieving the purpose of reducing leakage current.

[0040] As can be seen from the above, the first doping type can be P-type or N-type. When the first doping type can be P-type, the MOSFET device is an N-type device, and when the first doping type can be N-type, the MOSFET device is a P-type device. This embodiment is first described by taking an N-type device as an example. Optionally, the first doping type can be P-type; the second doping type can be N-type.

[0041] Optionally, the well region 12 may be formed by first ion implantation; the implantation energy of the first ion may range from 100 KeV to 400 KeV; and the implantation dose of the first ion may range from 2E13 atom / cm 2 ~6E13atom / cm 2 The first ion is a P-type doping ion such as boron; the lightly doped drain region 122 and the lightly doped source region 123 are both formed by second ion implantation; the implantation energy of the second ion is in the range of 50Kev to 300Kev; the implantation dose of the second ion is in the range of 1E12atom / cm 2 ~8E12atom / cm 2 The second ion is an N-type doping ion such as phosphorus; the heavily doped drain region 124 and the heavily doped source region 125 are both formed by implanting the third ion; the implantation energy of the third ion is in the range of 10 KeV to 50 KeV; the implantation dose of the third ion is in the range of 2E14 atom / cm 2 ~2E15atom / cm 2 ; The third ion is an N-type doping ion such as phosphorus.

[0042] When the parts of the active area are doped by the ion implantation process, the well area 12 is P-type doped, and P-type doping ions such as boron can be used for ion implantation, and the boron ions themselves have a strong diffusion effect. The lightly doped drain area 122 and the lightly doped source area 123 are N-type doped, and N-type doping ions such as phosphorus can be used for ion implantation. The heavily doped drain area 124 and the heavily doped source area 125 are N-type doped, and N-type doping ions such as phosphorus are used for ion implantation. Compared with the injection energy range of the lightly doped drain area 122 of 50Kev to 300Kev, the injection energy range of the heavily doped drain area 124 is 10Kev to 50Kev. The injection energy of the heavily doped drain area 124 is smaller, but the injection dose is larger, so the heavily doped drain area 124 forms a film layer with a larger concentration but a lower film thickness, that is, the heavily doped drain area 124 forms a heavier doping effect than the lightly doped drain area 122. Similarly, the heavily doped source region 125 forms a heavier doping effect than the lightly doped source region 123 , thereby forming a conductive connection between the heavily doped drain region 124 and the heavily doped source region 125 .

[0043] Optionally, the drain depletion injection region 126 and the source depletion injection region 127 can be formed by fourth ion implantation; the implantation energy of the fourth ion is in the range of 5 KeV to 10 KeV; the implantation dose of the fourth ion is in the range of 1E13 atom / cm 2 ~1E14atom / cm 2 ; The fourth ion is a P-type doping ion such as boron difluoride.

[0044] In this embodiment, the drain depletion injection region 126 and the source depletion injection region 127 can be ion doped with boron fluoride ions with weak diffusion effect, so as to form a medium-voltage N-type well region with stable performance, thereby improving the reliability of the semiconductor structure finally formed. Moreover, the dose of the drain depletion injection region 126 and the source depletion injection region 127 is relatively large, but the injection energy is relatively low. After the well region 12, the lightly doped drain region 122 and the lightly doped source region 123 are formed in sequence, a P type IMP with very low energy but relatively large dose is made, that is, the drain depletion injection region 126 and the source depletion injection region 127 are formed. This P type IMP makes the lightly doped drain region 122 and the lightly doped source region 123 surrounding it and close to the channel completely depleted. There are no free electrons in the completely depleted regions of the lightly doped drain region 122 and the lightly doped source region 123, so that the electric field distribution in the gate / drain overlap region is more uniform, and under the condition of controlling the width of the depletion region, the peak electric field is moved as far as possible toward the substrate. This is beneficial to improving the leakage performance and also beneficial to improving the hot carrier effect performance of the MOSFET device.

[0045] In this embodiment, the MOSFET device may also be a P-type device, and optionally, the first doping type may be N-type; the second doping type may be P-type. In this case, the doping conditions of various parts in the active region of the P-type device are different from the doping conditions of various parts in the active region of the N-type device.

[0046] Optionally, the well region 12 may be formed by implanting the fifth ion; the implantation energy of the fifth ion is in the range of 200 KeV to 800 KeV; and the implantation dose of the fifth ion is in the range of 2E13 atom / cm 2 ~6E13atom / cm 2 The fifth ion is an N-type doping ion such as phosphorus; the lightly doped drain region 122 and the lightly doped source region 123 are both formed by implanting the sixth ion; the implantation energy of the sixth ion is in the range of 40 KeV to 200 KeV; the implantation dose of the sixth ion is in the range of 1E12 atom / cm 2 ~8E12atom / cm 2 The sixth ion is a P-type doping ion such as boron; the heavily doped drain region 124 and the heavily doped source region 125 are both formed by implanting the seventh ion; the implantation energy of the seventh ion is in the range of 5Kev to 30Kev; the implantation dose of the seventh ion is in the range of 2E14atom / cm 2 ~2E15atom / cm 2 ; The seventh ion is a P-type doping ion such as boron.

[0047] When the parts of the active area 121 are doped by the ion implantation process, the well area 12 is N-type doped, and N-type doping ions such as phosphorus can be used for ion implantation, the lightly doped drain area 122 and the lightly doped source area 123 are P-type doped, and both can be ion implanted with P-type doping ions such as boron, and the heavily doped drain area 124 and the heavily doped source area 125 are also P-type doped, and boron is also used for ion implantation. Compared with the injection energy range of the lightly doped drain area 122 of 40Kev to 200Kev, the injection energy range of the heavily doped drain area 124 is 5Kev to 30Kev. The injection energy of the heavily doped drain area 124 is smaller, but the injection dose is larger, so the heavily doped drain area 124 forms a film layer with a larger concentration but a lower film thickness, that is, the heavily doped drain area 124 forms a heavier doping effect than the lightly doped drain area 122. Similarly, the heavily doped source region 125 forms a heavier doping effect than the lightly doped source region 123 , thereby forming a conductive connection between the heavily doped drain region 124 and the heavily doped source region 125 .

[0048] Optionally, the drain depletion injection region 126 and the source depletion injection region 127 can be formed by eighth ion implantation; the eighth ion implantation energy range is 5Kev to 20Kev; the eighth ion implantation dose range is 1E13atom / cm 2 ~1E14atom / cm 2 ; The eighth ion is an N-type doping ion such as arsenic.

[0049] In this embodiment, the drain depletion injection region 126 and the source depletion injection region 127 are ion doped with arsenic ions. The injection dose of the drain depletion injection region 126 and the source depletion injection region 127 is relatively large, but the injection energy is relatively low. After the well region 12, the lightly doped drain region 122 and the lightly doped source region 123 are formed in sequence, an N-type IMP with very low energy but relatively large dose is made, that is, the drain depletion injection region 126 and the source depletion injection region 127 are formed. This N-type IMP makes the lightly doped drain region 122 and the lightly doped source region 123 surrounding it and close to the channel completely depleted. There are no free holes in the completely depleted regions of the lightly doped drain region 122 and the lightly doped source region 123, making the electric field distribution in the gate / drain overlap region more uniform, and under the condition of controlling the width of the depletion region, the peak electric field is moved as far as possible toward the substrate. This is beneficial to improving the leakage performance and also beneficial to improving the hot carrier effect performance of the MOSFET device.

[0050] Figure 4A schematic structural diagram of another MOSFET device provided in an embodiment of the present invention. Optionally, the number of MOSFET devices may be multiple; a trench structure 17 is provided between the active regions 121 of two adjacent MOSFET devices; and the trench structure 17 is filled with an isolation material. Figure 4 Taking two MOSFET devices as an example, a groove structure 17 is provided between the active areas 121 of two adjacent MOSFET devices, and the groove structure 17 isolates the different active areas 121. To avoid the mutual influence of free carriers in the active areas 121 of adjacent MOSFET devices, especially when N-type MOSFET devices and P-type MOSFET devices are provided on the same silicon-based substrate, the provision of the groove structure 17 in this embodiment can effectively achieve the isolation of the N-type MOSFET device and the P-type MOSFET device, thereby improving the reliability of the MOSFET device. The groove structure 17 is filled with an isolation material, and the isolation material can be a material such as silicon oxide that can achieve electrical isolation.

[0051] Based on the same concept, an embodiment of the present invention further provides a method for preparing a MOSFET device. Figure 5 A schematic diagram of a process for preparing a MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the method of this embodiment includes the following steps:

[0052] Step S110: providing a substrate.

[0053] Step S120 , performing ion implantation on the substrate to form a well region having a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region.

[0054] Step S130 , performing ion implantation on the active region to form a lightly doped drain region and a lightly doped source region having a second doping type.

[0055] Step S140, forming a gate structure above the active region; a lightly doped drain region and a lightly doped source region are respectively disposed on two opposite sides of the gate structure.

[0056] Step S150, forming a heavily doped drain region in the lightly doped drain region by ion implantation; forming a heavily doped source region in the lightly doped source region by ion implantation; the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; the first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure.

[0057] Step S160, forming a drain depletion injection region with a first doping type in the first gap by ion implantation; the first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; forming a source depletion injection region with a first doping type in the third gap by ion implantation; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure.

[0058] After forming the lightly doped drain region and the lightly doped source region, sidewalls can be formed on opposite sides of the gate structure; then, using the gate structure and the sidewalls as masks, a drain depletion injection region is formed in the lightly doped drain region by ion implantation, and a source depletion injection region is formed in the lightly doped source region by ion implantation. The doping process does not need to coat photoresist for exposure, thereby saving a coating process, saving process time, improving process efficiency, and reducing process costs.

[0059] It should be noted that after forming the lightly doped drain region and the lightly doped source region in step S140, step S150 may be first performed to form the heavily doped drain region and the heavily doped source region, and then step S160 may be performed to form the drain depletion injection region and the source depletion injection region; or, step S160 may be first performed to form the drain depletion injection region and the source depletion injection region, and then step S150 may be performed to form the heavily doped drain region and the heavily doped source region. This embodiment does not specifically limit the execution order of step S150 and step S160.

[0060] In the present invention, the MOSFET device includes a substrate and a gate structure above the substrate in sequence, wherein the substrate includes a well region having a first doping type, the well region includes an active region and a trench structure arranged on opposite sides of the active region, and the gate structure is arranged above the active region. The active region includes a lightly doped drain region and a lightly doped source region of a second doping type on opposite sides of the gate structure. The lightly doped drain region is provided with a heavily doped drain region having a second doping type, and the lightly doped source region is provided with a heavily doped source region having a second doping type. It should be noted that the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; a drain depletion injection region having a first doping type is provided in the first gap; the first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; the first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure; a source depletion injection region having the first doping type is provided in the third gap; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure. In this embodiment, a gap is formed between the heavily doped region and the gate structure, and a depletion injection region is formed in the gap, that is, a drain depletion injection region and a source depletion injection region. The drain depletion injection region can completely deplete the lightly doped drain region surrounding it and close to the channel, and no free electrons exist. The source depletion injection region between the heavily doped source region and the gate structure can completely deplete the lightly doped source region surrounding it and close to the channel, and no free electrons exist. Then, the electric field distribution in the overlapping area between the gate structure and the lightly doped drain region is more uniform, and the peak electric field of the medium voltage device is moved as far as possible toward the substrate direction, thereby improving the leakage current performance of the MOSFET device.

[0061] On the basis of the above embodiment, optionally, after forming the gate structure above the active area, the method may further include: forming sidewalls in the second gap and the fourth gap on opposite sides of the gate structure; the first side of the sidewall of the second gap is flush with the second side of the drain depletion injection region; the first side of the sidewall of the fourth gap is flush with the second side of the source depletion injection region; in a plane parallel to the substrate, the sidewall overlaps with the lightly doped drain region and the lightly doped source region; forming a drain depletion injection region with a first doping type in the first gap by ion implantation; forming a source depletion injection region with a first doping type in the third gap by ion implantation, including: using the gate structure and the sidewall as a mask, forming a drain depletion injection region with a first doping type in the lightly doped drain region by ion implantation, and forming a source depletion injection region with a first doping type in the lightly doped source region by ion implantation. In this embodiment, when preparing the drain depletion injection region and the source depletion injection region, the gate structure and the sidewall are also used as a mask to dope the lightly doped drain region and the lightly doped source region. There is no need to apply photoresist for exposure and etching process, thereby saving a coating process, saving process time, and improving process efficiency. In summary, this embodiment saves a process when preparing the lightly doped drain region and the lightly doped source region, and saves another process when preparing the drain depletion injection region and the source depletion injection region, thereby improving the preparation efficiency of MOSFET devices.

[0062] An embodiment of the present invention further provides a pixel circuit. Figure 6 A schematic diagram of a pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the pixel circuit 100 provided in the embodiment of the present invention includes the MOSFET device 200 provided in any embodiment of the present invention. The pixel circuit 100 can be used to drive a light-emitting device 300 such as an LED chip, Mini-LED or Micro-OLED to display a picture. Optionally, the light-emitting device driven by the MOSFET device 22 in this embodiment can be a micro device such as Micro-OLED or Micro-OLED with a smaller size, faster response speed, higher luminous efficiency, stronger stability and longer service life, so as to improve the abnormal bright and dark spot phenomenon of Mini-LED or Micro-OLED micro-display devices.

[0063] The pixel circuit provided by the embodiment of the present invention includes the technical features of the MOSFET device provided by any embodiment of the present invention, and has the beneficial effects of the corresponding technical features, which will not be repeated here.

[0064] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A MOSFET device, characterized in that: include: substrate; The substrate forms a well region having a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region; A gate structure, disposed above the active area; The active region comprises a lightly doped drain region and a lightly doped source region having a second doping type, which are arranged on opposite sides of the gate structure; the lightly doped drain region is provided with a heavily doped drain region having a second doping type; the lightly doped source region is provided with a heavily doped source region having a second doping type; The first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; a drain depletion injection region with a first doping type is provided in the first gap; The first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; The first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure; a source depletion injection region with a first doping type is provided in the third gap; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; and a fourth gap is formed between the second side of the source depletion injection region and the gate structure.

2. The MOSFET device according to claim 1, characterized in that Also includes: Side walls; The sidewalls are arranged at the second gap and the fourth gap on opposite sides of the gate structure; the first side of the sidewall of the second gap is flush with the second side of the drain depletion injection region; the first side of the sidewall of the fourth gap is flush with the second side of the source depletion injection region; In a plane parallel to the substrate, the lightly doped drain region and the gate structure have an overlapping region; the lightly doped source region and the gate structure have an overlapping region.

3. The MOSFET device according to claim 2, characterized in that: Also includes: Drain metal silicide, gate metal silicide and source metal silicide; The gate metal silicide is disposed above the gate structure; the drain metal silicide is disposed above the heavily doped drain region and a portion of the drain depletion injection region; the source metal silicide is disposed above the heavily doped source region and a portion of the source depletion injection region; There is a gap between the drain metal silicide and the sidewall; there is a gap between the source metal silicide and the sidewall.

4. The MOSFET device according to claim 1, characterized in that: The first doping type is P type; the second doping type is N type.

5. The MOSFET device according to claim 4, characterized in that: The well region is formed by first ion implantation; the implantation energy of the first ion is in the range of 100 KeV to 400 KeV; the implantation dose of the first ion is in the range of 2E13 atom / cm 2 ~6E13atom / cm 2 ; The first ion is a P-type doping ion; The lightly doped drain region and the lightly doped source region are both formed by second ion implantation; the implantation energy of the second ion is in the range of 50 KeV to 300 KeV; the implantation dose of the second ion is in the range of 1E12 atom / cm 2 ~8E12atom / cm 2 ; The second ion is an N-type doping ion; The heavily doped drain region and the heavily doped source region are both formed by third ion implantation; the implantation energy of the third ion is in the range of 10 KeV to 50 KeV; the implantation dose of the third ion is in the range of 2E14 atom / cm 2 ~2E15atom / cm 2 ; The third ion is an N-type doping ion.

6. The MOSFET device according to claim 4, characterized in that: The drain depletion injection region and the source depletion injection region are both formed by fourth ion implantation; the implantation energy of the fourth ion is in the range of 5Kev to 10Kev; the implantation dose of the fourth ion is in the range of 1E13atom / cm 2 ~1E14atom / cm 2 ; The fourth ion is a P-type doped ion.

7. The MOSFET device according to claim 1, characterized in that: The first doping type is N-type; the second doping type is P-type.

8. The MOSFET device according to claim 7, characterized in that: The well region is formed by implanting the fifth ion; the implantation energy of the fifth ion is in the range of 200Kev to 800Kev; the implantation dose of the fifth ion is in the range of 2E13atom / cm 2 ~6E13atom / cm 2 ; The fifth ion is an N-type doping ion; The lightly doped drain region and the lightly doped source region are both formed by implanting the sixth ion; the implantation energy of the sixth ion is in the range of 40 KeV to 200 KeV; the implantation dose of the sixth ion is in the range of 1E12 atom / cm 2 ~8E12atom / cm 2 ; The sixth ion is a P-type doping ion; The heavily doped drain region and the heavily doped source region are both formed by seventh ion implantation; the implantation energy of the seventh ion is in the range of 5Kev to 30Kev; the implantation dose of the seventh ion is in the range of 2E14atom / cm 2 ~2E15atom / cm 2 ; The seventh ion is a P-type doped ion.

9. The MOSFET device according to claim 7, characterized in that: The drain depletion injection region and the source depletion injection region are both formed by eighth ion implantation; the implantation energy range of the eighth ion is 5Kev to 20Kev; the implantation dose range of the eighth ion is 1E13atom / cm 2 ~1E14atom / cm 2 ; The eighth ion is an N-type doped ion.

10. The MOSFET device according to claim 1, characterized in that: The number of the MOSFET devices is multiple; The trench structure is arranged between active areas of two adjacent MOSFET devices; the trench structure is filled with isolation material.

11. A method for preparing a MOSFET device, characterized in that: Used to form the MOSFET device according to any one of claims 1 to 10, comprising: providing a substrate; Ion implantation is performed on the substrate to form a well region having a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region; Performing ion implantation on the active region to form a lightly doped drain region and a lightly doped source region having a second doping type; A gate structure is formed above the active region; the lightly doped drain region and the lightly doped source region are respectively disposed on opposite sides of the gate structure; A heavily doped drain region is formed in the lightly doped drain region by ion implantation; a heavily doped source region is formed in the lightly doped source region by ion implantation; a first side of the heavily doped drain region is flush with the trench structure, and a first gap is formed between the second side of the heavily doped drain region and the gate structure; a first side of the heavily doped source region is flush with the trench structure, and a third gap is formed between the second side of the heavily doped source region and the gate structure; A drain depletion injection region with a first doping type is formed in the first gap by ion implantation; a first side of the drain depletion injection region is flush with a second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure; a source depletion injection region with a first doping type is formed in the third gap by ion implantation; a first side of the source depletion injection region is flush with a second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure.

12. The method for preparing a MOSFET device according to claim 11, characterized in that: After forming a gate structure above the active area, the method further includes: A sidewall is formed in the second gap and the fourth gap on opposite sides of the gate structure; a first side of the sidewall of the second gap is flush with the second side of the drain depletion injection region; a first side of the sidewall of the fourth gap is flush with the second side of the source depletion injection region; in a plane parallel to the substrate, the sidewall overlaps with the lightly doped drain region and the lightly doped source region; Forming a drain depletion injection region having a first doping type in the first gap by ion implantation; forming a source depletion injection region having a first doping type in the third gap by ion implantation, comprising: Using the gate structure and the sidewall as masks, a drain depletion injection region having a first doping type is formed in the lightly doped drain region by ion implantation, and a source depletion injection region having a first doping type is formed in the lightly doped source region by ion implantation.

13. A pixel circuit, characterized in that: include: A MOSFET device as claimed in any one of claims 1 to 10.

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