Ring gate transistor and manufacturing method thereof
By introducing a high mobility material part and a semiconductor covering part in the channel region of the ring gate transistor and optimizing the interface state, the problems of low yield and poor operating performance of the existing ring gate transistor are solved, and the effect of improving yield and operating performance is achieved.
Patent Information
- Application Number
- CN202411640484.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-03-28
AI Technical Summary
The existing ring gate transistors made of channel regions using silicon germanium or germanium have low yields, resulting in poor working performance, mainly due to the poor interface state between the channel region and the gate stacking structure.
The high mobility material part and a semiconductor cover part are introduced into the nanostructure of the channel region. The high mobility material part includes silicon germanium or germanium. The semiconductor cover part is arranged on both sides of the high mobility material part in the thickness direction of the semiconductor substrate, and the gate stack structure and the high mobility material part do not have semiconductor cover parts in both sides of the width direction to improve the interface state.
By improving the interface state between the channel region and the gate stacking structure, the yield and operating performance of the ring gate transistor are improved, process difficulty is reduced, and the problem of poor conduction characteristics caused by inconsistent thickness of the semiconductor cover layer is avoided.
Smart Images
Figure CN119730312A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate-all-around transistor and a manufacturing method thereof. Background Art
[0002] Compared with planar transistors and fin field-effect transistors, ring-gate transistors have better gate control performance, making them a strong candidate for device structures at technology nodes below 3nm. In addition, due to the saturation of the performance of traditional silicon material transistors, their operating voltage cannot be lower than 0.7V. At the same time, the mobility of the channel of semiconductor devices is degraded due to small-scale quantum effects. In addition, the strain engineering caused by the continuous miniaturization of semiconductor devices has a saturation effect, which degrades the performance of semiconductor devices. High-mobility materials such as germanium silicon and germanium have the characteristics of high carrier mobility, so it is necessary to introduce high-mobility materials to replace traditional silicon materials to manufacture channels in order to maintain the continuous improvement of the driving performance of ring-gate transistors and reduce their power consumption.
[0003] However, the yield of the existing all-around gate transistors using silicon germanium or germanium to manufacture the channel region is low, resulting in poor working performance of the all-around gate transistor. Summary of the invention
[0004] The object of the present invention is to provide a ring-gate transistor and a manufacturing method thereof, which is used to improve the yield of the ring-gate transistor, improve the interface state between the gate stack structure and the channel region, and enhance the working performance of the ring-gate transistor when the material of the channel region includes silicon germanium or germanium.
[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a ring-gate transistor, which includes: a semiconductor substrate, an active structure and a gate stack structure. The active structure is arranged on the semiconductor substrate. The active structure includes a source region, a drain region and a channel region. The source region and the drain region are arranged at intervals in a direction parallel to the surface of the semiconductor substrate, and the channel region is located between the source region and the drain region and contacts the source region and the drain region respectively. The channel region includes at least one layer of nanostructure. There is a gap between each layer of nanostructure and the semiconductor substrate, and each layer of nanostructure includes a high-mobility material portion and a semiconductor covering portion arranged on both sides of the high-mobility material portion along the thickness direction of the semiconductor substrate. The material of the high-mobility material portion includes germanium silicon or germanium. The gate stack structure surrounds the periphery of each layer of nanostructure. There is no semiconductor covering portion between the gate stack structure and the two sides of the high-mobility material portion along the width direction. The interface state between the gate stack structure and the semiconductor covering portion is smaller than the interface state between the gate stack structure and the two sides of the high-mobility material portion along the width direction.
[0006] In the case of adopting the above technical solution, in the ring-gate transistor provided by the present invention, each layer of nanostructure includes a high-mobility material portion, and the material of the high-mobility material portion includes germanium silicon or germanium. Compared with silicon materials, germanium silicon or germanium materials have relatively high carrier mobility, which is beneficial to improve the conduction characteristics of the nanostructure and improve the driving performance of the ring-gate transistor. Secondly, each layer of nanostructure also includes a semiconductor covering portion arranged on both sides of the high-mobility material portion along the thickness direction of the semiconductor substrate. The interface state between the semiconductor covering portion and the gate stack structure is relatively small, which can solve the problem of poor interface state caused by direct contact between the high-mobility material portion and the gate stack structure on both sides along the thickness direction. In addition, the high-mobility material portion is the main conductive crystal plane for transmitting carriers on both sides along the thickness direction. Improving the interface state on both sides can greatly improve the transmission performance of the channel region and greatly improve the driving performance of the ring-gate transistor. In addition, there is no semiconductor covering portion between the gate stack structure and the high-mobility material portion on both sides along the width direction. Based on this, in the actual manufacturing process, when a sacrificial layer and a high-mobility material layer (for manufacturing a high-mobility material portion) are epitaxially stacked on a semiconductor substrate, an epitaxial process can be used to form a whole layer of semiconductor covering material layer (for manufacturing a semiconductor covering portion) on both sides of the high-mobility material layer. There is no need to form a surrounding semiconductor covering layer after releasing the nanostructure to improve the interface state, which results in poor conduction characteristics of the nanostructure due to inconsistent thickness of the semiconductor covering layer. The process difficulty of selective epitaxy to form a surrounding semiconductor covering portion after releasing the nanostructure can be reduced, which is beneficial to improving the yield and working performance of semiconductor devices.
[0007] In one example, the material of the semiconductor capping portion includes silicon.
[0008] In one example, the material of the semiconductor cover portion includes germanium silicon. The germanium content in the semiconductor cover portion is less than the germanium content in the high-mobility material portion, and the germanium content in the semiconductor cover portion gradually decreases in a direction away from the high-mobility material portion.
[0009] In one example, the thickness of the semiconductor covering portion is greater than or equal to 0.5 nm and less than or equal to 1.5 nm.
[0010] In one example, the thicknesses of different layers of semiconductor covers are the same.
[0011] In one example, different regions in the same semiconductor cover layer have the same thickness.
[0012] In one example, the material of the high mobility material portion includes Si 1-x Ge x , 0.2≤x≤0.8.
[0013] In a second aspect, the present invention provides a method for manufacturing a ring-gate transistor, the method for manufacturing a ring-gate transistor comprising: first, providing a semiconductor substrate. Next, forming an active structure on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region. The source region and the drain region are arranged at intervals in a direction parallel to the surface of the semiconductor substrate, and the channel region is located between the source region and the drain region and contacts the source region and the drain region respectively. The channel region comprises at least one layer of nanostructure. There is a gap between each layer of nanostructure and the semiconductor substrate, and each layer of nanostructure comprises a high-mobility material portion and a semiconductor covering portion arranged on both sides of the high-mobility material portion along the thickness direction of the semiconductor substrate. The material of the high-mobility material portion comprises germanium silicon or germanium. Next, forming a gate stack structure surrounding the periphery of each layer of nanostructure. There is no semiconductor covering portion between the gate stack structure and the two sides of the high-mobility material portion along the width direction. The interface state between the gate stack structure and the semiconductor covering portion is smaller than the interface state between the gate stack structure and the two sides of the high-mobility material portion along the width direction.
[0014] In one example, an active structure is formed on a semiconductor substrate, including: forming at least one stacked layer on the semiconductor substrate by an epitaxial process along the thickness direction of the semiconductor substrate. Each stacked layer includes a sacrificial layer, a high mobility material layer located on the sacrificial layer, and a semiconductor covering material layer arranged on both sides of the high mobility material layer along the thickness direction of the semiconductor substrate. Next, etching at least one stacked layer to form a fin-shaped structure on the semiconductor substrate. Next, an active structure is formed based on the fin-shaped structure.
[0015] In one example, an active structure is formed based on a fin-shaped structure, including: forming a mask structure across the fin-shaped structure. Next, removing a portion of the fin-shaped structure exposed outside the mask structure; and using an epitaxial process to form a source region and a drain region on both sides of the remaining fin-shaped structure. Next, removing at least a portion of the mask structure. Next, removing the remaining sacrificial layer. The remaining high-mobility material layer forms a high-mobility material portion, and the remaining semiconductor covering material layer forms a semiconductor covering portion.
[0016] In one example, the material of the high mobility material layer includes silicon germanium, the material of the sacrificial layer includes silicon germanium or germanium, and the germanium content in the sacrificial layer is at least 20% higher than the germanium content in the high mobility material layer; or, the material of the high mobility material layer includes silicon germanium or germanium, the material of the sacrificial layer includes silicon germanium, and the germanium content in the sacrificial layer is at least 20% lower than the germanium content in the high mobility material layer.
[0017] In one example, a difference between a thickness of the semiconductor covering material layer and a thickness of the semiconductor covering portion is less than or equal to 1.5 nm.
[0018] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0020] Figure 1 It is a schematic longitudinal cross-sectional view of the structure of a gate-all-around transistor in the channel region in the related art;
[0021] Figure 2 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 1 ;
[0022] Figure 3 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ;
[0023] Figure 4 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ;
[0024] Figure 5 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 4 ;
[0025] Figure 6 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 5 ;
[0026] Figure 7 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 6 ;
[0027] Figure 8 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 7 ;
[0028] Fig. 9 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 8 ;
[0029] Fig.10 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 9 ;
[0030] Fig.11A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 .
[0031] Figure numerals: 11 is a semiconductor substrate, 12 is a source region, 13 is a drain region, 14 is a channel region, 15 is a nanostructure, 16 is a high-mobility material portion, 17 is a semiconductor covering portion, 18 is a shallow trench isolation structure, 19 is a gate sidewall, 20 is an interlayer dielectric layer, 21 is a sacrificial layer, 22 is a high-mobility material layer, 23 is a semiconductor covering material layer, 24 is a fin structure, 25 is a mask structure, and 26 is a gate stack structure. DETAILED DESCRIPTION
[0032] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.
[0033] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0034] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0037] Compared with planar transistors and fin field-effect transistors, ring-gate transistors have better gate control performance, making them a strong candidate for device structures at technology nodes below 3nm. In addition, due to the saturation of the performance of traditional silicon material transistors, their operating voltage cannot be lower than 0.7V. At the same time, the mobility of the channel of semiconductor devices is degraded due to small-scale quantum effects. In addition, the strain engineering caused by the continuous miniaturization of semiconductor devices has a saturation effect, which degrades the performance of semiconductor devices. High-mobility materials such as germanium silicon and germanium have the characteristics of high carrier mobility, so it is necessary to introduce high-mobility materials to replace traditional silicon materials to manufacture channels in order to maintain the continuous improvement of the driving performance of ring-gate transistors and reduce their power consumption.
[0038] However, the existing ring-gate transistors using germanium silicon or germanium to manufacture the channel region have a low yield, resulting in poor performance of the ring-gate transistor. Specifically, although the conduction characteristics of the channel region can be improved by using germanium silicon or germanium materials with high carrier mobility to manufacture the channel region. However, compared with materials such as silicon, the interface state between the channel region manufactured from germanium silicon or germanium materials and the gate stack structure is poor, resulting in poor performance of the ring-gate transistor. In response to this technical problem, technical personnel in this field remove the sacrificial gate and, after releasing the channel region by removing the sacrificial layer, epitaxially grow a layer of surrounding silicon material on the periphery of the channel region manufactured from germanium silicon or germanium materials, so as to improve the interface state between the channel region and the gate stack structure through the silicon material. However, Figure 1 As shown, when the silicon material is formed by epitaxial process, the growth rate of silicon in different crystal directions is different, resulting in different thicknesses of silicon material in different areas around the channel region made of germanium silicon or germanium material. In addition, the epitaxial temperature of silicon material is relatively high, while germanium silicon or germanium material has low temperature characteristics. There are great technical challenges in forming surrounding silicon material on the channel region made of germanium silicon or germanium material, and it is easy to have problems such as germanium diffusion, resulting in poor working performance of the ring-gate transistor.
[0039] In order to solve the above technical problems, an embodiment of the present invention provides a ring-gate transistor and a method for manufacturing the same. Among them, in the ring-gate transistor provided by the embodiment of the present invention, each layer of the nanostructure includes a high-mobility material portion and a semiconductor covering portion arranged on both sides of the high-mobility material portion along the thickness direction of the semiconductor substrate. There is no semiconductor covering portion between the gate stack structure and the two sides of the high-mobility material portion along the width direction. The interface state between the gate stack structure and the semiconductor covering portion is smaller than the interface state between the gate stack structure and the two sides of the high-mobility material portion along the width direction, so as to improve the yield and working performance of the semiconductor device.
[0040] Specifically, in a first aspect, an embodiment of the present invention provides a gate-all-around transistor. Fig.11 As shown, the ring-gate transistor includes: a semiconductor substrate 11, an active structure and a gate stack structure 26. The active structure is arranged on the semiconductor substrate 11. The active structure includes a source region 12, a drain region 13 and a channel region 14. The source region 12 and the drain region 13 are arranged in a direction parallel to the surface of the semiconductor substrate 11, and the channel region 14 is located between the source region 12 and the drain region 13 and contacts the source region 12 and the drain region 13 respectively. The channel region 14 includes at least one layer of nanostructure 15. There is a gap between each layer of nanostructure 15 and the semiconductor substrate 11, and each layer of nanostructure 15 includes a high-mobility material portion 16 and a semiconductor covering portion 17 arranged on both sides of the high-mobility material portion 16 along the thickness direction of the semiconductor substrate 11. The material of the high-mobility material portion 16 includes germanium silicon or germanium. The gate stack structure 26 surrounds the periphery of each layer of nanostructure 15. There is no semiconductor covering portion 17 between the gate stack structure 26 and the two sides of the high-mobility material portion 16 along the width direction. The interface state between the gate stack structure 26 and the semiconductor covering portion 17 is smaller than the interface state between the gate stack structure 26 and both sides of the high-mobility material portion 16 along the width direction.
[0041] When the above technical solution is adopted, Fig.11As shown, in the ring-gate transistor provided by the embodiment of the present invention, each layer of nanostructure 15 includes a high-mobility material portion 16, and the material of the high-mobility material portion 16 includes germanium silicon or germanium. Compared with silicon materials, germanium silicon or germanium materials have relatively high carrier mobility, which is conducive to improving the conduction characteristics of the nanostructure 15 and improving the driving performance of the ring-gate transistor. Secondly, each layer of nanostructure 15 also includes a semiconductor covering portion 17 arranged on both sides of the high-mobility material portion 16 along the thickness direction of the semiconductor substrate 11. The interface state between the semiconductor covering portion 17 and the gate stack structure 26 is relatively small, which can solve the problem of poor interface state caused by the high-mobility material portion 16 directly contacting the gate stack structure 26 on both sides along the thickness direction. In addition, the two sides of the high-mobility material portion 16 along the thickness direction are the main conductive crystal planes for transmitting carriers. Improving the interface state on both sides can greatly improve the transmission performance of the channel region 14 and greatly improve the driving performance of the ring-gate transistor. In addition, there is no semiconductor covering portion 17 between the gate stack structure 26 and the two sides of the high-mobility material portion 16 along the width direction. Based on this, in the actual manufacturing process, Figures 2 to 11 As shown, when a sacrificial layer 21 and a high-mobility material layer 22 (for manufacturing a high-mobility material portion 16) are epitaxially stacked on a semiconductor substrate 11, an epitaxial process is used to form a whole layer of semiconductor covering material layer 23 (for manufacturing a semiconductor covering portion 17) on both sides of the high-mobility material layer 22. There is no need to form a surrounding semiconductor covering layer after the nanostructure is released to improve the interface state, which may lead to poor conduction characteristics of the nanostructure due to inconsistent thickness of the semiconductor covering layer. The process difficulty of selective epitaxy for forming a surrounding semiconductor covering portion 17 after the nanostructure 15 is released can be reduced, which is beneficial to improving the yield and working performance of semiconductor devices.
[0042] In actual application, the embodiment of the present invention does not specifically limit the material and structure of the semiconductor substrate, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.
[0043] Exemplarily, the semiconductor substrate may be a semiconductor substrate on which no structure is formed, such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate or a germanium substrate.
[0044] Alternatively, the semiconductor substrate may also be a semiconductor substrate with some structures formed thereon. For example, when the gate-all-around transistor in the embodiment of the present invention is a second-layer or higher-layer gate-all-around transistor in a semiconductor device, the semiconductor substrate includes a semiconductor structure and an interlayer dielectric layer located below the gate-all-around transistor.
[0045] For the above active structure, from the structural aspect, the channel region of the active structure may include only one layer of nanostructure, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate. The number of layers of nanostructures included in the channel region may be set according to actual needs and is not specifically limited here.
[0046] From the material aspect, the material of the source region and the drain region included in the active structure may include any semiconductor material such as silicon, silicon germanium or germanium, and no specific limitation is made here.
[0047] For the channel region in the active structure, each layer of the nanostructure in the channel region includes a material of a high-mobility material portion including silicon germanium or germanium, wherein the germanium content in the silicon germanium material can be any value greater than 0 and less than 1. The germanium content in the high-mobility material portion is set according to the actual manufacturing process and actual needs, as long as it can be applied to the ring-gate transistor provided by the present invention. Exemplarily, the material of the high-mobility material portion includes Si 1-x Ge x , 0.2≤x≤0.8. For example, the material of the high mobility material portion may be Si 0.8 Ge 0.2 、Si 0.7 Ge 0.3 、Si 0.6 Ge 0.4 、Si 0.5 Ge 0.5 、Si 0.3 Ge 0.7 or Si 0.2 Ge 0.8 In this case, the germanium content in the high-mobility material portion is not too large. In the actual manufacturing process, germanium silicon or germanium with a relatively high germanium content can be used to manufacture the sacrificial layer, so as to reduce the influence of the etchant on the high-mobility material portion and the semiconductor covering portion when releasing the nanostructure, thereby improving the yield of the all-around gate transistor.
[0048] As for the semiconductor covering portion, Fig.11 As shown, the semiconductor covering portion 17 is located on both sides of the high mobility material portion 16 along the thickness direction, while the high mobility material portion 16 does not have the semiconductor covering portion 17 on both sides along the width direction. The thickness and material of the semiconductor covering portion 17 can be set according to actual needs, as long as the interface state between the gate stack structure 26 and the semiconductor covering portion 17 can be satisfied and smaller than the interface state between the gate stack structure 26 and the high mobility material portion 16 on both sides along the width direction.
[0049] By way of example, the material of the semiconductor cover may include silicon.
[0050] For example, the material of the semiconductor covering portion may include silicon germanium. The germanium content in the semiconductor covering portion is less than the germanium content in the high mobility material portion, and the germanium content in the semiconductor covering portion gradually decreases in the direction away from the high mobility material portion. In this case, the difference between the germanium content in the semiconductor covering portion and the germanium content in the high mobility material portion can be set according to actual needs, as long as it can be applied to the ring gate transistor provided in the embodiment of the present invention. For example: the material of the semiconductor covering portion includes Si 1-y Ge y , 0≤y<0.2. Next, in this case, the material of the semiconductor covering portion on the side away from the high-mobility material portion may be germanium silicon or silicon.
[0051] As for the thickness of the semiconductor covering portion, illustratively, the thickness of the semiconductor covering portion may be greater than or equal to 0.5 nm and less than or equal to 1.5 nm. For example, the thickness of the semiconductor covering portion may be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.2 nm, 1.4 nm or 1.5 nm, etc. In this case, the thickness of the semiconductor covering portion is within the above range, which can prevent the interface state between the nanostructure and the gate stack structure from being improved less due to the small thickness of the semiconductor covering portion. In addition, it can also prevent the poor carrier mobility of the nanostructure due to the large thickness of the semiconductor covering portion, thereby ensuring that the ring-gate transistor has a higher driving performance.
[0052] The thickness of different layers of semiconductor covering parts can be the same or different; in addition, the thickness of different regions in the same layer of semiconductor covering parts can be the same or different. When the thickness of different layers of semiconductor covering parts is the same, and the thickness of different regions in the same layer of semiconductor covering parts is the same, each region of the nanostructure has good conduction uniformity, which is conducive to further improving the driving performance of the all-around gate transistor.
[0053] For the above-mentioned gate stack structure, the gate stack structure may include a gate dielectric layer surrounding the periphery of the nanostructure, and a gate formed on the gate dielectric layer. The material of the gate dielectric layer included in the gate stack structure may include any insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the above-mentioned gate may include any conductive material such as TiN, TaN or TiSiN.
[0054] In some cases, such as Figure 7 and Fig.11As shown, the ring-gate transistor may also include: a shallow trench isolation structure 18, a gate sidewall 19 and an interlayer dielectric layer 20. The shallow trench isolation structure 18 is located on the semiconductor substrate 11 and is used to define different active areas of the semiconductor substrate 11. The gate sidewalls 19 are located on both sides of the gate stack structure 26 along the length direction to separate the gate stack structure 26 from other conductive structures formed subsequently to reduce the risk of leakage. The interlayer dielectric layer 20 covers the semiconductor substrate 11 and is used to protect the source region 12 and the drain region 13 located on the top layer from the influence of subsequent etching or cleaning operations, thereby further improving the yield of the semiconductor device. As for the materials of the shallow trench isolation structure 18, the gate sidewall 19 and the interlayer dielectric layer 20, they may include any insulating material such as silicon oxide, silicon oxynitride or silicon oxynitride, which is not specifically limited here.
[0055] In a second aspect, an embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. Figures 2 to 11 The manufacturing process is described by a cross-sectional view or a stereoscopic view of the operation shown. Specifically, the manufacturing method of the ring-gate transistor includes the following steps:
[0056] First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can be referred to above and will not be described in detail here.
[0057] Next, if Fig.11 As shown, an active structure is formed on a semiconductor substrate 11. The active structure includes a source region 12, a drain region 13 and a channel region 14. The source region 12 and the drain region 13 are arranged at intervals in a direction parallel to the surface of the semiconductor substrate 11, and the channel region 14 is located between the source region 12 and the drain region 13, and is in contact with the source region 12 and the drain region 13 respectively. The channel region 14 includes at least one layer of nanostructure 15. There is a gap between each layer of nanostructure 15 and the semiconductor substrate 11, and each layer of nanostructure 15 includes a high-mobility material portion 16, and a semiconductor covering portion 17 arranged on both sides of the high-mobility material portion 16 along the thickness direction of the semiconductor substrate 11. The material of the high-mobility material portion 16 includes germanium silicon or germanium.
[0058] Specifically, the materials and specific structures of each part in the active structure can be referred to in the previous text and will not be repeated here.
[0059] Exemplarily, the above-mentioned forming of an active structure on a semiconductor substrate may include the steps of:
[0060] like Figure 2 As shown, along the thickness direction of the semiconductor substrate 11, an epitaxial process is used to form at least one stacked layer on the semiconductor substrate 11. Each stacked layer includes a sacrificial layer 21, a high mobility material layer 22 located on the sacrificial layer 21, and a semiconductor covering material layer 23 arranged on both sides of the high mobility material layer 22 along the thickness direction of the semiconductor substrate 11.
[0061] Specifically, each of the above-mentioned high-mobility material layers is used to manufacture the high-mobility material portion, so the number of layers of the stack formed on the semiconductor substrate and the material and thickness of the high-mobility material layer can be determined according to the number of layers of the nanostructure included in the channel region of the ring-gate transistor described above, and the material and thickness of each layer of the high-mobility material portion in the nanostructure. Secondly, each layer of the nanostructure will be released by selectively removing the remaining sacrificial layer, so the material of the sacrificial layer can be any semiconductor material different from the high-mobility material layer and the semiconductor covering material layer.
[0062] For example, when the material of the high mobility material layer includes silicon germanium and the material of the sacrificial layer includes silicon germanium or germanium, the germanium content in the sacrificial layer may be at least 20% higher than the germanium content in the high mobility material layer (for example, when the material of the high mobility material layer is Si 0.5 Ge 0.5 In the case of 0.3 Ge 0.7 、Si 0.2 Ge 0.8 、Si 0.1 Ge 0.9 Or, when the material of the high mobility material layer includes germanium silicon or germanium, and the material of the sacrificial layer includes germanium silicon, the germanium content in the sacrificial layer is at least 20% lower than the germanium content in the high mobility material layer (for example, when the material of the high mobility material layer is Si 0.2 Ge 0.8 In the case of 0.4 Ge 0.6 、Si 0.5 Ge 0.5 、Si 0.6 Ge 0.4 or Si 0.7 Ge 0.3 wait).
[0063] As for the material and thickness of the semiconductor covering material layer, reference can be made to the material and thickness of the semiconductor covering part described above, which will not be repeated here. In addition, in the actual application process, the thickness of the semiconductor covering material layer may be greater than or equal to the semiconductor covering part. Among them, when the thickness of the semiconductor covering material layer is greater than the thickness of the semiconductor covering part, it can prevent subsequent etching or cleaning processes from affecting the semiconductor covering material layer and causing the thickness of the semiconductor covering part to be too small, and reserve a manufacturing margin to obtain a semiconductor covering part of appropriate thickness. As for the difference between the thickness of the semiconductor covering material layer and the thickness of the semiconductor covering part, it can be determined according to the actual manufacturing process and actual needs, and is not specifically limited here.
[0064] Exemplarily, the difference between the thickness of the semiconductor covering material layer and the thickness of the semiconductor covering portion can be less than or equal to 1.5 nm to prevent the thickness of the semiconductor covering material layer from being too large, which would result in the thickness of the semiconductor covering portion in the manufactured ring-gate transistor being too large, thereby ensuring that the nanostructure has good conduction characteristics.
[0065] Next, if Figure 3 and Figure 4 As shown, at least one stacked layer is etched to form a fin structure 24 on the semiconductor substrate 11 .
[0066] In the actual manufacturing process, Figure 3 As shown, photolithography and etching processes can be used to etch at least one stacked layer and a portion of the semiconductor substrate 11 to form a fin on the semiconductor substrate 11. Then, as shown in FIG. Figure 4 As shown, a shallow trench isolation structure 18 is formed on a semiconductor substrate 11 by using deposition and etching processes. The top height of the shallow trench isolation structure 18 is less than or equal to the bottom height of the sacrificial layer 21 at the bottom. The part of the fin exposed outside the shallow trench isolation structure 18 is a fin-shaped structure 24.
[0067] Alternatively, when the semiconductor substrate is a semiconductor substrate including a buried oxide layer such as silicon on insulator, the above-mentioned shallow trench isolation structure may not be formed, and at least one stacked layer may be directly etched to form a fin structure on the semiconductor substrate.
[0068] Next, if Figures 5 to 10 As shown, an active structure is formed based on the fin structure 24. The specific manufacturing process of this operation can be determined according to the specific structure and material of the active structure.
[0069] Exemplarily, the above-mentioned formation of an active structure based on a fin-shaped structure may include the following steps:
[0070] like Figure 5 and Figure 6 As shown, deposition and etching processes may be used to form a mask structure 25 spanning the fin structure 24. The specific structure and material of the mask structure 25 may be determined according to the actual application scenario, and are not specifically limited here.
[0071] For example, the mask structure may include a sacrificial gate. For another example, the mask structure may include a gate oxide layer and a sacrificial gate located on the gate oxide layer. For another example, the mask structure may include a sacrificial gate and gate sidewalls located on both sides of the sacrificial gate along the length direction.
[0072] Next, if Figure 7 As shown, a dry etching process or a wet etching process may be used to remove the portion of the fin structure exposed outside the mask structure 25; and Figure 8As shown, an epitaxial process is used to form a source region 12 and a drain region 13 on both sides of the remaining fin structure.
[0073] Alternatively, diffusion or ion implantation or other processes may be used to perform doping treatment on the portion of the fin structure exposed outside the mask structure to form a source region and a drain region.
[0074] Next, if Fig. 9 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 20 covering the semiconductor substrate 11. The top of the interlayer dielectric layer 20 is flush with the top of the mask structure 25. The material of the interlayer dielectric layer 20 can refer to the above.
[0075] Next, if Fig.10 As shown, at least a portion of the mask structure may be removed by using a dry etching process or a wet etching process.
[0076] Specifically, the scope of removal of the mask structure can be determined according to the specific structure of the mask structure, as long as the remaining fin-shaped structure can be exposed. For example, when the mask structure may include a sacrificial gate, the mask structure needs to be completely removed. Another example is when the mask structure may include a sacrificial gate and a gate sidewall, only the sacrificial gate needs to be removed, and only part of the mask structure is removed.
[0077] Next, if Fig.10 As shown, dry etching or wet etching is used to remove the remaining sacrificial layer. The remaining high mobility material layer forms the high mobility material portion 16, and the remaining semiconductor covering material layer forms the surface state. The specific structure and materials of the gate stack structure can be referred to above and will not be repeated here.
[0078] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.
[0079] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0080] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.
Claims
1. A gate-all-around transistor, characterized in that: include: Semiconductor substrate, An active structure is arranged on the semiconductor substrate; the active structure comprises a source region, a drain region and a channel region; the source region and the drain region are arranged at intervals in a direction parallel to the surface of the semiconductor substrate, the channel region is located between the source region and the drain region, and is in contact with the source region and the drain region respectively; the channel region comprises at least one layer of nanostructure; there is a gap between each layer of the nanostructure and the semiconductor substrate, and each layer of the nanostructure comprises a high-mobility material portion and semiconductor covering portions arranged on both sides of the high-mobility material portion along the thickness direction of the semiconductor substrate; The material of the high mobility material portion includes germanium silicon or germanium; A gate stack structure surrounds the periphery of each layer of the nanostructure; there is no semiconductor covering portion between the gate stack structure and both sides of the high mobility material portion along the width direction; and the interface state between the gate stack structure and the semiconductor covering portion is smaller than the interface state between the gate stack structure and both sides of the high mobility material portion along the width direction.
2. The gate-all-around transistor according to claim 1, characterized in that: The material of the semiconductor cover includes silicon.
3. The gate-all-around transistor according to claim 1, wherein: The material of the semiconductor covering portion includes germanium silicon; the germanium content in the semiconductor covering portion is less than the germanium content in the high-mobility material portion, and the germanium content in the semiconductor covering portion gradually decreases in a direction away from the high-mobility material portion.
4. The gate-all-around transistor according to claim 1, wherein: The thickness of the semiconductor covering portion is greater than or equal to 0.5 nm and less than or equal to 1.5 nm; and / or, the thicknesses of the semiconductor covering parts in different layers are the same; And / or, the thicknesses of different regions in the same layer of the semiconductor cover are the same.
5. The gate-all-around transistor according to claim 1, wherein: The material of the high mobility material portion includes Si 1-x Ge x , 0.2≤x≤0.
8.
6. A method for manufacturing a gate-all-around transistor, characterized in that: include: Providing a semiconductor substrate; An active structure is formed on the semiconductor substrate; the active structure comprises a source region, a drain region and a channel region; the source region and the drain region are arranged at intervals in a direction parallel to the surface of the semiconductor substrate, the channel region is located between the source region and the drain region, and is in contact with the source region and the drain region respectively; the channel region comprises at least one layer of nanostructure; there is a gap between each layer of the nanostructure and the semiconductor substrate, and each layer of the nanostructure comprises a high-mobility material portion and a semiconductor covering portion arranged on both sides of the high-mobility material portion along the thickness direction of the semiconductor substrate; the material of the high-mobility material portion comprises germanium silicon or germanium; A gate stack structure is formed around the periphery of each layer of the nanostructure; the semiconductor covering portion is not provided between the gate stack structure and both sides of the high mobility material portion along the width direction; and the interface state between the gate stack structure and the semiconductor covering portion is smaller than the interface state between the gate stack structure and both sides of the high mobility material portion along the width direction.
7. The method for manufacturing a gate-all-around transistor according to claim 6, wherein: The active structure is formed on the semiconductor substrate, comprising: At least one stack is formed on the semiconductor substrate by using an epitaxial process along the thickness direction of the semiconductor substrate; each stack comprises a sacrificial layer, a high mobility material layer located on the sacrificial layer, and a semiconductor covering material layer arranged on both sides of the high mobility material layer along the thickness direction of the semiconductor substrate; Etching the at least one stacked layer to form a fin structure on the semiconductor substrate; The active structure is formed based on the fin-shaped structure.
8. The method for manufacturing a gate-all-around transistor according to claim 7, characterized in that: The forming of the active structure based on the fin-shaped structure comprises: forming a mask structure spanning over the fin-shaped structure; Removing the portion of the fin-shaped structure exposed outside the mask structure; and using an epitaxial process to form the source region and the drain region on both sides of the remaining fin-shaped structure; removing at least a portion of the mask structure; The remaining sacrificial layer is removed; the remaining high-mobility material layer forms the high-mobility material portion, and the remaining semiconductor covering material layer forms the semiconductor covering portion.
9. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: The material of the high mobility material layer includes germanium silicon, the material of the sacrificial layer includes germanium silicon or germanium, and the germanium content in the sacrificial layer is at least 20% higher than the germanium content in the high mobility material layer; Alternatively, the material of the high-mobility material layer includes silicon germanium or germanium, the material of the sacrificial layer includes silicon germanium, and the germanium content in the sacrificial layer is at least 20% lower than the germanium content in the high-mobility material layer.
10. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: A difference between a thickness of the semiconductor covering material layer and a thickness of the semiconductor covering portion is less than or equal to 1.5 nm.