Groove type MOSFET structure and preparation method thereof

Abstract

The invention provides a trench type MOSFET structure and a preparation method thereof, and the trench type MOSFET structure comprises an epitaxial protection layer which extends along a first direction and surrounds the side wall and the bottom surface of a gate structure, the conduction type of the epitaxial protection layer is the same as the conduction type of a drift layer, and the doping concentration of the epitaxial protection layer is greater than the doping concentration of the drift layer; the well region is positioned in the drift layer on two sides of the gate structure and the epitaxial protection layer along the second direction; the doped regions are located in the drift layer on the side, facing the semiconductor substrate layer, of the well region, and any one doped region surrounds the epitaxial protection layer on the side, in the second direction, of one gate region and a part of the epitaxial protection layer on the side, facing the semiconductor substrate layer, of the corresponding gate region; the doped region exposes the epitaxial protection layer on the other side of the corresponding gate region along the second direction and the other part of epitaxial protection layer on one side of the corresponding gate region facing the semiconductor substrate layer, and the conductive type of the doped region is opposite to that of the epitaxial protection layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon Carbide (SiC), a wide bandgap semiconductor material, has become an ideal choice for high-voltage, high-temperature, high-frequency, and high-power power electronic devices due to its advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. SiC Metal-Oxide-Semiconductor FieldEffecTransistor (MOSFET) is a unipolar device with ideal gate insulation characteristics. There is no tail current during the shutdown process, which can greatly reduce switching losses and reduce the size of the heat sink. In addition, the high switching frequency of SiC MOSFET is conducive to reducing the size and weight of source filter components in power electronic devices, and improving the efficiency and power density of the device.

[0003] Compared with planar gate structure SiC MOSFET, trench gate MOSFET can effectively reduce the cell size and increase the channel density. However, for trench SiC MOSFET, the performance needs to be further improved. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to overcome the problem of excessively high electric field strength at the gate dielectric layer at the bottom of the gate structure of the trench MOSFET structure in the prior art.

[0005] In order to solve the above technical problems, the present invention provides a trench MOSFET structure, comprising: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer; a gate structure extending in a first direction in the drift layer, the gate structure enclosing a gate region; an epitaxial protection layer extending in the first direction and enclosing a sidewall and a bottom surface of the gate structure, the conductivity type of the epitaxial protection layer being the same as that of the drift layer, and the doping concentration of the epitaxial protection layer being greater than that of the drift layer; a well region located in the drift layer on both sides of the gate structure and the epitaxial protection layer along a second direction, the second direction being perpendicular to the first direction; a doped region located in the drift layer on a side of the well region facing the semiconductor substrate layer, any one of the doped regions enclosing the epitaxial protection layer on one side of the gate region along the second direction and a portion of the epitaxial protection layer corresponding to the side of the gate region facing the semiconductor substrate layer, and the doped region exposing the epitaxial protection layer on the other side of the gate region along the second direction and another portion of the epitaxial protection layer corresponding to the side of the gate region facing the semiconductor substrate layer, and the conductivity type of the doped region is opposite to that of the epitaxial protection layer.

[0006] Optionally, the doped region is in contact with the well region.

[0007] Optionally, it also includes: a channel region, located in the epitaxial protection layer on the side wall of the gate structure, the side surface of the channel region facing away from the semiconductor substrate layer is spaced from the side surface of the drift layer facing away from the semiconductor substrate layer, and the side surface of the channel region facing the semiconductor substrate layer is spaced from the side surface of the gate structure facing the semiconductor substrate layer.

[0008] Optionally, it further includes: a source region located in a partial area of ​​the well region and in the epitaxial protection layer on a side of the channel region away from the semiconductor substrate layer.

[0009] Optionally, the gate structure includes a gate region; the orthographic projection pattern of the doped region on the semiconductor substrate layer is in the shape of a long strip.

[0010] Optionally, the gate structure includes a plurality of gate regions arranged at intervals along the first direction; an epitaxial protection layer on the sidewalls and bottom of the gate structure is surrounded by a plurality of the doped regions spaced along the first direction; wherein, for two adjacent doped regions along the first direction, one doped region is located on one side of one gate region along the second direction, and the other doped region is located on the other side of the other gate region along the second direction.

[0011] Optionally, the gate structure includes a plurality of gate regions arranged at intervals along the first direction; an epitaxial protection layer on the sidewalls and bottom of the gate structure is surrounded by a plurality of the doped regions spaced along the first direction; wherein, for two adjacent doped regions along the first direction, the two doped regions are located on the same side of different gate regions along the second direction.

[0012] Optionally, for adjacent gate structures, the doped region of the epitaxial protection layer surrounding the sidewall and bottom of one gate structure is spaced apart from the doped region of the epitaxial protection layer surrounding the sidewall and bottom of another gate structure.

[0013] Optionally, for adjacent gate structures, the doped region of the epitaxial protection layer surrounding the sidewall of one gate structure and the doped region of the epitaxial protection layer surrounding the sidewall of another gate structure are both located on the same side of the corresponding gate region along the second direction.

[0014] Optionally, for the gate regions adjacent to each other along the second direction, the doped region of the epitaxial protection layer surrounding the side wall of one gate region is located on one side of the corresponding gate region along the second direction, and the doped region of the epitaxial protection layer surrounding the side wall of another gate region is located on the other side of the corresponding gate region along the second direction.

[0015] Optionally, for every two adjacent gate regions along the second direction, the doped region of the epitaxial protection layer surrounding the side wall of one gate region and the doped region of the epitaxial protection layer surrounding the side wall of another gate region are connected together.

[0016] Optionally, the doping concentration of the epitaxial protection layer is 3 to 8 times the doping concentration of the drift layer.

[0017] Optionally, the doping concentration of the doping region is less than the doping concentration of the well region.

[0018] The present application also provides a method for preparing a trench MOSFET structure, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a gate structure extending along a first direction in the drift layer, the gate structure comprising a gate region; forming an epitaxial protection layer in the drift layer, the epitaxial protection layer extending along the first direction, the conductivity type of the epitaxial protection layer being the same as the conductivity type of the drift layer, and the doping concentration of the epitaxial protection layer being greater than the doping concentration of the drift layer; forming a well region in the drift layer; forming a doped region in the drift layer; the epitaxial protection layer surrounds the sidewalls and bottom surface of the gate structure; the well region is located in the The gate structure and the epitaxial protection layer are on both sides along a second direction, and the second direction is perpendicular to the first direction; the doped region is located on the side of the well region facing the semiconductor substrate layer, and any one of the doped regions surrounds the epitaxial protection layer on one side of the gate region along the second direction and a portion of the epitaxial protection layer corresponding to the side of the gate region facing the semiconductor substrate layer, and the doped region exposes the epitaxial protection layer on the other side of the gate region along the second direction and another portion of the epitaxial protection layer corresponding to the side of the gate region facing the semiconductor substrate layer, and the conductivity type of the doped region is opposite to the conductivity type of the epitaxial protection layer.

[0019] Optionally, the step of forming the gate structure includes: forming a groove in the drift layer; forming the gate structure in the groove; wherein the step of forming the epitaxial protection layer includes: before forming the gate structure in the groove, forming the epitaxial protection layer on the inner wall surface of the groove; wherein the step of forming the doped region includes: before forming the epitaxial protection layer on the inner wall surface of the groove, forming the doped region in a portion of the drift layer at the bottom of the groove and in the drift layer on the side of the groove.

[0020] Optionally, it also includes: forming a channel region in the epitaxial protection layer on the side wall surface of the groove, the side surface of the channel region facing away from the semiconductor substrate layer is separated from the side surface of the drift layer facing away from the semiconductor substrate layer, and the side surface of the channel region facing the semiconductor substrate layer is separated from the epitaxial protection layer on the bottom wall of the groove.

[0021] The technical solution of the present invention has the following technical effects:

[0022] The trench MOSFET structure provided by the technical solution of the present invention, any one of the doped regions surrounds the epitaxial protection layer on one side of the gate region along the second direction and a portion of the epitaxial protection layer corresponding to the gate region facing the semiconductor substrate layer, and the doped region exposes the epitaxial protection layer on the other side of the gate region along the second direction and another portion of the epitaxial protection layer corresponding to the gate region facing the semiconductor substrate layer. When the trench MOSFET structure is in reverse withstand voltage, the doped region can form a PN junction with the drift layer at the bottom of the doped region, and the doped region can form a PN junction with the epitaxial protection layer, and part of the electric field peak is transferred to the junction of the PN junction. The PN junction protects the gate dielectric layer at the bottom of the gate structure, so that the shielding effect of the doped region on the electric field is enhanced, the electric field strength at the position of the gate dielectric layer is reduced, and the protective effect of the doped region on the gate dielectric layer is enhanced. Because the doping concentration of the epitaxial protection layer is greater than the doping concentration of the drift layer, the forward conduction resistance is reduced. The epitaxial protection layer is used to provide a forward conduction path. In summary, the performance of the trench MOSFET structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a trench MOSFET structure provided by an embodiment of the present invention;

[0025] Figure 2 Figure 1 A top view of the doped layer;

[0026] Figure 3 Figure 1 Another top view of the doped layer;

[0027] Figure 4 Figure 1 Another top view of the doped layer;

[0028] Figure 5 A schematic diagram of a trench MOSFET structure provided by another embodiment of the present invention;

[0029] Figure 6 Figure 5 A top view of the doped layer;

[0030] Figure 7 Figure 5 Another top view of the doped layer;

[0031] Figure 8 Figure 5 Another top view of the doped layer;

[0032] Fig. 9 A schematic diagram of a trench MOSFET structure provided by another embodiment of the present invention;

[0033] Fig.10 Fig. 9 A top view of the doped layer;

[0034] Fig.11 Fig. 9 Another top view of the doped layer;

[0035] Figures 12 to 19 A structural diagram of a process for preparing a trench MOSFET structure provided by an embodiment of the present invention;

[0036] Figure 20 to Figure 24 A structural diagram of a preparation process of a trench MOSFET structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0041] An embodiment of the present application provides a trench MOSFET structure, referring to Figure 1 ,include:

[0042] Semiconductor substrate layer 100;

[0043] A drift layer 110 located on one side of the semiconductor substrate layer 100;

[0044] A gate structure 150 extending along a first direction Y in the drift layer 110 , wherein the gate structure 150 includes a gate region;

[0045] an epitaxial protection layer 190 extending along the first direction Y and surrounding the sidewall and bottom surface of the gate structure 150 , wherein the conductivity type of the epitaxial protection layer 190 is the same as the conductivity type of the drift layer 110 , and the doping concentration of the epitaxial protection layer 190 is greater than the doping concentration of the drift layer 110 ;

[0046] The well region 120 is located in the drift layer 110 on both sides of the gate structure 150 and the epitaxial protection layer 190 along a second direction X, where the second direction X is perpendicular to the first direction Y;

[0047] The doped regions 140 are located in the drift layer 110 on the side of the well region 120 facing the semiconductor substrate layer 100, any one of the doped regions 140 surrounds the epitaxial protection layer 190 on one side of the gate region along the second direction X and a portion of the epitaxial protection layer 190 corresponding to the gate region on the side facing the semiconductor substrate layer 100, and the doped regions 140 expose the epitaxial protection layer 190 on the other side of the gate region along the second direction X and another portion of the epitaxial protection layer 190 corresponding to the gate region on the side facing the semiconductor substrate layer 100, and the conductivity type of the doped regions 140 is opposite to the conductivity type of the epitaxial protection layer 190.

[0048] In the trench MOSFET structure of this embodiment, any one of the doped regions 140 surrounds the epitaxial protection layer 190 on one side of the gate region along the second direction X and a portion of the epitaxial protection layer 190 corresponding to the gate region facing the semiconductor substrate layer 100, and the doped region 140 exposes the epitaxial protection layer 190 on the other side of the gate region along the second direction X and another portion of the epitaxial protection layer 190 corresponding to the gate region facing the semiconductor substrate layer 100. When the trench MOSFET structure is in reverse withstand voltage, the doped region 140 can form a PN junction with the drift layer 110 at the bottom of the doped region 140, and the doped region 140 can form a PN junction with the epitaxial protection layer 190, and part of the electric field peak is transferred to the junction of the PN junction, and the PN junction protects the gate dielectric layer at the bottom of the gate structure 150, so that the shielding effect of the doped region 140 on the electric field is enhanced, the electric field strength at the position of the gate dielectric layer 151 is reduced, and the protective effect of the doped region 140 on the gate dielectric layer 151 is enhanced.

[0049] The trench MOSFET structure refers to: the gate structure in the MOSFET adopts a trench gate structure.

[0050] The doped region 140 exposes the epitaxial protection layer 190 on the other side of the corresponding gate region along the second direction X and another portion of the epitaxial protection layer 190 on the side of the corresponding gate region toward the semiconductor substrate layer 100, which means that the doped region 140 does not surround the epitaxial protection layer 190 on the other side of the corresponding gate region along the second direction X and another portion of the epitaxial protection layer 190 on the side of the corresponding gate region toward the semiconductor substrate layer 100.

[0051] For the same gate region, the epitaxial protection layer 190 on one side of the gate region along the second direction X and a portion of the epitaxial protection layer 190 on the side of the gate region facing the semiconductor substrate layer 100 are surrounded by a doped region, and the epitaxial protection layer 190 on the other side of the gate region along the second direction X and another portion of the epitaxial protection layer 190 on the side of the gate region facing the semiconductor substrate layer 100 are not surrounded by the doped region.

[0052] The doped region 140 is in contact with the epitaxial protection layer 190 .

[0053] In this embodiment, the new generation SiC-based trench MOSFET structure represented by SiC has higher reverse withstand voltage, lower forward conduction loss, faster switching frequency and stronger environmental tolerance than the Si-based trench MOSFET structure, and is therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0054] In this embodiment, the conductivity type of the drift layer 110 is the same as the conductivity type of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is less than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the material of the drift layer is silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0055] In this embodiment, the conductivity type of the well region 120 is opposite to the conductivity type of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the well region 120 is P-type.

[0056] In this embodiment, the trench MOSFET structure further includes: a channel region 170, which is located in the epitaxial protection layer 190 on the side wall of the gate structure 150, wherein a surface of the channel region 170 facing away from the semiconductor substrate layer 100 is spaced from a surface of the drift layer 110 facing away from the semiconductor substrate layer 100, and a surface of the channel region 170 facing the semiconductor substrate layer 100 is spaced from a surface of the gate structure 150 facing the semiconductor substrate layer 100. The conductivity type of the channel region 170 is the same as the conductivity type of the well region 120.

[0057] In this embodiment, the trench MOSFET structure further includes: a source region 130, which is located in a portion of the well region 120 and in the epitaxial protection layer 190 on the side of the channel region 170 away from the semiconductor substrate layer 100. The conductivity type of the source region 130 is opposite to the conductivity type of the well region 120. In one embodiment, the conductivity type of the well region 120 is P type, and the conductivity type of the source region 130 is N type.

[0058] In this embodiment, the doping concentration of the channel region 170 is less than the doping concentration of the source region 130 and less than the doping concentration of the well region 120. Since the doping concentration of the channel region 170 is relatively small, the conductivity type of the source region 130 will not be changed. Since the conductivity type of the ions injected into the channel region 170 is the same as the conductivity type of the ions in the well region 120, the conductivity type of the well region 120 will not be changed.

[0059] The doping concentration of the channel region 170 is relatively small, which makes the channel region 170 more easily inverted and the channel resistance smaller.

[0060] When the trench MOSFET structure is forward-conducted, electrons pass from the source region 130 through the channel region 170 and the epitaxial protection layer 190 at the bottom of the channel region 170 , and then pass from the epitaxial protection layer 190 through the drift layer 110 at the side of the doped region 140 along the second direction X, and then reach the semiconductor substrate layer 100 .

[0061] Since the doping concentration of the epitaxial protection layer 190 is greater than the doping concentration of the drift layer 110 , the forward conduction resistance is reduced. The epitaxial protection layer 190 is used to provide a forward conduction path.

[0062] In this embodiment, the channel region 170 is located in the epitaxial protection layer 190 on the side wall of the gate structure 150, and the doping concentration of the channel region 170 and the length of the channel region 170 can be well controlled, so that the threshold voltage and the channel resistance can be independently regulated. Again, when the trench MOSFET structure is forward-conducted, the epitaxial protection layer 190 on the side wall of the gate structure 150 acts as an accumulation layer under the action of the gate structure 150 and can play a role in current expansion. The length direction of the channel region 170 is parallel to the Z direction.

[0063] In this embodiment, the doped region 140 is in contact with the well region 120 , so that the doped region 140 can surround more sidewalls of the gate region and better protect the gate structure.

[0064] Since the channel region 170 is located in the epitaxial protection layer 190 , even if the doped region 140 is in contact with the well region 120 , the provision of the doped region 140 will not increase the channel resistance.

[0065] It should be noted that, in this embodiment Figure 1 In the embodiment, the doped region is in contact with the well region as an example. In other embodiments, the doped region is spaced apart from the well region.

[0066] The width direction of the gate structure 150 is parallel to the second direction X. The length direction of the gate structure 150 is parallel to the first direction Y.

[0067] The number of the gate structure 150 is one or more. When the number of the gate structure 150 is multiple, the multiple gate structures 150 are arranged along the second direction X at intervals.

[0068] In one embodiment, the doping concentration of the epitaxial protection layer 190 is 3 to 8 times the doping concentration of the drift layer 110. In other embodiments, the doping concentration of the epitaxial protection layer 190 is not limited.

[0069] In one embodiment, the doping concentration of the doping region 140 is less than the doping concentration of the well region 120 .

[0070] In one embodiment, the doping concentration of the well region 120 is 2 to 5 times the doping concentration of the doping region 140 .

[0071] Since the well region 120 does not have a channel region, the doping concentration of the well region 120 can be set relatively high without affecting the doping concentration of the channel region. The doping concentration of the well region 120 is set relatively high, so that the contact resistance between the front electrode and the well region 120 is relatively low, and there is no need to set an additional ohmic contact region in the well region. In one embodiment, the doping concentration of the well region 120 is 5E18atom / cm 3 ~1E20atom / cm 3 , 5E18atom / cm 3 、1E19atom / cm 3 、5E19atom / cm 3 or 1E20atom / cm 3 .

[0072] In this embodiment, the gate structure 150 includes a gate dielectric layer 151 and a gate electrode layer 152. The gate dielectric layer 151 is located on the sidewall of the gate electrode layer 152 and the surface of the gate electrode layer 152 facing the semiconductor substrate layer 100. The material of the gate dielectric layer 151 includes silicon oxide, and the material of the gate electrode layer 152 includes polysilicon.

[0073] In one embodiment, in conjunction with reference Figure 1 and Figure 4 The gate structure 150 includes a gate region; the orthographic projection pattern of the doped region 140 on the semiconductor substrate layer 100 is in the shape of a long strip.

[0074] In one embodiment, in conjunction with reference Figure 1 and Figure 2 The gate structure 150 includes a plurality of gate regions arranged at intervals along a first direction Y; the epitaxial protection layer 190 on the sidewalls and the bottom of a gate structure 150 is surrounded by a plurality of doped regions 140 spaced apart along the first direction Y; wherein, for two doped regions 140 adjacent to each other along the first direction Y, one doped region 140 is located on one side of one gate region along the second direction X, and the other doped region 140 is located on the other side of the other gate region along the second direction X.

[0075] In one embodiment, in conjunction with reference Figure 1 and Figure 3 The gate structure 150 includes a plurality of gate regions arranged at intervals along a first direction Y; the epitaxial protection layer 190 on the sidewalls and bottom of a gate structure 150 is surrounded by a plurality of doped regions 140 spaced apart along the first direction Y; wherein, for two adjacent doped regions 140 along the first direction Y, the two doped regions 140 are located on the same side of different gate regions along the second direction X.

[0076] In one embodiment, reference Figure 1 , Figure 2 , Figure 3 and Figure 4For adjacent gate structures 150 , the doped regions 140 of the epitaxial protection layer 190 surrounding the sidewalls and bottom of one gate structure 150 are spaced apart from the doped regions 140 of the epitaxial protection layer 190 surrounding the sidewalls and bottom of another gate structure 150 .

[0077] In one embodiment, reference Figure 3 and Figure 4 For adjacent gate structures 150 , the doped region 140 of the epitaxial protection layer 190 surrounding the sidewall of one gate structure 150 and the doped region 140 of the epitaxial protection layer 190 surrounding the sidewall of another gate structure 150 are both located on the same side of the corresponding gate region along the second direction X.

[0078] In this embodiment, reference Figure 1 The trench MOSFET structure also includes: an isolation layer 180, which is located on the side surface of the gate structure 150 away from the semiconductor substrate layer 100, and the isolation layer 180 also covers a portion of the source region 130 on the side of the gate structure 150; a drain metal layer 160, which is located on the side surface of the semiconductor substrate layer 100 away from the drift layer 110.

[0079] Another embodiment of the present application further provides a trench MOSFET structure, referring to Figure 5 , this embodiment and Figure 1 The difference between the corresponding embodiments is that: for the gate regions adjacent to each other along the second direction X, the doped region 140 of the epitaxial protection layer 190 surrounding the side wall of one gate region is located on one side of the corresponding gate region along the second direction X, and the doped region 140 of the epitaxial protection layer 190 surrounding the side wall of the other gate region is located on the other side of the corresponding gate region along the second direction X.

[0080] Combined with reference Figure 5 and Figure 6 The gate structure 150 includes a plurality of gate regions arranged at intervals along a first direction Y; the epitaxial protection layer 190 on the sidewalls and the bottom of a gate structure 150 is surrounded by a plurality of doped regions 140 spaced apart along the first direction Y; wherein, for two adjacent doped regions 140 along the first direction Y, one doped region 140 is located on one side of one gate region along the second direction X, and the other doped region 140 is located on the other side of the other gate region along the second direction X.

[0081] Combined with reference Figure 5 and Figure 7 The gate structure 150 includes a plurality of gate regions arranged at intervals along a first direction Y; the epitaxial protection layer 190 on the sidewalls and bottom of a gate structure 150 is surrounded by a plurality of doped regions 140 spaced apart along the first direction Y; wherein, for two adjacent doped regions 140 along the first direction Y, the two doped regions 140 are located on the same side of different gate regions along the second direction X.

[0082] Combined with reference Figure 5 and Figure 8 The gate structure 150 includes a gate region; the orthographic projection pattern of the doped region 140 on the semiconductor substrate layer 100 is in the shape of a long strip.

[0083] Combined with reference Figures 5 to 8 For adjacent gate structures 150 , the doped regions 140 of the epitaxial protection layer 190 surrounding the sidewalls and bottom of one gate structure 150 are spaced apart from the doped regions 140 of the epitaxial protection layer 190 surrounding the sidewalls and bottom of another gate structure 150 .

[0084] The contents of this embodiment that are the same as those of the previous embodiment will not be described in detail.

[0085] Another embodiment of the present application further provides a trench MOSFET structure, referring to Fig. 9 , this embodiment and Figure 5 The difference between the corresponding embodiments is that for every two adjacent gate regions along the second direction X, the doped region 140 of the epitaxial protection layer 190 surrounding the sidewall of one gate region and the doped region 140 of the epitaxial protection layer 190 surrounding the sidewall of another gate region are connected together.

[0086] refer to Fig. 9 For gate regions adjacent to each other along the second direction X, the doped region 140 of the epitaxial protection layer 190 surrounding the side wall of one gate region is located on one side of the corresponding gate region along the second direction X, and the doped region 140 of the epitaxial protection layer 190 surrounding the side wall of another gate region is located on the other side of the corresponding gate region along the second direction X.

[0087] refer to Fig.10 The gate structure 150 includes a plurality of gate regions arranged at intervals along a first direction Y; the epitaxial protection layer 190 on the sidewalls and bottom of a gate structure 150 is surrounded by a plurality of doped regions 140 spaced apart along the first direction Y; wherein, for two adjacent doped regions 140 along the first direction Y, the two doped regions 140 are located on the same side of different gate regions along the second direction X.

[0088] refer to Fig.11 The gate structure 150 includes a gate region; the orthographic projection pattern of the doped region 140 on the semiconductor substrate layer 100 is in the shape of a long strip.

[0089] The contents of this embodiment that are the same as those of the previous embodiment will not be described in detail.

[0090] The present application also provides a method for preparing a trench MOSFET structure, comprising forming a drift layer on one side of a semiconductor substrate layer; forming a gate structure extending along a first direction in the drift layer, the gate structure including a gate region; forming an epitaxial protection layer in the drift layer, the epitaxial protection layer extending along the first direction, the conductivity type of the epitaxial protection layer being the same as that of the drift layer, and the doping concentration of the epitaxial protection layer being greater than the doping concentration of the drift layer; forming a well region in the drift layer; forming a doped region in the drift layer; the epitaxial protection layer surrounds the sidewalls and bottom surface of the gate structure; the well region is located at the gate The structure and the epitaxial protection layer are arranged on both sides along a second direction, and the second direction is perpendicular to the first direction; the doped region is located on the side of the well region facing the semiconductor substrate layer, and any one of the doped regions surrounds the epitaxial protection layer on one side of the gate region along the second direction and a portion of the epitaxial protection layer corresponding to the gate region facing the semiconductor substrate layer, and the doped region exposes the epitaxial protection layer on the other side of the gate region along the second direction and another portion of the epitaxial protection layer corresponding to the gate region facing the semiconductor substrate layer, and the conductivity type of the doped region is opposite to the conductivity type of the epitaxial protection layer.

[0091] In this embodiment, the step of forming the gate structure includes: forming a groove in the drift layer; forming the gate structure in the groove; wherein the step of forming the epitaxial protection layer includes: before forming the gate structure in the groove, forming the epitaxial protection layer on the inner wall surface of the groove; wherein the step of forming the doped region includes: before forming the epitaxial protection layer on the inner wall surface of the groove, forming the doped region in a portion of the drift layer at the bottom of the groove and in the drift layer on the side of the groove.

[0092] The following reference Figures 12 to 19 The preparation process of trench MOSFET structure is described in detail.

[0093] refer to Fig.12 , a drift layer 110 is formed on one side of the semiconductor substrate layer 100 .

[0094] The description of the semiconductor substrate layer and the drift layer 110 refers to the aforementioned embodiment and will not be described in detail.

[0095] refer to Fig.13 , an initial well region 1200 is formed in a partial thickness of the drift layer 110 ; and an initial source region 1300 is formed in a portion of the initial well region 1200 .

[0096] The conductivity type of the initial well region 1200 is opposite to that of the drift layer 110 . The conductivity type of the initial source region 1300 is the same as that of the drift layer 110 , and the doping concentration of the initial source region 1300 is greater than that of the drift layer 110 .

[0097] The surface of the initial source region 1300 facing the semiconductor substrate layer 100 is farther away from the semiconductor substrate layer 100 than the surface of the initial well region 1200 facing the semiconductor substrate layer 100 .

[0098] The process of forming the initial well region 1200 includes an ion implantation process. The process of forming the initial source region 1300 includes an ion implantation process.

[0099] refer to Fig.14 , a groove G1 is formed in the drift layer 110 .

[0100] The groove G1 extends from a surface of the drift layer 110 facing away from the semiconductor substrate 100 to a portion of the thickness of the drift layer 110 .

[0101] Specifically, a groove G1 is formed in the initial well region 1200 , the initial source region 1300 , and a portion of the drift layer 110 at the bottom of the initial well region 1200 . The initial well region 1200 on both sides of the groove G1 forms the well region 120 . The initial source region 1300 on both sides of the groove G1 forms the first sub-source region 131 .

[0102] The process of forming the groove G1 includes an etching process.

[0103] It should be noted that before forming the groove G1, a first mask layer Y covering part of the initial source region 1300 and the initial well region 1200 can be formed, the first mask layer Y exposes part of the initial source region 1300, and then the initial well region 1200, the initial source region 1300, and part of the drift layer 110 at the bottom of the initial well region 1200 are etched using the first mask layer Y as a mask to form the groove G1.

[0104] refer to Fig.15 , forming a doped region 140.

[0105] The step of forming the doping region 140 includes forming the doping region 140 in a portion of the drift layer 110 at the bottom of the groove G1 and in the drift layer 110 at the side of the groove G1. The process of forming the doping region 140 includes an ion implantation process.

[0106] Specifically, a first filling body can be formed in a partial area of ​​the groove G1, the first filling body covers one side wall of the groove G1 along the second direction X and a portion of the bottom surface of the groove G1, and the first filling body exposes the other side wall of the groove G1 along the second direction X and a portion of the bottom surface of the groove G1; a doping region 140 is formed using the first filling body and the first mask layer Y as a mask; after the doping region 140 is formed using the first filling body and the first mask layer Y as a mask, the first filling body and the first mask layer Y are removed.

[0107] It should be noted that, in this embodiment, for adjacent gate structures 150, the doped regions 140 of the epitaxial protection layer 190 surrounding the sidewalls and bottom of one gate structure 150 are spaced from the doped regions 140 of the epitaxial protection layer 190 surrounding the sidewalls and bottom of another gate structure 150. For the specific different position settings of the doped regions 140, refer to the description of the aforementioned embodiment and will not be described in detail.

[0108] refer to Fig.16 , forming an epitaxial protection layer 190.

[0109] The step of forming the epitaxial protection layer 190 includes: forming the epitaxial protection layer 190 on the inner wall surface of the groove G1 .

[0110] The process of forming the epitaxial protection layer 190 includes an epitaxial process, so that the morphology of the epitaxial protection layer 190 can be more accurately controlled, and the epitaxial protection layer 190 is formed inside the trench G1 without increasing the lateral size of the cell.

[0111] In this embodiment, after the doping region 140 is formed in a portion of the drift layer 110 at the bottom of the groove G1 and in the drift layer 110 at the side of the groove G1 , an epitaxial protection layer 190 is formed on the inner wall surface of the groove G1 .

[0112] refer to Fig.17 A channel region 170 is formed in the epitaxial protection layer 190 on the side wall surface of the groove G1, and a side surface of the channel region 170 facing away from the semiconductor substrate layer 100 is separated from a side surface of the drift layer 110 facing away from the semiconductor substrate layer 100, and a side surface of the channel region 170 facing the semiconductor substrate layer 100 is separated from the epitaxial protection layer 190 on the bottom wall of the groove G1.

[0113] The process of forming the channel region 170 includes an ion implantation process.

[0114] In one embodiment, the ion implantation process used to form the channel region 170 has an implantation direction perpendicular to the upper surface of the semiconductor substrate layer 100 .

[0115] The doping concentration of the channel region 170 is less than the doping concentration of the well region 120 and less than the doping concentration of the first sub-source region 131. Since the doping concentration of the channel region 170 is relatively small, the conductivity type of the first sub-source region 131 will not be changed. Since the conductivity type of the ions injected into the channel region 170 is the same as the conductivity type of the ions in the well region 120, the conductivity type of the well region 120 will not be changed.

[0116] It should be noted that before forming the channel region 170 in the epitaxial protection layer 190 on the side wall surface of the groove G1, a second filling body can also be formed in the groove G1; the channel region 170 is formed using the second filling body as a mask; after forming the channel region 170 using the second filling body as a mask, the second filling body is removed.

[0117] refer to Fig.18 , a gate structure 150 extending along the first direction Y is formed in the drift layer 110 , specifically, the gate structure 150 is formed in the groove G1 .

[0118] In this embodiment, after the epitaxial protection layer 190 is formed on the inner wall surface of the groove G1 , the gate structure 150 is formed in the groove G1 .

[0119] In this embodiment, after the channel region 170 is formed, the gate structure 150 is formed in the groove G1 .

[0120] The gate structure 150 includes a gate dielectric layer 151 and a gate electrode layer 152. The positions and materials of the gate dielectric layer 151 and the gate electrode layer 152 refer to the above-mentioned embodiments.

[0121] Continue to refer Fig.18 A second sub-source region 132 is formed in the epitaxial protection layer 190 on the side of the channel region 170 away from the semiconductor substrate layer 100 , and the second sub-source region 132 and the first sub-source region 131 constitute the source region 130 .

[0122] It should be noted that in other embodiments, the initial source region 1300 may not be formed before the groove G1 is formed; after the epitaxial protection layer 190 is formed, the source region 130 is formed in part of the well region 120 and in the epitaxial protection layer 190 on the side of the channel region 170 away from the semiconductor substrate layer 100 .

[0123] refer to Fig.19 An isolation layer 180 is formed on a surface of the gate structure 150 that is away from the semiconductor substrate layer 100 ; and a drain metal layer 160 is formed on a surface of the semiconductor substrate layer 100 that is away from the drift layer 110 .

[0124] The following reference Figure 20 to Figure 24 Another preparation process of trench MOSFET structure is introduced in detail.

[0125] refer to Fig. 20 , a drift layer 110 is formed on one side of the semiconductor substrate layer 100 .

[0126] refer to Fig.21 , an initial well region 1200 is formed in a partial thickness of the drift layer 110 ; and an initial source region 1300 is formed in a portion of the initial well region 1200 .

[0127] The description of the initial well region 1200 and the initial source region 1300 refers to the description of the previous embodiment.

[0128] refer to Fig. 22 , a groove G1 is formed in the drift layer 110. The groove G1 extends from a surface of the drift layer 110 facing away from the semiconductor substrate 100 to a portion of the thickness of the drift layer 110.

[0129] Specifically, a groove G1 is formed in the initial well region 1200 , the initial source region 1300 , and a portion of the drift layer 110 at the bottom of the initial well region 1200 . The initial well region 1200 on both sides of the groove G1 forms the well region 120 . The initial source region 1300 on both sides of the groove G1 forms the first sub-source region 131 .

[0130] The process of forming the groove G1 includes an etching process.

[0131] It should be noted that before forming the groove G1, a first mask layer Y covering part of the initial source region 1300 and the initial well region 1200 can be formed, the first mask layer Y exposes part of the initial source region 1300, and then the initial well region 1200, the initial source region 1300, and part of the drift layer 110 at the bottom of the initial well region 1200 are etched using the first mask layer Y as a mask to form the groove G1.

[0132] The plurality of grooves G1 are arranged along the second direction X at intervals.

[0133] refer to Fig.23 , forming a doped region 140.

[0134] The step of forming the doping region 140 includes forming the doping region 140 in a portion of the drift layer 110 at the bottom of the groove G1 and in the drift layer 110 at the side of the groove G1. The process of forming the doping region 140 includes an ion implantation process.

[0135] Specifically, a first filling body can be formed in a partial area of ​​the groove G1, the first filling body covers one side wall of the groove G1 along the second direction X and a portion of the bottom surface of the groove G1, and the first filling body exposes the other side wall of the groove G1 along the second direction X and a portion of the bottom surface of the groove G1; a portion of the first mask layer Y is removed to expose a portion of the drift layer 110 between adjacent grooves G1; then, a doped region 140 is formed using the first filling body and the first mask layer Y as a mask; after the doped region 140 is formed using the first filling body and the first mask layer Y as a mask, the first filling body and the first mask layer Y are removed.

[0136] It should be noted that, in this embodiment, for every two adjacent gate regions along the second direction X, the doped region 140 of the epitaxial protection layer 190 surrounding the sidewall of one gate region and the doped region 140 of the epitaxial protection layer 190 surrounding the sidewall of another gate region are connected together. The specific different position settings of the doped region 140 refer to the description of the aforementioned embodiment and will not be described in detail.

[0137] refer to Fig.24 , forming an epitaxial protection layer 190; forming a channel region 170 in the epitaxial protection layer 190 on the side wall surface of the groove G1, a side surface of the channel region 170 away from the semiconductor substrate layer 100 is spaced from a side surface of the drift layer 110 away from the semiconductor substrate layer 100, and a side surface of the channel region 170 facing the semiconductor substrate layer 100 is spaced from the epitaxial protection layer 190 on the bottom wall of the groove G1; forming a gate structure 150 extending along the first direction Y in the drift layer 110, specifically, forming the gate structure 150 in the groove G1.

[0138] In this embodiment, the method further includes forming a second sub-source region in the epitaxial protection layer 190 on the side of the channel region 170 away from the semiconductor substrate layer 100 , and the second sub-source region and the first sub-source region 131 constitute the source region 130 .

[0139] It should be noted that in other embodiments, the initial source region 1300 may not be formed before the groove G1 is formed; after the epitaxial protection layer 190 is formed, the source region 130 is formed in part of the well region 120 and in the epitaxial protection layer 190 on the side of the channel region 170 away from the semiconductor substrate layer 100 .

[0140] In this embodiment, the method further includes: forming an isolation layer 180 on a surface of the gate structure 150 that is away from the semiconductor substrate layer 100 ; and forming a drain metal layer 160 on a surface of the semiconductor substrate layer 100 that is away from the drift layer 110 .

[0141] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A trench MOSFET structure, characterized in that: include: Semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; A gate structure located in the drift layer and extending along a first direction, the gate structure comprising a gate region; an epitaxial protection layer extending along the first direction and surrounding the sidewall and bottom surface of the gate structure, wherein the conductivity type of the epitaxial protection layer is the same as the conductivity type of the drift layer, and the doping concentration of the epitaxial protection layer is greater than the doping concentration of the drift layer; A well region located in the drift layer on both sides of the gate structure and the epitaxial protection layer along a second direction, wherein the second direction is perpendicular to the first direction; The doped regions are located in the drift layer on the side of the well region facing the semiconductor substrate layer, any one of the doped regions surrounds the epitaxial protection layer on one side of the gate region along the second direction and a portion of the epitaxial protection layer corresponding to the gate region on the side facing the semiconductor substrate layer, and the doped regions expose the epitaxial protection layer on the other side of the gate region along the second direction and another portion of the epitaxial protection layer corresponding to the gate region on the side facing the semiconductor substrate layer, and the conductivity type of the doped regions is opposite to the conductivity type of the epitaxial protection layer.

2. The trench MOSFET structure according to claim 1, characterized in that: The doped region is in contact with the well region.

3. The trench MOSFET structure according to claim 1, characterized in that: Also includes: A channel region is located in the epitaxial protection layer of the side wall of the gate structure, a surface of the channel region facing away from the semiconductor substrate layer is spaced from a surface of the drift layer facing away from the semiconductor substrate layer, and a surface of the channel region facing the semiconductor substrate layer is spaced from a surface of the gate structure facing the semiconductor substrate layer.

4. The trench MOSFET structure according to claim 3, characterized in that: Also includes: The source region is located in a partial area of ​​the well region and in the epitaxial protection layer on a side of the channel region away from the semiconductor substrate layer.

5. The trench MOSFET structure according to claim 1, characterized in that: The gate structure includes a gate region; the orthographic projection pattern of the doped region on the semiconductor substrate layer is in the shape of a long strip.

6. The trench MOSFET structure according to claim 1, characterized in that: The gate structure comprises a plurality of gate regions spaced apart along the first direction; an epitaxial protection layer on the sidewall and bottom of the gate structure is surrounded by the plurality of doped regions spaced apart along the first direction; Among them, for the two doping regions adjacent to each other along the first direction, one of the doping regions is located on one side of one of the gate regions along the second direction, and the other of the doping regions is located on the other side of the other of the gate regions along the second direction.

7. The trench MOSFET structure according to claim 1, characterized in that: The gate structure comprises a plurality of gate regions spaced apart along the first direction; an epitaxial protection layer on the sidewall and bottom of the gate structure is surrounded by the plurality of doped regions spaced apart along the first direction; Wherein, for the two doping regions adjacent to each other along the first direction, the two doping regions are located on the same side of different gate regions along the second direction.

8. The trench MOSFET structure according to claim 1, 5, 6 or 7, characterized in that: For the adjacent gate structures, the doped region of the epitaxial protection layer surrounding the sidewall and bottom of one gate structure is spaced apart from the doped region of the epitaxial protection layer surrounding the sidewall and bottom of another gate structure.

9. The trench MOSFET structure according to claim 5 or 7, characterized in that: For the adjacent gate structures, the doped region of the epitaxial protection layer surrounding the sidewall of one gate structure and the doped region of the epitaxial protection layer surrounding the sidewall of another gate structure are both located on the same side of the corresponding gate region along the second direction.

10. The trench MOSFET structure according to claim 5 or 7, characterized in that: For the gate regions adjacent to each other along the second direction, the doped region of the epitaxial protection layer surrounding the side wall of one gate region is located on one side of the corresponding gate region along the second direction, and the doped region of the epitaxial protection layer surrounding the side wall of another gate region is located on the other side of the corresponding gate region along the second direction.

11. The trench MOSFET structure according to claim 10, characterized in that: For every two adjacent gate regions along the second direction, the doped region of the epitaxial protection layer surrounding the side wall of one gate region and the doped region of the epitaxial protection layer surrounding the side wall of another gate region are connected together.

12. The trench MOSFET structure according to claim 1, characterized in that: The doping concentration of the epitaxial protection layer is 3 to 8 times the doping concentration of the drift layer.

13. The trench MOSFET structure according to claim 1, characterized in that: The doping concentration of the doping region is lower than the doping concentration of the well region.

14. A method for forming a trench MOSFET structure as claimed in any one of claims 1 to 13, characterized in that: include: forming a drift layer on one side of the semiconductor substrate layer; forming a gate structure extending along a first direction in the drift layer, wherein the gate structure includes a gate region; forming an epitaxial protection layer in the drift layer, wherein the epitaxial protection layer extends along the first direction, the conductivity type of the epitaxial protection layer is the same as the conductivity type of the drift layer, and the doping concentration of the epitaxial protection layer is greater than the doping concentration of the drift layer; forming a well region in the drift layer; forming a doped region in the drift layer; The epitaxial protection layer surrounds the side walls and bottom surface of the gate structure; the well region is located on both sides of the gate structure and the epitaxial protection layer along a second direction, and the second direction is perpendicular to the first direction; the doped region is located on the side of the well region facing the semiconductor substrate layer, and any one of the doped regions surrounds the epitaxial protection layer on one side of the gate region along the second direction and a portion of the epitaxial protection layer corresponding to the side of the gate region facing the semiconductor substrate layer, and the doped region exposes the epitaxial protection layer on the other side of the gate region along the second direction and another portion of the epitaxial protection layer corresponding to the side of the gate region facing the semiconductor substrate layer, and the conductivity type of the doped region is opposite to that of the epitaxial protection layer.

15. The method for preparing a trench MOSFET structure according to claim 14, characterized in that: The steps of forming the gate structure include: forming a groove in the drift layer; forming the gate structure in the groove; Wherein, the step of forming the epitaxial protection layer comprises: before forming the gate structure in the groove, forming the epitaxial protection layer on the inner wall surface of the groove; The step of forming the doped region includes: before forming the epitaxial protection layer on the inner wall surface of the groove, forming the doped region in a portion of the drift layer at the bottom of the groove and in the drift layer at the side of the groove.

16. The method for preparing a trench MOSFET structure according to claim 15, characterized in that: Also includes: A channel region is formed in the epitaxial protection layer on the side wall surface of the groove, a side surface of the channel region facing away from the semiconductor substrate layer is spaced from a side surface of the drift layer facing away from the semiconductor substrate layer, and a side surface of the channel region facing the semiconductor substrate layer is spaced from the epitaxial protection layer on the bottom wall of the groove.

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