Shield gate gallium oxide MOSFET device based on heterojunction and preparation method thereof

Abstract

The invention relates to a shield gate gallium oxide MOSFET device based on heterojunction and a preparation method thereof. The device comprises an n-type gallium oxide substrate layer, an n-type gallium oxide epitaxial drift layer, an n-type current expansion layer, a p-type nickel oxide base region, an n +-type epitaxial source region and a shield gate structure. Wherein the n-type gallium oxide substrate layer, the n-type gallium oxide epitaxial drift layer, the n-type current expansion layer, the p-type nickel oxide base region and the n +-type epitaxial source region are sequentially stacked from bottom to top; the n-type current expansion layer, the p-type nickel oxide base region and the n +-type epitaxial source region form a heterojunction; and the shield gate structure is arranged in a region extending downwards from the top of the n + type epitaxial source region to the interior of the n type gallium oxide epitaxial drift layer. According to the device, the p-n heterojunction MOSFET is constructed by adopting the p-type material nickel oxide and gallium oxide, the key difficult problem that gallium oxide lacks effective p-type doping is effectively solved, and the device has the advantages of being good in insulating property, low in on-resistance and high in current switching ratio.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to a shielded-gate gallium oxide MOSFET device based on a heterojunction and a preparation method thereof. Background Art

[0002] Gallium oxide (β-Ga2O3) has attracted widespread attention due to its excellent performance. It has a bandgap width far exceeding that of silicon carbide (SiC) and gallium nitride (GaN), an extremely high theoretical breakdown electric field, a high electron saturation drift velocity, a BFOM value that is nearly four times that of GaN and ten times that of SiC. These excellent properties make β-Ga2O3 devices likely to increase the switching speed of devices and shorten the reverse recovery time of rectifier devices, and have great application potential in high-voltage power and radio frequency fields.

[0003] At present, in the application of gallium oxide MOSFET devices, it is difficult to achieve p-type doping of gallium oxide materials, resulting in poor device insulation performance, large leakage current, and low switching ratio, making it difficult to give full play to the advantages of gallium oxide materials. Therefore, it is urgent to develop a new type of gallium oxide MOSFET device structure to achieve a new generation of high-performance gallium oxide power electronic devices with device preparation process compatible with mainstream processes and superior device performance. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a shielded gate gallium oxide MOSFET device based on heterojunction and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, the present invention provides a shielded gate gallium oxide MOSFET device based on a heterojunction, comprising: an n-type gallium oxide substrate layer, an n-type gallium oxide epitaxial drift layer, an n-type current spreading layer, a p-type nickel oxide base region, an n+ type epitaxial source region, and a shielded gate structure; wherein the n-type gallium oxide substrate layer, the n-type gallium oxide epitaxial drift layer, the n-type current spreading layer, the p-type nickel oxide base region, and the n+ type epitaxial source region are stacked in sequence from bottom to top; the n-type current spreading layer, the p-type nickel oxide base region, and the n+ type epitaxial source region constitute a heterojunction; and the shielded gate structure is arranged in a region extending downward from the top of the n+ type epitaxial source region to the inside of the n-type gallium oxide epitaxial drift layer.

[0006] In some embodiments, a gate groove is provided in the heterojunction and the n-type gallium oxide epitaxial drift layer, and the gate groove extends downward from the top of the n+ type epitaxial source region to the inside of the n-type gallium oxide epitaxial drift layer; the shielding gate structure includes: a shielding layer, a gate dielectric layer and a gate layer; the shielding layer is located at the bottom of the gate groove; the gate dielectric layer is provided on the side wall of the gate groove and the upper surface of the shielding layer; the gate layer is filled in the gate groove provided with the gate dielectric layer, and the top of the gate layer is flush with the top of the gate groove.

[0007] In some embodiments, the p-type nickel oxide base region and the n+ type epitaxial source region form a stepped structure; the heterojunction-based shielded gate gallium oxide MOSFET device further includes: a p+ injection source region, an isolation layer, a source metal layer and a drain metal layer; wherein the p+ injection source region is arranged on the stepped structure, and the top of the p+ injection source region is flush with the top of the p-type nickel oxide base region; the isolation layer is located on the upper surface of the shielding gate structure and part of the upper surface of the n+ type epitaxial source region; the source metal layer covers the upper surface of the n+ type epitaxial source region, the upper surface of the isolation layer and the upper surface of the p+ injection source region; the drain metal layer is located on the lower surface of the n-type gallium oxide substrate layer.

[0008] In some embodiments, the thickness of the p-type nickel oxide base region ranges from 300 nm to 700 nm.

[0009] In some embodiments, the n+ type epitaxial source region is a β-Ga2O3 material doped with Si element, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 The thickness of the n+ type epitaxial source region ranges from 200nm to 300nm.

[0010] In some embodiments, the p+ injection source region is a β-Ga2O3 material doped with Li, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 , the junction depth thickness is in the range of 100nm to 200nm.

[0011] In some embodiments, the gate trench has a depth ranging from 2 μm to 5 μm.

[0012] In a second aspect, the present invention provides a method for preparing a shielded gate gallium oxide MOSFET device based on a heterojunction, the preparation method being used to prepare the shielded gate gallium oxide MOSFET device based on a heterojunction described in the first aspect, the preparation method comprising: epitaxially growing an n-type gallium oxide epitaxial drift layer on the upper surface of an n-type gallium oxide substrate layer; preparing an n-type current spreading layer on the upper surface of the n-type gallium oxide epitaxial drift layer; preparing a p-type nickel oxide base region on the upper surface of the n-type current spreading layer; preparing an n+ type epitaxial source region on the upper surface of the p-type nickel oxide base region, and etching the upper surface of the n+ type epitaxial source region using a photolithography process, penetrating the n-type current spreading layer and the p-type nickel oxide base region, until extending into the interior of the n-type gallium oxide epitaxial drift layer to form a gate groove; growing a shielded gate structure in the gate groove, wherein the shielded gate structure comprises a shielding layer, a gate dielectric layer and a gate layer stacked from bottom to top.

[0013] In some embodiments, before growing the shielding gate structure in the gate trench, the preparation method further includes: etching both sides of the n+ type epitaxial source region using a dry etching process to expose a portion of the surface of the p-type nickel oxide base region to form a stepped structure; and preparing a p+ injection source region on the stepped structure.

[0014] In some embodiments, the preparation method further includes: preparing an isolation layer on the upper surface of the n+ type epitaxial source region and the upper surface of the shielding gate structure; preparing a source metal layer on the upper surface of the n+ type epitaxial source region, the upper surface of the isolation layer and the upper surface of the p+ injection source region; and preparing a drain metal layer on the lower surface of the n-type gallium oxide substrate layer.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] Aiming at the problem that it is difficult to achieve p-type doping in existing gallium oxide MOSFET devices, resulting in poor device insulation performance, large leakage current, low switching ratio, and difficulty in giving full play to the advantages of gallium oxide materials, the present invention provides a shielded gate gallium oxide MOSFET device based on heterojunction and a preparation method thereof. The device comprises a heterojunction consisting of an n-type current spreading layer, a p-type nickel oxide base region and an n+ type epitaxial source region. By using p-type nickel oxide and gallium oxide to construct a pn heterojunction MOSFET, the key difficulty of gallium oxide lacking effective p-type doping can be effectively overcome, and the device has the advantages of good insulation performance, low on-resistance and high current switching ratio. In addition, the shielded gate adopts a trench gate structure, which can turn off the device when the gate bias is zero, reduce static power consumption, and increase the current switching ratio of the device. At the same time, an n-type current spreading layer is provided, which can effectively reduce the on-resistance of the device. In addition, by using the shielded gate structure, the electric field at the gate dielectric of the device is modulated, the electric field concentration phenomenon is effectively suppressed, and the risk of device breakdown and damage is reduced. The shielded gate gallium oxide MOSFET device based on heterojunction and the preparation method thereof provided by the present invention can help realize high-efficiency, high-power and commercially scalable gallium oxide microelectronic systems and promote their practical application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of a shielded gate gallium oxide MOSFET device based on a heterojunction provided by an embodiment of the present invention;

[0018] Figure 2 It is a schematic flow chart of a method for preparing a shielded-gate gallium oxide MOSFET device based on a heterojunction provided in an embodiment of the present invention.

[0019] Reference numerals:

[0020] 1: n-type gallium oxide substrate layer; 2: n-type gallium oxide epitaxial drift layer; 3: n-type current spreading layer; 4: p-type nickel oxide base region; 5: n+ type epitaxial source region; 6: shielded gate structure; 7: p+ injection source region; 8: isolation layer; 9: source metal layer; 10: drain metal layer; 61: shielding layer; 62: gate dielectric layer; 63: gate layer. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0022] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0023] The shielded gate gallium oxide MOSFET device based on heterojunction and the preparation method thereof provided by the present invention are now described in detail with reference to the accompanying drawings.

[0024] Figure 1 Schematic diagram of the structure of a shielded-gate gallium oxide MOSFET device based on a heterojunction provided by an embodiment of the present invention. Figure 1 As shown, the device includes: an n-type gallium oxide substrate layer 1, an n-type gallium oxide epitaxial drift layer 2, an n-type current spreading layer 3, a p-type nickel oxide base region 4, an n+ type epitaxial source region 5, and a shielding gate structure 6; wherein the n-type gallium oxide substrate layer 1, the n-type gallium oxide epitaxial drift layer 2, the n-type current spreading layer 3, the p-type nickel oxide base region 4 and the n+ type epitaxial source region 5 are stacked in sequence from bottom to top; the n-type current spreading layer 3, the p-type nickel oxide base region 4 and the n+ type epitaxial source region 5 form a heterojunction; the shielding gate structure 6 is arranged in a region extending downward from the top of the n+ type epitaxial source region 5 to the inside of the n-type gallium oxide epitaxial drift layer 2.

[0025] In a possible implementation, the material of the n-type gallium oxide substrate layer 1 is a β-Ga2O3 material doped with Sn element, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 , preferably 5×10 18 cm -3 The thickness ranges from 90 μm to 1500 μm, preferably 200 μm. And the n-type gallium oxide epitaxial drift layer 2 is a β-Ga2O3 material doped with SiCl4, and the doping concentration ranges from 4×10 15 cm -3 ~5×10 16 cm -3 , preferably 1.5×10 18 cm -3 The thickness ranges from 10 μm to 500 μm, preferably 10 μm. Here, the doping concentration of the n-type gallium oxide substrate layer 1 is greater than the doping concentration of the n-type gallium oxide epitaxial drift layer 2 .

[0026] In a possible implementation, the n-type current spreading layer 3 is a β-Ga2O3 material doped with Si, and the doping concentration range is 5×10 16 cm -3 ~1×10 18 cm -3 , preferably 5×10 16 cm -3 The thickness range is 300 μm to 700 μm, preferably 300 μm. The thickness range of the p-type nickel oxide base region 4 is 300 nm to 700 nm, preferably 300 nm. The target material of the p-type nickel oxide base region 4 is a high-purity 99.99% NiO ceramic with a hole concentration of 1×10 17 cm -3 ~1×10 19 cm -3 The n+ type epitaxial source region 5 is a β-Ga2O3 material doped with Si element, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 , preferably 3×10 18 cm -3 , and the thickness of the n+ type epitaxial source region 5 is in the range of 200nm to 300nm, preferably 200nm.

[0027] Here, by using the n-type current spreading layer 3, the p-type nickel oxide base region 4 and the n+ type epitaxial source region 5 to form a heterojunction, p-type doping of the gallium oxide material can be achieved, which has the advantages of good insulation performance and greatly reduced leakage current. In addition, the use of the n-type current spreading layer 3 can effectively reduce the on-resistance.

[0028] Here, a gate groove is arranged in the heterojunction and the n-type gallium oxide epitaxial drift layer 2, and the gate groove extends downward from the top of the n+ type epitaxial source region 5 to the inside of the n-type gallium oxide epitaxial drift layer 2; the shielding gate structure 6 includes: a shielding layer 61, a gate dielectric layer 62 and a gate layer 63; the shielding layer 61 is located at the bottom of the gate groove; the gate dielectric layer 62 is arranged on the side wall of the gate groove and the upper surface of the shielding layer 61; the gate layer 63 is filled in the gate groove provided with the gate dielectric layer 62, and the top of the gate layer 63 is flush with the top of the gate groove.

[0029] Here, the bottom of the gate groove transitions in an arc, and the gate groove penetrates the n-type current spreading layer 3, the p-type nickel oxide base region 4, the n+ type epitaxial source region 5, and extends into the n-type gallium oxide epitaxial drift layer 2. The depth of the gate groove ranges from 2 μm to 5 μm, preferably 2 μm.

[0030] In a possible implementation, the material of the shielding layer 61 is a β-Ga2O3 material doped with N element, and the doping concentration range is 5×10 18 cm-3 ~5×10 19 cm -3 , preferably 5×10 18 cm -3 The junction depth of the shielding layer 61 is in the range of 100 nm to 200 nm, preferably 200 nm; the wall thickness of the gate dielectric layer 62 forming the groove is in the range of 20 nm to 100 nm, preferably 30 nm.

[0031] In a possible implementation, the gate layer 63 completely fills the inside of the groove, and its thickness is about 2 μm to 5 μm, preferably 2 μm. Here, the material of the gate layer 63 is polysilicon.

[0032] By adopting the gate groove design, the switching ratio of the gallium oxide MOSFET device is increased, and the device can be turned off when the gate voltage is zero, thereby reducing static power consumption. In addition, the shielding layer 61 is arranged at the bottom of the gate groove, which can effectively modulate the electric field at the corner of the bottom of the gate groove, and suppress the electric field concentration phenomenon that easily occurs in the gate dielectric layer at the corner below the trench gate in the conventional device structure.

[0033] Here, the p-type nickel oxide base region 4 and the n+ type epitaxial source region 5 form a stepped structure; the shielded gate gallium oxide MOSFET device based on the heterojunction also includes: a p+ injection source region 7, an isolation layer 8, a source metal layer 9 and a drain metal layer 10; wherein the p+ injection source region 7 is arranged on the stepped structure, and the top of the p+ injection source region 7 is flush with the top of the p-type nickel oxide base region 4; the isolation layer 8 is located on the upper surface of the shielding gate structure 6 and part of the upper surface of the n+ type epitaxial source region 5; the source metal layer 9 covers the upper surface of the n+ type epitaxial source region 5, the upper surface of the isolation layer 8 and the upper surface of the p+ injection source region 7; the drain metal layer 10 is located on the lower surface of the n-type gallium oxide substrate layer 1.

[0034] In a possible implementation, the material of the p+ injection source region 7 is a β-Ga2O3 material doped with Li, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 , preferably 3×10 18 cm -3 The junction depth of the p+ implanted source region 7 is in the range of 100nm to 200nm, preferably 150nm. The material of the isolation layer 8 is one of SiO2 or Si3N4, and the corresponding thickness range is 100nm to 800nm, preferably 300nm.

[0035] In a possible implementation, the source metal layer 9 and the drain metal layer 10 are both Ti / Au stacked layers, wherein, in the source metal layer 9, the stacking thickness of Ti is 28nm~32nm, preferably 30nm; the stacking thickness of Au is 98nm~102nm, preferably 100nm; in the drain metal layer 10, the stacking thickness of Ti is 48nm~52nm, preferably 50nm; the stacking thickness of Au is 98nm~102nm, preferably 100nm.

[0036] By vertically designing the gate layer 63 , the source metal layer 9 and the drain metal layer 10 , a smaller size and a higher power density can be achieved.

[0037] The above is a schematic diagram of the structure of a shielded gate gallium oxide MOSFET device based on a heterojunction provided in an embodiment of the present invention. Corresponding to the device, the present invention also provides a method for preparing a shielded gate gallium oxide MOSFET device based on a heterojunction. Figure 2 It is a schematic flow chart of a method for preparing a shielded-gate gallium oxide MOSFET device based on a heterojunction provided in an embodiment of the present invention. Figure 2 The 13 small figures include arrows that indicate the order of device preparation. It should be understood that for the sake of simplicity and to facilitate the clear identification of the newly added parts, the components that have appeared in the previous small figures in each small figure are not numbered, and only the newly added components in the current small figure are numbered. Figure 2 , the preparation method is described in detail.

[0038] like Figure 2 As shown, the preparation method includes: epitaxially growing an n-type gallium oxide epitaxial drift layer 2 on the upper surface of an n-type gallium oxide substrate layer 1; preparing an n-type current expansion layer 3 on the upper surface of the n-type gallium oxide epitaxial drift layer 2; preparing a p-type nickel oxide base region 4 on the upper surface of the n-type current expansion layer 3; preparing an n+ type epitaxial source region 5 on the upper surface of the p-type nickel oxide base region 4, and etching the upper surface of the n+ type epitaxial source region 5 by a photolithography process, penetrating the n-type current expansion layer 3 and the p-type nickel oxide base region 4, until extending into the n-type gallium oxide epitaxial drift layer 2, so as to form a gate groove; growing a shielding gate structure 6 in the gate groove, wherein the shielding gate structure 6 includes a shielding layer 61, a gate dielectric layer 62 and a gate layer 63 stacked from bottom to top. Specifically:

[0039] like Figure 2 As shown in (1), after the n-type gallium oxide substrate layer 1 is pretreated, a halide vapor phase epitaxy (HVPE) device is used, high-purity GaCl and O2 gases are used as gallium and oxygen precursors, SiCl4 and N2 are used as doping sources and carrier gases, respectively, in a growth environment at 800°C to epitaxially grow an n-type gallium oxide epitaxial drift layer 2 on the upper surface of the n-type gallium oxide substrate layer 1.

[0040] like Figure 2 As shown in (2), after obtaining the epitaxial n-type gallium oxide epitaxial drift layer 2, a halide vapor phase epitaxy (HVPE) device is used, with high-purity GaCl and O2 gases as gallium and oxygen precursors, SiCl4 and N2 as doping sources and carrier gases, respectively, in a growth environment at 800°C to prepare an n-type current spreading layer 3 on the upper surface of the n-type gallium oxide epitaxial drift layer 2.

[0041] like Figure 2 As shown in (3), after obtaining the n-type current spreading layer 3, the sample is cleaned with acetone and isopropanol, and then continuously rinsed with deionized water and dried to remove impurities; then, a radio frequency sputtering device is used to sputter high-purity NiO ceramic molecules onto the upper surface of the n-type current spreading layer 3; the sputtering process is carried out at room temperature and an Ar / O2 mixture 20 / 1sccm environment, the chamber pressure is 3mTorr, and the radio frequency RF power is 150W, wherein the deposition rate of the p-type nickel oxide base region 4 is 0.75nm / min. After the sputtering is completed, annealing is performed to improve the interface quality of the p-type nickel oxide base region 4, and the annealing temperature is 300°C. By using radio frequency magnetron sputtering, the device preparation time can be shortened and the interface reliability of the heterojunction can be improved; in addition, the use of an annealing process can reduce the interface state at the heterojunction interface.

[0042] like Figure 2 As shown in (4), after obtaining the p-type nickel oxide base region 4, gallium is evaporated in oxygen plasma and the temperature of the overall structure is maintained at 800°C, wherein the oxygen plasma RF power is 100W, the oxygen gas flow rate is controlled at 4sccm, the chamber pressure is 0.5mTorr, and the evaporation is continued for a period of time to allow gallium oxide molecules to be deposited on the upper surface of the p-type nickel oxide base region 4 to obtain an n+ type epitaxial source region 5, and then annealing is performed to activate the doping element Si ions.

[0043] like Figure 2 As shown in (5)-(6), here, before growing the shielding gate structure 6 in the gate groove, the preparation method also includes: etching both sides of the n+ type epitaxial source region 5 using a dry etching process to expose a portion of the surface of the p-type nickel oxide base region 4 to form a stepped structure; and preparing a p+ injection source region 7 on the stepped structure.

[0044] Specifically, after etching both sides of the n+ type epitaxial source region 5 using a photolithography process, an inductively coupled plasma ICP dry etching process is used to etch part of the surface of the p-type nickel oxide base region 4 to form a pre-implantation area; an ion implantation process is used to prepare a p+ implantation source region 7 in the pre-implantation area, and then annealing is performed to activate the implanted doping element Li ions.

[0045] like Figure 2As shown in (7)-(10) in the figure, after obtaining the p+ injection source region 7, the shield gate structure 6 is prepared. Specifically, first, the upper surface of the n+ epitaxial source region 5 is etched using a photolithography process, and a mask is used to protect the outer area of ​​the gate groove; then, an inductively coupled plasma ICP dry etching process is used to penetrate the n+ epitaxial source region 5, the n-type current expansion layer 3 and the p-type nickel oxide base region 4, until it extends into the n-type gallium oxide epitaxial drift layer 2, so as to form a rounded rectangular gate groove with a depth of about 2μm. Then, an ion implantation process is used to prepare a shield layer 61 at the bottom of the gate groove. After the preparation is completed, the overall structure is annealed to activate the implanted doping element N ions; a gate dielectric layer 62 of a certain thickness is deposited on the upper surface of the shield layer 61 and the sidewall of the gate groove, and the gate dielectric layer 62 is in the shape of a groove; a gate layer 63 is deposited in the gate dielectric layer 62 using a chemical vapor deposition device.

[0046] It should be noted that, when preparing the shielding gate structure 6 , only one ion implantation process is used, which effectively reduces the lattice damage of the material and effectively improves the working stability of the device.

[0047] like Figure 2 As shown in (11)-(13) in the figure, the preparation method here also includes: preparing an isolation layer 8 on the upper surface of the n+ type epitaxial source region 5 and the upper surface of the shielding gate structure 6; preparing a source metal layer 9 on the upper surface of the n+ type epitaxial source region 5, the upper surface of the isolation layer 8 and the upper surface of the p+ implanted source region 7; and preparing a drain metal layer 10 on the lower surface of the n-type gallium oxide substrate layer 1.

[0048] Specifically, a chemical vapor deposition device is used to deposit an isolation dielectric on the upper surface of the n+ epitaxial source region 5 and the upper surface of the shielding gate structure 6 to form an isolation layer 8. Subsequently, an electron beam evaporation coating machine is used to evaporate the source metal to prepare a source metal layer 9 on the upper surface of the isolation layer 8 and the upper surface of the p+ injection source region 7; finally, a drain metal layer 10 is prepared on the lower surface of the n-type gallium oxide substrate layer 1 through a thinning process and a back gold process, thereby obtaining a complete shielded gate gallium oxide MOSFET device based on a heterojunction, which is an enhancement MOSFET device with a vertical structure.

[0049] Aiming at the problem that it is difficult to achieve p-type doping in existing gallium oxide MOSFET devices, resulting in poor device insulation performance, large leakage current, low switching ratio, and difficulty in giving full play to the advantages of gallium oxide materials, the present invention provides a shielded gate gallium oxide MOSFET device based on heterojunction and a preparation method thereof. The device comprises a heterojunction consisting of an n-type current spreading layer, a p-type nickel oxide base region and an n+ type epitaxial source region. By adopting p-type nickel oxide and gallium oxide to construct a pn heterojunction MOSFET, the key difficulty problem of gallium oxide lacking effective p-type doping is effectively overcome, and the device has the advantages of good insulation performance, low on-resistance, and high current switching ratio. In addition, the shielded gate adopts a trench gate structure, which can turn off the device when the gate bias is zero, reduce static power consumption, and increase the current switching ratio of the device. At the same time, an n-type current spreading layer is provided, which can effectively reduce the on-resistance of the device. In addition, by using the shielded gate structure, the electric field at the gate dielectric of the device is modulated, the electric field concentration phenomenon is effectively suppressed, and the risk of device breakdown and damage is reduced. The shielded gate gallium oxide MOSFET device based on heterojunction and the preparation method thereof provided by the present invention can help realize high-efficiency, high-power and commercially scalable gallium oxide microelectronic systems and promote their practical application.

[0050] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A shielded gate gallium oxide MOSFET device based on heterojunction, characterized in that: include: n-type gallium oxide substrate layer (1), n-type gallium oxide epitaxial drift layer (2), n-type current spreading layer (3), p-type nickel oxide base region (4), n+ type epitaxial source region (5), shielded gate structure (6); wherein, The n-type gallium oxide substrate layer (1), the n-type gallium oxide epitaxial drift layer (2), the n-type current spreading layer (3), the p-type nickel oxide base region (4) and the n+ type epitaxial source region (5) are stacked in sequence from bottom to top; the n-type current spreading layer (3), the p-type nickel oxide base region (4) and the n+ type epitaxial source region (5) form a heterojunction; The shielding gate structure (6) is arranged in a region extending downward from the top of the n+ type epitaxial source region (5) to the inside of the n-type gallium oxide epitaxial drift layer (2).

2. The shielded gate gallium oxide MOSFET device based on heterojunction according to claim 1, characterized in that: A gate groove is provided in the heterojunction and the n-type gallium oxide epitaxial drift layer (2), and the gate groove extends downward from the top of the n+ type epitaxial source region (5) to the inside of the n-type gallium oxide epitaxial drift layer (2); The shielding gate structure (6) comprises: a shielding layer (61), a gate dielectric layer (62) and a gate layer (63); The shielding layer (61) is located at the bottom of the gate groove; The gate dielectric layer (62) is arranged on the sidewalls of the gate groove and the upper surface of the shielding layer (61); The gate layer (63) is filled in the gate groove provided with the gate dielectric layer (62), and the top of the gate layer (63) is flush with the top of the gate groove.

3. The shielded gate gallium oxide MOSFET device based on heterojunction according to claim 1, characterized in that: The p-type nickel oxide base region (4) and the n+ type epitaxial source region (5) form a stepped structure; the shielded gate gallium oxide MOSFET device based on heterojunction further comprises: a p+ injection source region (7), an isolation layer (8), a source metal layer (9) and a drain metal layer (10); wherein, The p+ injection source region (7) is arranged on the stepped structure, and the top of the p+ injection source region (7) is flush with the top of the p-type nickel oxide base region (4); The isolation layer (8) is located on the upper surface of the shielding gate structure (6) and on the upper surface of part of the n+ type epitaxial source region (5); The source metal layer (9) covers the upper surface of the n+ type epitaxial source region (5), the upper surface of the isolation layer (8) and the upper surface of the p+ implanted source region (7); The drain metal layer (10) is located on the lower surface of the n-type gallium oxide substrate layer (1).

4. The shielded gate gallium oxide MOSFET device based on heterojunction according to claim 1, characterized in that: The thickness of the p-type nickel oxide base region (4) is in the range of 300 nm to 700 nm.

5. The shielded gate gallium oxide MOSFET device based on heterojunction according to claim 1, characterized in that: The n+ type epitaxial source region (5) is a β-Ga2O3 material doped with Si element, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 The thickness of the n+ type epitaxial source region (5) is in the range of 200nm to 300nm.

6. The shielded gate gallium oxide MOSFET device based on heterojunction according to claim 3, characterized in that: The p+ injection source region (7) is a β-Ga2O3 material doped with Li, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 , the junction depth thickness is in the range of 100nm to 200nm.

7. The shielded gate gallium oxide MOSFET device based on heterojunction according to claim 2, characterized in that: The depth of the gate groove ranges from 2 μm to 5 μm.

8. A method for preparing a shielded gate gallium oxide MOSFET device based on a heterojunction, characterized in that: The preparation method is used to prepare the shielded gate gallium oxide MOSFET device based on heterojunction according to any one of claims 1 to 7, and the preparation method comprises: Epitaxially growing an n-type gallium oxide epitaxial drift layer (2) on the upper surface of the n-type gallium oxide substrate layer (1); Preparing an n-type current spreading layer (3) on the upper surface of the n-type gallium oxide epitaxial drift layer (2); Preparing a p-type nickel oxide base region (4) on the upper surface of the n-type current spreading layer (3); An n+ type epitaxial source region (5) is prepared on the upper surface of the p-type nickel oxide base region (4), and the upper surface of the n+ type epitaxial source region (5) is etched using a photolithography process, penetrating the n-type current spreading layer (3) and the p-type nickel oxide base region (4) until extending into the interior of the n-type gallium oxide epitaxial drift layer (2), so as to form a gate groove; A shielding gate structure (6) is grown in the gate groove, wherein the shielding gate structure (6) comprises a shielding layer (61), a gate dielectric layer (62) and a gate layer (63) stacked from bottom to top.

9. The method for preparing a shielded-gate gallium oxide MOSFET device based on a heterojunction according to claim 8, characterized in that: Before growing the shielding gate structure (6) in the gate trench, the preparation method further comprises: Etching both sides of the n+ type epitaxial source region (5) using a dry etching process to expose a portion of the surface of the p type nickel oxide base region (4) to form a stepped structure; A p+ implantation source region (7) is prepared on the stepped structure.

10. The method for preparing a shielded-gate gallium oxide MOSFET device based on a heterojunction according to claim 8, characterized in that: The preparation method further comprises: Preparing an isolation layer (8) on the upper surface of the n+ type epitaxial source region (5) and the upper surface of the shielding gate structure (6); Preparing a source metal layer (9) on the upper surface of the n+ type epitaxial source region (5), the upper surface of the isolation layer (8) and the upper surface of the p+ implanted source region (7); A drain metal layer (10) is prepared on the lower surface of the n-type gallium oxide substrate layer (1).

Images