Semiconductor memory device

Abstract

The invention discloses a semiconductor storage device, belongs to the technical field of semiconductor storage, and solves the problems that the application of a Z2-FET mainly focuses on a volatile storage device at present, and the limitation exists in the aspect of realizing high storage density and flexible storage architecture. And the application requirements of electronic products on high-integration density and high-performance embedded memories are difficult to meet. The device is composed of the following parts: an undoped or weakly doped substrate, an insulating buried layer, a channel region, a tunneling oxide layer, a floating gate layer, a barrier oxide layer, a grid electrode, a low doped region, a grid electrode side wall, a heavily doped drain electrode region, an inverted heavily doped source electrode region, a drain electrode metal contact, a source electrode metal contact and a grid electrode metal contact. The device structure provided by the invention has symmetry, can use a complete self-alignment process, is completely compatible with an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) process, is favorable for further improving the storage density and realizing a flexible storage framework, and provides a new application scene and a new development direction for a field effect positive feedback device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a semiconductor storage device. Background Art

[0002] Z 2 -FET is a new type of semiconductor device, which works based on a novel field effect positive feedback mechanism. Different from the traditional MOSFET, Z 2 -FET adopts a new mechanism of charge in-situ storage and internal feedback amplification readout. Its subthreshold swing is significantly lower than the physical limit of ordinary MOSFET, making it show great potential in low-voltage and low-power integrated circuit applications. 2 -FET exhibits a significant hysteresis effect in output characteristics, breaking away from the limitations of traditional DRAM that relies on external capacitors for charge storage and external amplifiers for signal reading. It has the excellent performance of single-transistor storage and high-speed reading and writing, and its performance far exceeds that of traditional memory. 2 -FET also has fast switching speed, controllable switching voltage and high on-state current, so it is used by STMicroelectronics, a leading European semiconductor company, for electrostatic discharge protection inside the chip. 2 -FET has become a research hotspot for the new generation of semiconductor devices.

[0003] Current semiconductor devices, such as a semiconductor field effect positive feedback device with application number CN201710064235.0, have the following technical points: they are composed of the following parts: an undoped or weakly doped substrate; an insulating buried layer located on the substrate; a channel region located on the insulating buried layer, a first low-doped region on both sides of the channel region, a second low-doped region, a heavily doped cathode region and an inverse heavily doped anode region; a gate oxide layer covering the channel, and a gate on the gate oxide layer; a first side wall and a second side wall on both sides of the gate; in addition, they also include: a cathode metal contact in contact with the cathode region, an anode metal contact in contact with the anode region, and a gate metal contact in contact with the gate; the first low-doped region and the second low-doped region have the same doping type; the channel region is undoped or weakly doped.

[0004] The device structure proposed in the above technical solution is symmetrical and can use a fully self-aligned process, which is fully compatible with the MOSFET process. This device not only retains the low subthreshold swing and gate-controlled hysteresis output characteristics of the field effect positive feedback device, but can be widely used in switches, memories, and electrostatic protection, etc., and has lower process costs and less process difficulty.

[0005] However, currently Z 2The application of -FET is mainly concentrated in volatile memory devices, and there are certain limitations in further realizing high storage density and flexible storage architecture, which makes it difficult to meet the application requirements of consumer electronic products for high integration density and high-performance embedded memory.

[0006] Therefore, a semiconductor memory device is proposed to solve or alleviate the above problems. Summary of the invention

[0007] The purpose of the present invention is to solve the shortcomings of the prior art and propose a semiconductor memory device that uses a floating gate structure to store charge and can realize the functions of dynamic random access memory and non-volatile memory respectively under different bias conditions, further improve energy efficiency, and realize a flexible storage architecture. At the same time, the device retains the traditional Z 2 -FET has a sharp turn-on characteristic, good hysteresis characteristics and high data read and write speed. The device proposed in this invention has a symmetrical structure, uses the masking effect of the gate sidewall and tilted ion implantation, is prepared based on a self-aligned process, and is fully compatible with ordinary MOSFET processes.

[0008] In the present invention, the injection barrier of electrons and holes in the field effect positive feedback device is formed by the positive gate and the low-doped region adjacent to the channel. In the non-volatile storage mode, a higher bias is applied to the gate and back gate of the device, and electrons or holes tunnel into the floating gate layer under the action of the electric field and are captured, resulting in a change in the charge of the floating gate layer, causing the turn-on voltage of the device to shift, thereby realizing the storage of different logical states. In order to avoid the transient discharge effect of the drain causing the device to be triggered prematurely, the reading of the logical state is achieved by applying a voltage to the source and measuring the drain current. In the dynamic random access memory mode, the writing of the logical state is achieved by applying a small voltage to the gate and back gate, and the reading of the logical state is triggered by a small amount of stored charge. The transient feedback effect inside the device is triggered by a pulse voltage applied to the drain and the source current is measured.

[0009] In order to achieve the above object, the present invention adopts the following technical solutions:

[0010] A semiconductor memory device consists of the following parts: an undoped or weakly doped substrate, an insulating buried layer, a channel region, a tunneling oxide layer, a floating gate layer, a blocking oxide layer, a gate, a low-doped region, a gate sidewall, a heavily doped drain region and an inverse heavily doped source region, a drain metal contact, a source metal contact and a gate metal contact.

[0011] Preferably, the semiconductor memory device is based on silicon-on-insulator or other semiconductors built on an insulating layer.

[0012] Preferably, the channel is undoped or weakly doped, and two sides of the channel are weakly doped regions.

[0013] Preferably, the source and drain are heavily anti-doped, ie one is n-type and the other is p-type doped.

[0014] The present invention has the following beneficial effects:

[0015] In the present invention, based on Z 2 The new unified memory of -FET is built on a fully depleted insulating layer silicon substrate, and the silicon layer thickness of the channel is less than 50nm. On the one hand, the gate forms a carrier injection barrier in the channel with the help of the fully depleted thin silicon layer. On the other hand, the electron injection barrier is formed by the low-doped area next to the channel area. When a high bias is applied to the gate and the back gate, the carriers tunnel through the blocking oxide layer, and the device realizes charge storage in non-volatile mode through polysilicon floating gate, nitride or SiO2 / HfO2 interface traps. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a structural schematic diagram of the present invention;

[0018] Figure 2 is a preparation flow chart of the present invention;

[0019] Figure 3 It is a schematic diagram of the structures of Examples 1 to 6 of the present invention.

[0020] 1. Substrate; 2. Insulating buried layer; 3. Channel region; 4. Tunneling oxide layer; 5. Floating gate layer; 6. Blocking oxide layer; 7. Gate; 8. Low-doped region; 9. Low-doped region; 10. Gate sidewall; 11. Gate sidewall; 12. Drain region; 13. Source region; 14. Drain metal contact; 15. Source metal contact; 16. Gate metal contact. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0024] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0025] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0026] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] A semiconductor memory device, such as Figure 1 As shown, it consists of the following parts: undoped or weakly doped substrate, insulating buried layer, channel region, tunneling oxide layer, floating gate layer, blocking oxide layer, gate, low-doped region, gate sidewall, heavily doped drain region and inverted heavily doped source region, drain metal contact, source metal contact and gate metal contact.

[0028] Preferably, the semiconductor memory device is based on silicon-on-insulator or other semiconductors built on an insulating layer.

[0029] Preferably, the channel is undoped or weakly doped, and both sides of the channel are weakly doped regions.

[0030] Preferably, the source and drain are heavily counter-doped, ie one is n-type and the other is p-type doped.

[0031] Preferably, the device structure is symmetrical, and the gate sidewall is used as a mask for ion implantation to form the source and drain doping regions in a self-aligned manner.

[0032] Preferably, the device stores charges via interface traps of polysilicon floating gate, nitride, or SiO2 and HfO2 stacked oxide.

[0033] Preferably, the semiconductor memory device is mainly used as DRAM and Flash under different gate voltage conditions, and the data stored in the two modes do not affect each other, so high-density storage can be achieved.

[0034] The invention proposes a method based on Z 2 -FET new unified memory preparation method, the specific steps refer to Figure 2 for:

[0035] The initial silicon-on-insulator layer includes a substrate (1), a buried oxide layer (2) and an upper semiconductor layer (3);

[0036] Depositing a tunneling oxide layer (4), a floating gate layer (5), a blocking oxide layer (6) and a positive gate material (7);

[0037] Photolithography and etching to form a positive gate pattern;

[0038] Using the gate as a mask, ion implantation is performed in a self-aligned manner to form low-doped regions (8) and (9);

[0039] Depositing a layer of gate sidewall dielectric and performing dry anisotropic etching to form gate sidewalls such as (10) and (11);

[0040] Using the gate as a mask, an inclined ion implantation is performed to form a heavily n-type doped drain (12);

[0041] Using the gate as a mask, an inclined ion implantation is used to form a heavily p-type doped source (13) and a thermal annealing is performed to activate the implanted ions;

[0042] Metal contacts are deposited and annealed to form metal contacts of the drain (14), drain (15), and gate (16).

[0043] Various embodiments of the present invention are provided below:

[0044] Example 1 (corresponding to Figure 1 The device structure and Figure 2 Process flow):

[0045] (1) Figure 2The figure (a) shows the initial silicon wafer on the insulating layer. The substrate doping is generally weak p-type doping with a doping concentration of 10 15 cm -2 Up to 10 17 cm -2 The buried layer is usually silicon dioxide with a thickness between 10nm and 1000nm. The upper channel material is usually silicon, silicon germanium or gallium nitride, etc., with a thickness between 5nm and 50nm.

[0046] (2) Depositing a tunneling oxide layer, a floating gate layer, a blocking oxide layer and a positive gate layer in sequence, such as Figure 2 As shown in (b). The tunneling oxide layer is generally silicon dioxide (SiO2), but can also be silicon nitride, aluminum oxide or hafnium oxide and other materials, with a thickness generally between 5nm and 10nm, and the deposition method can be thermal oxidation, chemical vapor deposition or atomic layer deposition and other methods. The floating gate layer is generally polycrystalline silicon, and the thickness is generally between 10nm and 50nm. The blocking oxide layer material is the same as the tunneling oxide layer material, and the thickness is generally between 10nm and 30nm. The positive gate is generally polycrystalline silicon or metal, or a composite layer of polycrystalline silicon and metal, and its thickness can be 2nm to 200nm.

[0047] (3) Photolithography is performed to open a window for the positive gate pattern, and then the positive gate is etched using the photoresist as a mask to form a gate pattern, such as Figure 2 As shown in (c), dry or wet etching can be used. Dry etching generally uses fluorine-based or halogen-based gases, such as SF6, CHF3, HBr or Cl2, while wet etching generally uses TMAH, KOH and other solutions.

[0048] (4) Self-aligned ion implantation is performed using the gate as a self-aligned mask to form low-doped regions on both sides of the channel, such as Figure 2 As shown in (d) in the figure, ion implantation usually uses boron or BF2 with a dose of 10 12 cm -2 Up to 10 14 cm -2 The energy is between 2keV and 40keV.

[0049] (5) Deposit a layer of gate sidewall material, such as commonly used silicon nitride, silicon dioxide, or low dielectric constant dielectrics such as SiOCN and SiBCN. Deposition can be done using chemical vapor deposition, atomic layer deposition, and other processes. Etching is then performed to form a Figure 2 The gate sidewall shown in (e) is generally etched using vertically directional reactive ion etching, and dry etching generally uses fluorine-based gases such as SF6, CHF3 or CH3F.

[0050] (6) Use tilted ion implantation to form a heavily doped drain n+ region, such as Figure 2 Medium (f). Arsenic or phosphorus is usually used, with a dose of 10 13 cm -2 Up to 10 16 cm -2 The energy is between 10keV and 300keV, and the inclination angle is between 0 and 45 degrees.

[0051] (7) Use tilted ion implantation to form a heavily doped source p+ region, such as Figure 2 (g). Boron or BF2 is usually used for ion implantation, with a dose of 10 13 cm -2 Up to 10 16 cm -2 The energy is between 2keV and 40keV, and the tilt angle is between 0 degrees and minus 45 degrees. Thereafter, annealing is performed to activate the doping of the source and drain. The ion annealing temperature is generally between 800 degrees and 1300 degrees, and the time is 100 microseconds to 10 seconds.

[0052] (8) Deposit metal and anneal to form the following on the source, drain and gate: Figure 2 The electrode shown in (h); commonly used metals are aluminum, nickel, titanium or metal silicides, such as nickel silicon, titanium silicon, etc., and the annealing temperature is between 300 degrees and 900 degrees.

[0053] Example 2 (corresponding to Figure 3 Device structure diagram in (a):

[0054] Example 2 is the inverse structure of Example 1, except that the low-doped regions on both sides of the channel are changed to n-type doping instead of p-type. In this example, the gate controls the electron injection barrier, while the n-type weakly doped region on the left side of the channel controls the hole injection barrier. The specific implementation steps are similar to those of Example 1, except that in step (4), arsenic or phosphorus is generally used for ion implantation, with a dose of 10 12 cm -2 Up to 10 14 cm -2 The energy is between 2keV and 40keV.

[0055] Example 3 (corresponding to Figure 3 Device structure diagram in (b):

[0056] The principle of Example 3 is similar to that of Example 1, except that the device adopts a SONOS structure and stores charge through nitride. Compared with floating gate memory, SONOS memory has higher potential for further reducing device size, lower operating voltage, longer reliability and data retention time. The difference in the implementation steps mainly lies in the deposition material of the floating gate layer and the deposition thickness of the tunneling oxide layer and the blocking oxide layer. In this embodiment, the deposition material of the floating gate layer is generally silicon nitride, the thickness of the blocking oxide layer is generally between 5nm and 10nm, and the thickness of the tunneling oxide layer is generally between 2nm and 5nm.

[0057] Example 4 (corresponding to Figure 3 Device structure diagram in (c):

[0058] Example 4 is an inverted structure of Example 3, except that the low-doped regions on both sides of the channel are changed to n-type doping instead of p-type. The specific implementation steps are similar to those of Example 3. The difference is that in step (4), arsenic or phosphorus is generally used for ion implantation, and the dosage is 10 12 cm -2 Up to 10 14 cm -2 The energy is between 2keV and 40keV.

[0059] Example 5 (corresponding to Figure 3 Device structure diagram in (d)):

[0060] Example 5 uses the interface traps of SiO2 and HfO2 stacked oxides to capture charges and realize information storage through the charge injection mechanism. Compared with the traditional three-layer structure, the double-layer structure has a simpler process and a lower operating voltage. In this embodiment, the thickness of the tunneling oxide layer SiO2 is generally 2nm, and the thickness of HfO2 is generally 20nm. The specific implementation steps are similar to those of Example 1, except that the materials deposited in step (2) are 2nmSiO2 tunneling oxide layer, 20nm HfO2 dielectric layer and positive gate, respectively, rather than a three-layer floating gate structure.

[0061] Example 6 (corresponding to Figure 3 Device structure diagram in (e):

[0062] Example 6 is an inverted structure of Example 5, except that the low-doped regions on both sides of the channel are changed to n-type doping instead of p-type. The specific implementation steps are similar to those of Example 5. The difference is that in step (4), arsenic or phosphorus is generally used for ion implantation, and the dosage is 10 12 cm -2 Up to 10 14 cm -2 The energy is between 2keV and 40keV.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, characterized in that: The invention is composed of the following parts: an undoped or weakly doped substrate (1), an insulating buried layer (2), a channel region (3), a tunneling oxide layer (4), a floating gate layer (5), a blocking oxide layer (6), a gate (7), low-doped regions (8) and (9), gate sidewalls (10) and (11), a heavily doped drain region (12) and an inverse heavily doped source region (13), a drain metal contact (14), a source metal contact (15) and a gate metal contact (16).

2. A semiconductor memory device according to claim 1, characterized in that: The semiconductor memory device is based on silicon-on-insulator or other semiconductors built on an insulating layer.

3. A semiconductor memory device according to claim 1, characterized in that: The channel is undoped or weakly doped, and both sides of the gate are low-doped regions.

4. A semiconductor memory device according to claim 1, characterized in that: The source and drain are heavily inversion doped.

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