A transistor structure and electronic device

Abstract

This invention discloses a transistor structure and an electronic device. The transistor structure includes a substrate and a transistor module and a clamping module located on one side of the substrate. One side of the substrate has: a buffer layer located on the substrate, including a first buffer layer on the transistor module and a second buffer layer on the clamping module; a barrier layer located on the buffer layer, including a first barrier layer on the transistor module and a second barrier layer on the clamping module; a capping layer located on the barrier layer, including a first capping layer on the transistor module and a second capping layer on the clamping module; a source and a drain, with the first capping layer spaced between the source and the drain; a connecting electrode and a gate, the connecting electrode having an ohmic contact with the first barrier layer, and the gate having a Schottky contact with the first barrier layer; an anode and a cathode located on the side of the barrier layer away from the buffer layer and on the clamping module, the cathode being electrically connected to the gate, and the anode being electrically connected to the connecting electrode. This transistor structure can improve gate reliability.

Description

Technical Field

[0001] This invention relates to the field of display device technology, and in particular to a transistor structure and electronic device. Background Technology

[0002] Thanks to its superior material properties, gallium nitride (GaN)-based power electronic devices can surpass the performance limits of silicon (Si) and silicon carbide (SiC) devices, enabling efficient, miniaturized, and high-power-density power electronic systems. P-gate GaN high electron mobility transistors (HEMTs), as enhancement-mode devices, are leading the commercialization of GaN power devices due to their normally-off characteristics. However, due to a series of reliability issues inherent in GaN power device materials, p-gate GaN HEMTs have not yet been able to replace traditional silicon-based devices on a large scale. The gate of a GaN HEMT determines the device's turn-on and turn-off states, and its stability directly affects the stable operation of the device; therefore, the reliability of the GaN power device gate is of particular concern.

[0003] Currently, research on gate reliability issues in p-gate GaN HEMTs mainly includes two categories: gate safe operating voltage and threshold voltage stability. Gate safe operating voltage refers to the gate voltage at which GaN HEMT devices can operate reliably over a long period. Under a ten-year operating life, the stable operating voltage of a p-gate GaN HEMT is typically only 7V, while GaN manufacturers usually recommend a gate operating voltage greater than 5V. This low gate operating life severely limits the design freedom of the gate drive circuit; therefore, efforts should be made to optimize the gate operating life of GaN HEMTs. On the other hand, the gallium nitride material in the capping layer contains various defects. Under voltage stress, charge carriers are trapped by these defects and cannot be released in time, causing the device's threshold voltage to drift, which may lead to problems such as false turn-on and increased switching losses. Summary of the Invention

[0004] The present invention provides a transistor structure and an electronic device. The transistor structure can improve the operating life of the gate and make the threshold voltage more stable, thereby improving the reliability of the gate.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A transistor structure includes a substrate and a transistor module and a clamping module located on one side of the substrate, wherein an electrical isolation region exists between the transistor module and the clamping module;

[0007] One side of the substrate has:

[0008] A buffer layer, located on the substrate, includes a first buffer layer located on the transistor module and a second buffer layer located on the clamping module;

[0009] A barrier layer, located on the side of the buffer layer away from the substrate, includes a first barrier layer located in the transistor module and a second barrier layer located in the clamping module;

[0010] A capping layer, located on the side of the barrier layer away from the buffer layer, includes a first capping layer located within the transistor module and a second capping layer located within the clamping module;

[0011] The source and drain are located on the side of the barrier layer away from the buffer layer and in the transistor module. The source and drain are in ohmic contact with the first barrier layer. The first capping layer is disposed between the source and the drain.

[0012] A connecting electrode and a gate are spaced apart on the side of the capping layer away from the barrier layer and located in the transistor module. The connecting electrode is in ohmic contact with the first capping layer, and the gate is in Schottky contact with the first capping layer.

[0013] The anode and cathode are located on the side of the barrier layer away from the buffer layer and in the clamping module. The cathode is electrically connected to the gate, and the anode is electrically connected to the connecting electrode.

[0014] The clamping module is used to clamp the voltage between the anode and the cathode within a preset regulated value.

[0015] Optionally, the clamping module includes a first clamping unit; wherein,

[0016] The second buffer layer includes a first sub-buffer layer located in the first clamping unit;

[0017] The second barrier layer includes a first sub-barrier layer located in the first clamping unit;

[0018] The second cap layer includes a first sub-cap layer located in the first clamping unit, the first sub-cap layer being disposed at a distance between the anode and the cathode;

[0019] It also includes a first electrode, a second electrode, and a third electrode located in the first clamping unit;

[0020] The first electrode, the second electrode, the anode, the cathode, the source, and the drain are disposed in the same layer. The first electrode is disposed at a distance from the anode on the side away from the first sub-capping layer. The second electrode is disposed at a distance from the cathode on the side away from the first sub-capping layer. The first electrode and the second electrode are in ohmic contact with the first sub-barrier layer.

[0021] The third electrode is disposed on the same layer as the gate, the third electrode is in Schottky contact with the first sub-cap layer, and the third electrode is electrically connected to the first electrode and the second electrode.

[0022] Optionally, the clamping module includes a second clamping unit, which comprises N sub-clamping units, where N is an integer greater than or equal to 1; wherein,

[0023] The second buffer layer includes a second sub-buffer layer located in the sub-clamping unit;

[0024] The second barrier layer includes a second sub-barrier layer located in the sub-clamping unit;

[0025] The second cap layer includes a second sub-cap layer located in the sub-clamping unit;

[0026] It also includes a fourth electrode, a fifth electrode, and a sixth electrode located in the sub-clamping unit;

[0027] The fourth electrode and the fifth electrode are disposed in the same layer as the source and drain electrodes. The fourth electrode and the fifth electrode are located on both sides of the second sub-capping layer and are in ohmic contact with the second sub-barrier layer. The fifth electrode is disposed at a distance from the second sub-capping layer.

[0028] The sixth electrode is disposed in the same layer as the gate, the sixth electrode is in Schottky contact with the second sub-capping layer, and is in Ohmic contact with the second sub-barrier layer through the fourth electrode;

[0029] When N=1, the sixth electrode of the sub-clamping unit is the cathode of the second clamping unit, and the fifth electrode of the sub-clamping unit is the anode of the second clamping unit;

[0030] When N≥2, the second sub-buffer layer and the second sub-barrier layer of each sub-clamping unit are electrically isolated. The N sub-clamping units are connected in series in sequence. The sixth electrode of the first sub-clamping unit is the cathode of the second clamping unit. The fifth electrode of the (N-1)th sub-clamping unit is connected to the sixth electrode of the Nth sub-clamping unit. The fifth electrode of the Nth sub-clamping unit is the anode of the second clamping unit.

[0031] Optionally, the clamping module includes the first clamping unit and the second clamping unit;

[0032] The anode of the first clamping unit is the anode of the clamping module, and the cathode of the first clamping unit is the cathode of the clamping module;

[0033] The third electrode of the first clamping unit is connected to the first electrode through the second clamping unit, the cathode of the second clamping unit is connected to the third electrode, and the anode of the second clamping unit is connected to the first electrode.

[0034] Optionally, it may also include a passivation layer and a wiring layer;

[0035] The passivation layer is located on the side of the gate and connection electrode facing away from the substrate;

[0036] The wiring layer is located on the side of the passivation layer away from the substrate, and the wiring layer includes a first connection line and a second connection line;

[0037] The cathode of the clamping module is connected to the gate via a first connecting line, and the anode of the clamping module is connected to the connecting electrode via a second connecting line.

[0038] Optionally, the material of the gate is different from the material of the connecting electrode.

[0039] Optionally, the buffer layer is made of gallium nitride, the barrier layer is made of aluminum gallium nitride, and the capping layer is made of p-type gallium nitride.

[0040] Optionally, the source and drain electrodes are made of at least one of titanium, aluminum, gold, nickel, and titanium nitride.

[0041] The gate material includes at least one of titanium nitride, titanium, nickel, and gold;

[0042] The material of the connecting electrode includes at least one of nickel, gold, and titanium.

[0043] Optionally, the buffer layer includes multiple sub-film layers sequentially stacked on the substrate;

[0044] The sub-film layer on the side of the buffer layer away from the substrate is a channel layer, and the channel layer and the barrier layer form a heterostructure.

[0045] Optionally, an insertion layer is provided between the buffer layer and the barrier layer, the material of the insertion layer including aluminum nitride, and the insertion layer located in the transistor module is electrically isolated from the insertion layer located in the clamping module.

[0046] Optionally, the electrical isolation region between the transistor module and the clamping module is achieved by ion implantation or trench etching.

[0047] The present invention also includes an electronic device comprising any of the transistor structures provided in the above-described technical solutions.

[0048] This invention provides a transistor structure and an electronic device. In this transistor structure, a first buffer layer, a first barrier layer, a first capping layer, a source, a drain, a connecting electrode, and a gate are located in a transistor module, while a second buffer layer, a second barrier layer, a second capping layer, an anode, and a cathode are located in a clamping module. The transistor module and the clamping module are fabricated in the same layer. Since the gate of the transistor module is connected to the cathode of the clamping module, and the connecting electrode of the transistor module is connected to the anode of the clamping module, when the voltage applied to the gate exceeds a preset value, the clamping module can clamp the voltage on the gate within a preset regulated value, preventing the voltage on the gate from becoming too high and improving the gate's operating life. Furthermore, since there is an ohmic contact between the connecting electrode and the first capping layer, the traps that capture electrons in the first capping layer are quickly recombinated by holes injected by the connecting electrode, avoiding the problem of traps in the first capping layer capturing electrons and not being released in time. Therefore, the threshold voltage of the transistor structure no longer deviates, making the threshold voltage more stable, and ultimately improving the reliability of the transistor gate. Attached Figure Description

[0049] Figure 1 A schematic diagram of a transistor structure provided in an embodiment of the present invention;

[0050] Figure 2 This is an equivalent schematic diagram of a transistor structure provided in an embodiment of the present invention;

[0051] Figure 3 An equivalent circuit diagram of a transistor structure provided in an embodiment of the present invention;

[0052] Figure 4 The voltage-current characteristic curve of the Zener diode provided in the embodiment of the present invention;

[0053] Figure 5 An equivalent circuit diagram of a transistor structure provided in an embodiment of the present invention;

[0054] Figure 6 This is an equivalent schematic diagram of a transistor structure provided in an embodiment of the present invention;

[0055] Figure 7 An equivalent circuit diagram of a first clamping unit provided in an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of the structure of a second clamping unit provided in an embodiment of the present invention;

[0057] Figure 9 An equivalent circuit diagram of a second clamping unit provided in an embodiment of the present invention;

[0058] Figure 10 An equivalent circuit diagram of a clamping module provided in an embodiment of the present invention;

[0059] Figure 11 A schematic diagram of a transistor structure provided in an embodiment of the present invention;

[0060] Figure 12 A schematic planar view of a transistor structure provided in an embodiment of the present invention;

[0061] Figure 13 A schematic planar view of a transistor structure provided in an embodiment of the present invention;

[0062] Figures 14 to 21 This is a schematic diagram illustrating the fabrication process of a transistor structure provided in an embodiment of the present invention.

[0063] icon:

[0064] 1-Substrate; 2-Transistor module; 21-First buffer layer; 22-First barrier layer; 23-First capping layer; S-Source; D-Drain; G-Gate; 24-Connection electrode; 25-Passivation layer; 26-Wire layer; L1-First connection line; L2-Second connection line; L3-Third connection line; L4-Fourth connection line; 3-Clamping module; 31-First clamping unit; 311-First sub-buffer layer; 312-First sub-barrier layer; 313-First sub-capping layer; 314-First electrode; 315-Second electrode; 316-Third electrode; A-Anode; C-Cathode; 32-Second clamping unit; 320-Sub-clamping unit; 321-Second sub-buffer layer; 322-Second sub-barrier layer; 323-Second sub-capping layer; 324-Fourth electrode; 325-Fifth electrode; 326-Sixth electrode. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Please refer to Figure 1 and Figure 2 The present invention provides a transistor structure, including a substrate 11 and a transistor module 2 and a clamping module 3 located on one side of the substrate 11, wherein there is an electrical isolation region between the transistor module 2 and the clamping module 3.

[0067] One side of substrate 1 has:

[0068] A buffer layer, located on substrate 1, includes a first buffer layer 21 located in transistor module 2 and a second buffer layer located in clamping module 3;

[0069] The barrier layer, located on the side of the buffer layer away from the substrate 1, includes a first barrier layer 22 located in the transistor module 2 and a second barrier layer located in the clamping module 3.

[0070] The capping layer, located on the side of the barrier layer away from the buffer layer, includes a first capping layer 23 located in the transistor module 2 and a second capping layer located in the clamping module 3;

[0071] The source S and drain D are located on the side of the barrier layer away from the buffer layer and are located in the transistor module 2. The source S and drain D are in ohmic contact with the first barrier layer 22. The first capping layer 23 is disposed between the source S and the drain D.

[0072] The connecting electrode 24 and the gate G are spaced apart on the side of the capping layer away from the barrier layer and located in the transistor module 2. The connecting electrode 24 is in ohmic contact with the first capping layer 23, and the gate G is in Schottky contact with the first capping layer 23.

[0073] Anode A and cathode C are located on the side of the barrier layer away from the buffer layer and are located in clamping module 3. Cathode C is electrically connected to gate G, and anode A is electrically connected to connecting electrode 24.

[0074] The clamping module 3 is used to clamp the voltage between the anode A and the cathode C within a preset regulated value.

[0075] In the transistor structure provided in this embodiment of the invention, the first buffer layer 21, the first barrier layer 22, the first capping layer 23, the source S, the drain D, the connecting electrode 24, and the gate G are located in the transistor module 2, while the second buffer layer, the second barrier layer, the second capping layer, the anode A, and the cathode C are located in the clamping module 3. The transistor module 2 and the clamping module 3 are fabricated in the same layer. A two-dimensional electron gas is formed at the interface of the heterojunction formed by the first buffer layer 21 and the first barrier layer 22 in the transistor module 2. The first capping layer 23 is used to deplete the two-dimensional electron gas at the interface of the heterojunction of the first buffer layer 21 and the first barrier layer 22. The gate G forms a Schottky contact with the first capping layer 23. The concentration of the two-dimensional electron gas at the interface of the heterojunction of the first buffer layer 21 and the first barrier layer 22 can be controlled by adjusting the voltage applied to the gate G, thereby controlling the on and off states of the source S and the drain D.

[0076] In this design, since the gate G of transistor module 2 is connected to the cathode C of clamping module 3, and the connecting electrode 24 of transistor module 2 is connected to the anode A of clamping module 3, when the voltage applied to the gate G exceeds a preset value, clamping module 3 can clamp the voltage on the gate G within a preset regulated value, preventing the voltage on the gate G from becoming too high and improving the working life of the gate G. Furthermore, since there is an ohmic contact between the connecting electrode 24 and the first capping layer 23, the traps that capture electrons in the first capping layer 23 will be quickly recombinated by the holes injected by the connecting electrode 24, which can avoid the problem of the traps in the first capping layer 23 capturing electrons and not being released in time. Therefore, the threshold voltage of the transistor structure no longer deviates, making the threshold voltage more stable, and ultimately improving the reliability of the gate G of the transistor structure.

[0077] In this embodiment of the invention, the clamping module 3 can be any two-port module that exhibits voltage regulation characteristics. There are no restrictions here, and it depends on the actual situation.

[0078] In the above transistor structure, if the gate of transistor module 2 is not connected to clamping module 3, the gate G of transistor module 2 can be equivalent to an anti-parallel connection of a Schottky diode (formed by the Schottky contact between the gate G and the first capping layer 23) and a PIN diode (formed by the heterojunction of the first capping layer 23, the first barrier layer 22 and the first buffer layer 21). When a voltage is applied to the gate G, the Schottky diode initially bears all the gate G voltage. When the PIN diode is turned on, the increased gate G voltage will also drop onto the reverse-biased Schottky diode until the gate G voltage causes the gate G to break down.

[0079] In the embodiments of the present invention, such as Figure 2 As shown, the gate G is in Schottky contact with the first capping layer 23, and the interface between the gate G and the first capping layer 23 can be equivalent to a Schottky diode D1; the heterostructure formed by the first capping layer 23, the first barrier layer 23, and the first buffer layer 31 can be equivalent to a PIN diode D2; the clamping module 3 can be equivalent to a Zener diode D3; therefore, in the transistor structure, the gate G structure can be equivalent to an anti-parallel connection of Schottky diode D1 and Zener diode D3. Thus, in the above transistor structure, the equivalent circuit of the gate can be as follows: Figure 3 As shown; Figure 4 The current-voltage characteristic curve of Zener diode D3 shows that when the voltage between the anode and cathode of Zener diode D3 exceeds the preset Zener voltage value Vz, the current in Zener diode D3 will increase sharply.

[0080] Specifically, when the voltage applied to the gate G increases from 0V to the preset regulated voltage value Vz, due to the voltage clamping characteristic of the Zener diode D3, the current in Zener diode D3 will increase dramatically, and correspondingly, the current in PIN diode D2 will also increase dramatically. Since the equivalent resistance of PIN diode D2 is greater than that of Zener diode D3, PIN diode D2 will bear a large voltage, thus limiting the voltage across the anode and cathode of Zener diode D3 to the preset regulated voltage value. In other words, the voltage across Schottky diode D1 will be limited to the preset regulated voltage value Vz, and the voltage on the gate G will also be limited to the preset regulated voltage value Vz. This prevents the voltage on the gate G from becoming too high and improves the operating life of the gate G. Compared with the prior art, the transistor structure provided in this embodiment of the invention can have a higher safe operating voltage.

[0081] Furthermore, since the connecting electrode 24 is in ohmic contact with the first capping layer 23, the structure of the clamping module 3, the connecting electrode 24, and the first capping layer 23 can be equivalent to a resistor R connected in parallel with the Schottky diode D1. The equivalent circuit of the transistor structure can be as follows: Figure 5 As shown, the holes injected into the first capping layer 23 by the gate G are no longer restricted by the Schottky junction formed at the metal-semiconductor interface and can be directly injected into the first capping layer 23. Therefore, the carriers captured by the defects of the first capping layer 23 can recombine in time, which can make the threshold voltage of the gate G of the transistor structure more stable.

[0082] In the transistor structure provided in this embodiment of the invention, the clamping module 3 may include a first clamping unit 31; wherein, the second buffer layer may include a first sub-buffer layer 311 located in the first clamping unit 31; the second barrier layer may include a first sub-barrier layer 312 located in the first clamping unit 31; the second capping layer may include a first sub-capping layer 313 located in the first clamping unit 31, and the first sub-capping layer 313 is spaced between the anode A and the cathode C;

[0083] In addition, the above-mentioned transistor structure may also include a first electrode 314, a second electrode 315, and a third electrode 316 located in the first clamping unit 31; the first electrode 314, the second electrode 315, the anode A, the cathode C, the source S, and the drain D are disposed on the same layer, the first electrode 314 is disposed at a distance from the anode A on the side away from the first sub-capping layer 313, the second electrode 315 is disposed at a distance from the cathode C on the side away from the first sub-capping layer 313, and the first electrode 314 and the second electrode 315 are in ohmic contact with the first sub-barrier layer 312; the third electrode 316 is disposed on the same layer as the gate G, the third electrode 316 is in Schottky contact with the first sub-capping layer 313, and the third electrode 316 is electrically connected to the first electrode 314 and the second electrode 315;

[0084] The first sub-buffer layer 311, the second sub-barrier layer 322, the first sub-cap layer 313, the anode A, the cathode C, the first electrode 314, the second electrode 315 and the third electrode 316 constitute the first clamping unit 31.

[0085] Specifically, in the first clamping unit 31, the first sub-buffer layer 311, the first sub-barrier layer 312, the first sub-capping layer 313, the first electrode 314, the second electrode 315, and the third electrode 316 form the structure of an enhancement-mode transistor. A two-dimensional electron gas is formed at the interface of the heterojunction formed by the first sub-buffer layer 311 and the first sub-barrier layer 312. The first sub-capping layer 313 is used to deplete the two-dimensional electron gas at the interface of the heterojunction between the first sub-buffer layer 311 and the first sub-barrier layer 312. The voltage on the third electrode 316 can control the concentration of the two-dimensional electron gas at the interface of the heterojunction between the second buffer layer 311 and the second barrier layer 312, thereby controlling the conduction and cutoff between the first electrode 314 and the second electrode 315.

[0086] like Figure 6 As shown, since the first electrode 314 and anode A are in ohmic contact with the first sub-barrier layer 312, the connection between anode A and the first electrode 314 can be equivalent to a connection through the first resistor R1; since the second electrode 315 and cathode C are in ohmic contact with the first sub-barrier layer 312, the connection between cathode C and the second electrode 315 can be equivalent to a connection through the second resistor R2; therefore, the equivalent circuit of the first clamping unit 31 can be as follows: Figure 7 As shown, the equivalent circuit structure has Zener diode characteristics. The equivalent circuit includes a first resistor R1, a second resistor R2, and an enhancement-mode transistor M.

[0087] The aforementioned clamping module 3 can be a first clamping unit 31, which is fabricated on the same layer as the transistor module 2; for example Figure 1 As shown, when the voltage V between the cathode C and the anode A on the first clamping unit 31... AC When the voltage starts to rise from 0V, the resistor R1 and the resistor R2 connected in series share the voltage V across the cathode C and the anode A. AC Since this voltage is less than the threshold voltage VTH of the enhancement-mode transistor M, the enhancement-mode transistor M remains off. The current between the anode A and cathode C of the first clamping unit 31 is determined only by the values ​​of the first resistor R1 and the second resistor R2. At this time, the equivalent circuit of the transistor structure can be as follows: Figure 5 As shown; when V ACWhen R2 / (R1+R2) exceeds the threshold voltage VTH of the enhancement-mode transistor M, the enhancement-mode transistor M begins to conduct. At this time, the current between the anode A and cathode C of the first clamping unit 31 is dominated by the current through the enhancement-mode transistor M. The current-voltage characteristic of the first clamping unit 31 then exhibits characteristics similar to that of a Zener diode. The first clamping unit 31 can clamp the voltage on the gate G at a preset regulated voltage value Vz. The preset regulated voltage value Vz between the anode A and cathode C of the first clamping unit 31 is V... AC R2 / (R1+R2) equals VTH. The equivalent circuit of the transistor structure can be represented as follows: Figure 3 As shown.

[0088] In embodiments of the present invention, such as Figure 8 As shown, the clamping module 3 may further include a second clamping unit 32, which includes N sub-clamping units 320, where N is an integer greater than or equal to 1; wherein, the second buffer layer includes a second sub-buffer layer 321 located in the sub-clamping unit 320; the second barrier layer includes a second sub-barrier layer 322 located in the sub-clamping unit 320; and the second cap layer includes a second sub-cap layer 323 located in the sub-clamping unit 320.

[0089] In addition, the above-mentioned transistor structure also includes a fourth electrode 324, a fifth electrode 325, and a sixth electrode 326 located in the sub-clamping unit 320; the fourth electrode 324 and the fifth electrode 325 are disposed on the same layer as the source S and the drain D, the fourth electrode 324 and the fifth electrode 325 are located on both sides of the second sub-capping layer 323 and are in ohmic contact with the second sub-barrier layer 322, and the fifth electrode 325 is disposed at a distance from the second sub-capping layer 323; the sixth electrode 326 is disposed on the same layer as the gate G, the sixth electrode 326 is in Schottky contact with the second sub-capping layer 323, and is in ohmic contact with the second sub-barrier layer 322 through the fourth electrode 324;

[0090] In the transistor structure described above, the second sub-buffer layer 321, the second sub-barrier layer 322, the second sub-capping layer 323, the fourth electrode 324, the fifth electrode 325, and the sixth electrode 326 form a sub-clamping unit 320, and N sub-clamping units 320 form a second clamping unit 32.

[0091] When N=1, the sixth electrode 326 of the sub-clamping unit 320 can be the cathode C of the second clamping unit 32, and the fifth electrode 325 of the sub-clamping unit 320 can be the anode A of the second clamping unit 32.

[0092] When N≥2, the second sub-buffer layer 321 and the second sub-barrier layer 322 of each sub-clamping unit 320 are electrically isolated. The N sub-clamping units 320 are connected in series. The sixth electrode 326 of the first sub-clamping unit 320 can be the cathode C of the second clamping unit 32. The fifth electrode 325 of the (N-1)th sub-clamping unit 320 is connected to the sixth electrode 326 of the Nth sub-clamping unit 320. The fifth electrode 325 of the Nth sub-clamping unit 320 can be the anode A of the second clamping unit 32.

[0093] In the sub-clamping unit 320, a two-dimensional electron gas is formed at the interface of the heterojunction formed by the second sub-buffer layer 321 and the second sub-barrier layer 322. The second sub-capping layer 323 is used to deplete the two-dimensional electron gas at the interface of the heterojunction between the second sub-buffer layer 321 and the second sub-barrier layer 322. The conduction and cutoff states of the sub-clamping unit 320 can be controlled by controlling the voltage between the sixth electrode 326 and the fifth electrode 325. The sub-clamping unit 320 can be equivalent to a diode, and the threshold voltage of the sub-clamping unit 320 can be VON.

[0094] Specifically, the clamping module 3 can be a second clamping unit 32, in which N sub-clamping modules 320 are fabricated on the same layer as the transistor module 2. When the second clamping unit 32 includes a sub-clamping unit 320, i.e., N=1, after the voltage between the anode and cathode of the second clamping unit 32 reaches VON, the voltage-current characteristic of the sub-clamping unit 320 exhibits a voltage-current characteristic similar to that of a Zener diode, and can clamp the voltage on the gate G at Vz equal to VON.

[0095] When the second clamping unit 32 includes at least two sub-clamping units 320, i.e., N≥2, the equivalent circuit of the second clamping unit 32 can be N diodes D4 connected in series, such as... Figure 9 As shown; when the voltage between the anode A and cathode C of the second clamping unit 32 reaches N×VON, the voltage-current characteristic of the second clamping unit 32 exhibits characteristics similar to those of a Zener diode, and can clamp the voltage on the gate G at a preset regulated voltage value Vz, which is equal to N×VON, thereby increasing the safe operating voltage of the transistor structure.

[0096] In this embodiment of the invention, the clamping module 3 may include only the first clamping unit 31; or only the second clamping unit 32; or both the first clamping unit 31 and the second clamping unit 32.

[0097] For example, the clamping module 3 may include a first clamping unit 31 and a second clamping unit 32; wherein, the anode A of the first clamping unit 31 is the anode A of the clamping module 3, the cathode C of the first clamping unit 31 is the cathode C of the clamping module 3, the third electrode 316 of the first clamping unit 31 is connected to the first electrode 314 through the second clamping unit 32, the cathode C of the second clamping unit 32 is connected to the third electrode 316, and the anode A of the second clamping unit 32 is connected to the first electrode 314.

[0098] The equivalent circuit of the clamping module 3 described above can be as follows: Figure 10 As shown, the device includes an enhancement-mode transistor M and N diodes D4. The current-voltage characteristic of the first clamping unit 31 is similar to that of a Zener diode, and the current-voltage characteristic of the second clamping unit 32 is similar to that of a Zener diode. Therefore, the current-voltage characteristic of the clamping module 3 can also exhibit characteristics similar to those of a Zener diode. The threshold voltage of the first clamping unit 31 is VTH, and the threshold voltage of the second clamping unit 32 is N×VON. Therefore, the preset regulated voltage Vz between the anode and cathode of the clamping module 3 is VTH+N×VON.

[0099] In embodiments of the present invention, such as Figure 11 , Figure 12 and Figure 13 As shown, the transistor structure may also include a passivation layer 25 and a wiring layer 26; the passivation layer 25 may be located on the side of the gate G and the connection electrode 24 away from the substrate 1; the wiring layer 26 is located on the side of the passivation layer 25 away from the substrate 1, and the wiring layer 26 may include a first connection line L1 and a second connection line L2.

[0100] The cathode C of the clamping module 3 can be connected to the gate G of the transistor module 2 via the first connection line L1, and the anode A of the clamping module 3 can be connected to the connection electrode 24 of the transistor module 2 via the second connection line L2.

[0101] When the clamping module 3 includes the first clamping unit 31, the wiring layer 26 also includes the third connecting wiring L3 and the fourth connecting wiring L4. The first electrode 314 and the third electrode 316 of the first clamping unit 31 can be connected through the third connecting wiring L3, and the second electrode 315 and the third electrode 316 of the first clamping unit 31 can be connected through the fourth connecting wiring L4.

[0102] Specifically, the passivation layer 25 can protect the source S, drain D, gate G, connecting electrode 24, first electrode 314, second electrode 315, third electrode 316, fourth electrode 324, fifth electrode 325 and sixth electrode 326 in the transistor structure, and facilitate the wiring of the wiring layer 26.

[0103] In this embodiment of the invention, the material of the gate G is different from the material of the connecting electrode 24, so that the gate G is in Schottky contact with the first capping layer 23 and the connecting electrode 24 is in Ohmic contact with the first capping layer 23.

[0104] Specifically, the material of the gate G can be at least one of titanium nitride (TiN), titanium (Ti), nickel (Ni) and gold (Au). For example, the material of the gate G can be titanium nitride, nickel / gold alloy, or titanium / gold alloy, etc. There are no restrictions here, and it depends on the actual situation.

[0105] The material of the connecting electrode 24 can be at least one of nickel (Ni), gold (Au) and titanium (Ti). For example, the material of the connecting electrode 24 can be a nickel / gold alloy or a titanium / gold alloy, etc. There are no restrictions here, and it depends on the actual situation.

[0106] Specifically, the materials of the source electrode S and the drain electrode D can include at least one of titanium, aluminum, gold, nickel and titanium nitride. For example, the materials of the source electrode S and the drain electrode D can be titanium / aluminum / gold alloy, titanium / aluminum / nickel / gold alloy or titanium nitride / titanium / aluminum alloy, etc. There are no restrictions here, and it depends on the actual situation. The source electrode S and the drain electrode D can be formed by fabrication in multiple layers.

[0107] Specifically, the material of the buffer layer may include gallium nitride (GaN), the material of the barrier layer may include aluminum gallium nitride (AlGaN), and the material of the capping layer may include p-type gallium nitride (p-GaN).

[0108] Alternatively, the buffer layer can be a C-doped GaN layer with a C concentration between 1e⁻¹ and 1e⁻¹. 19 -1e 20 It can also be a superlattice structure composed of one or more of AlN, AlGaN, and GaN.

[0109] Specifically, the buffer layer may include multiple sub-film layers stacked sequentially on the substrate 1; the sub-film layer on the side of the buffer layer away from the substrate 1 may be a channel layer, and the channel layer and the barrier layer form a heterogeneous structure.

[0110] In this embodiment of the invention, an insertion layer is provided between the buffer layer and the barrier layer. The material of the insertion layer includes aluminum nitride. The insertion layer located in the transistor module 2 is electrically isolated from the insertion layer located in the clamping module 3. The insertion layer can improve the confinement of the two-dimensional electron gas (2DEG) and increase the electron mobility.

[0111] In this embodiment of the invention, the electrical isolation region between the transistor module 2 and the clamping module 3 is achieved by ion implantation or trench etching.

[0112] Specifically, electrical isolation between the first buffer layer 21 and the second buffer layer, or between the first barrier layer 22 and the second barrier layer, is achieved through ion implantation or trench etching, resulting in a simple and easy-to-implement structure.

[0113] In embodiments of the present invention, such as Figures 11 to 13 The diagram shown is a planar structural schematic of the transistor structure when the clamping module 3 includes the first clamping unit 31. The specific fabrication steps of this transistor structure can include the following steps:

[0114] S1: Patterning of the capping layer on the epitaxial wafer to form a first capping layer 23 and a first sub-capping layer 313, such as... Figure 14 As shown, the epitaxial wafer includes a substrate 1, a buffer layer 201, a barrier layer 202, and a capping layer formed sequentially on the substrate 1.

[0115] Specifically, hard masks are used to etch the capping layer on the epitaxial wafer using methods such as ICP and RIE;

[0116] The substrate 1 can be made of materials such as Si, SiC, or sapphire; the buffer layer 201 can be made of GaN; the barrier layer 202 can be made of AlGaN; the capping layer can be made of p-GaN; and the Mg doping concentration in the capping layer 203 can be in the range of 5 × 10⁻⁶. 18 ~10×10 19 cm -3 .

[0117] S2: Divide the entire buffer layer 201 and barrier layer 202 to form a first buffer layer 21, a first sub-buffer layer 311, a first barrier layer 22, and a first sub-barrier layer 312, as shown. Figure 15 As shown;

[0118] Specifically, the buffer layer 201 and the barrier layer 202 are separated by ion implantation or ICP etching.

[0119] S3: Forms a structure consisting of source S, drain D, first electrode 314, second electrode 315, anode A, and cathode C, as follows: Figure 16 As shown;

[0120] Specifically, a metal stack is grown and RTP annealed in an N2 atmosphere to generate a source electrode S, a drain electrode D, a first electrode 314, a second electrode 315, an anode A, and a cathode C;

[0121] The metal stack can include a combination of various III / V group compound ohmic metals such as Ti / Al / Ti / Au, Ti / Al / Ni / Au, or TiN / Al / Ti / TiN.

[0122] S4: Form connecting electrode 24, such as Figure 17 As shown;

[0123] Specifically, a metal stack is grown on the capping layer 203 and RTP annealed in an O2 atmosphere to generate a connecting electrode 24. The material of the connecting electrode 24 can be a Ni / Au alloy, Ti / Au alloy, etc.

[0124] S5: Forms the gate G and the third electrode 316, such as Figure 18 As shown;

[0125] Specifically, a metal stack is grown on the capping layer 203 to form a gate G and a third electrode 316. The materials of the gate G and the third electrode 316 can be TiN, Ni / Au alloy, Ti / Au alloy, etc.

[0126] S6: Form a passivation layer 25, such as Figure 19 As shown; wherein, the material of the passivation layer 25 can be SiN or SiO2, and the passivation layer 25 can be multilayered.

[0127] S7: Create a hole in the passivation layer 25, such as Figure 20 As shown, the aperture can be created using a combination of dry etching and wet etching.

[0128] S8: A routing layer 26 is formed on the passivation layer 25, forming a first connection trace L1, a second connection trace L2, a third connection trace L3, and a fourth connection trace L4, as follows: Figure 21 As shown, the wiring layer 26 is connected to the source S, drain D, gate G, connecting electrode 24, first electrode 314, second electrode 315, third electrode 316, anode A, and cathode C through the openings on the passivation layer 25.

[0129] In the above-described transistor structure fabrication steps, transistor module 2 and clamping module 3 are fabricated on the same layer, which simplifies the transistor structure fabrication steps and saves manufacturing costs.

[0130] In addition, when the clamping module 3 includes the second clamping unit 32, the specific fabrication steps of the transistor structure are similar to the above-mentioned fabrication steps, and the transistor module 2 and the clamping module 3 are fabricated on the same layer.

[0131] The present invention also includes an electronic device comprising any of the transistor structures provided in the above-described technical solutions.

[0132] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A transistor structure, characterized in that, It includes a substrate and a transistor module and a clamping module located on one side of the substrate, wherein there is an electrical isolation region between the transistor module and the clamping module; One side of the substrate has: A buffer layer, located on the substrate, includes a first buffer layer located on the transistor module and a second buffer layer located on the clamping module; A barrier layer, located on the side of the buffer layer away from the substrate, includes a first barrier layer located in the transistor module and a second barrier layer located in the clamping module; A capping layer, located on the side of the barrier layer away from the buffer layer, includes a first capping layer located within the transistor module and a second capping layer located within the clamping module; The source and drain are located on the side of the barrier layer away from the buffer layer and in the transistor module. The source and drain are in ohmic contact with the first barrier layer. The first capping layer is disposed between the source and the drain. A connecting electrode and a gate are spaced apart on the side of the capping layer away from the barrier layer and located in the transistor module. The connecting electrode is in ohmic contact with the first capping layer, and the gate is in Schottky contact with the first capping layer. The anode and cathode are located on the side of the barrier layer away from the buffer layer and in the clamping module. The cathode is electrically connected to the gate, and the anode is electrically connected to the connecting electrode. The clamping module is used to clamp the voltage between the anode and the cathode within a preset regulated value.

2. The transistor structure according to claim 1, characterized in that, The clamping module includes a first clamping unit; wherein... The second buffer layer includes a first sub-buffer layer located in the first clamping unit; The second barrier layer includes a first sub-barrier layer located in the first clamping unit; The second cap layer includes a first sub-cap layer located in the first clamping unit, the first sub-cap layer being disposed at a distance between the anode and the cathode; It also includes a first electrode, a second electrode, and a third electrode located in the first clamping unit; The first electrode, the second electrode, the anode, the cathode, the source, and the drain are disposed in the same layer. The first electrode is disposed at a distance from the anode on the side away from the first sub-capping layer. The second electrode is disposed at a distance from the cathode on the side away from the first sub-capping layer. The first electrode and the second electrode are in ohmic contact with the first sub-barrier layer. The third electrode is disposed on the same layer as the gate, the third electrode is in Schottky contact with the first sub-cap layer, and the third electrode is electrically connected to the first electrode and the second electrode.

3. The transistor structure according to claim 1 or 2, characterized in that, The clamping module includes a second clamping unit, which comprises N sub-clamping units, where N is an integer greater than or equal to 1; wherein, The second buffer layer includes a second sub-buffer layer located in the sub-clamping unit; The second barrier layer includes a second sub-barrier layer located in the sub-clamping unit; The second cap layer includes a second sub-cap layer located in the sub-clamping unit; It also includes a fourth electrode, a fifth electrode, and a sixth electrode located in the sub-clamping unit; The fourth electrode and the fifth electrode are disposed in the same layer as the source and drain electrodes. The fourth electrode and the fifth electrode are located on both sides of the second sub-capping layer and are in ohmic contact with the second sub-barrier layer. The fifth electrode is disposed at a distance from the second sub-capping layer. The sixth electrode is disposed in the same layer as the gate, the sixth electrode is in Schottky contact with the second sub-capping layer, and is in Ohmic contact with the second sub-barrier layer through the fourth electrode; When N=1, the sixth electrode of the sub-clamping unit is the cathode of the second clamping unit, and the fifth electrode of the sub-clamping unit is the anode of the second clamping unit; When N≥2, the second sub-buffer layer and the second sub-barrier layer of each sub-clamping unit are electrically isolated. The N sub-clamping units are connected in series in sequence. The sixth electrode of the first sub-clamping unit is the cathode of the second clamping unit. The fifth electrode of the (N-1)th sub-clamping unit is connected to the sixth electrode of the Nth sub-clamping unit. The fifth electrode of the Nth sub-clamping unit is the anode of the second clamping unit.

4. The transistor structure according to claim 3, characterized in that, The clamping module includes a first clamping unit and a second clamping unit; The anode of the first clamping unit is the anode of the clamping module, and the cathode of the first clamping unit is the cathode of the clamping module; The third electrode of the first clamping unit is connected to the first electrode through the second clamping unit, the cathode of the second clamping unit is connected to the third electrode, and the anode of the second clamping unit is connected to the first electrode.

5. The transistor structure according to claim 1, characterized in that, It also includes a passivation layer and a wiring layer; The passivation layer is located on the side of the gate and connection electrode facing away from the substrate; The wiring layer is located on the side of the passivation layer away from the substrate, and the wiring layer includes a first connection line and a second connection line; The cathode of the clamping module is connected to the gate via a first connecting line, and the anode of the clamping module is connected to the connecting electrode via a second connecting line.

6. The transistor structure according to claim 1, characterized in that, The material of the gate is different from the material of the connecting electrode.

7. The transistor structure according to claim 6, characterized in that, The buffer layer is made of gallium nitride, the barrier layer is made of aluminum gallium nitride, and the capping layer is made of p-type gallium nitride.

8. The transistor structure according to claim 1, characterized in that, The source and drain electrodes are made of at least one of titanium, aluminum, gold, nickel, and titanium nitride. The gate material includes at least one of titanium nitride, titanium, nickel, and gold; The material of the connecting electrode includes at least one of nickel, gold, and titanium.

9. The transistor structure according to claim 1, characterized in that, The buffer layer comprises multiple sub-film layers sequentially stacked on a substrate; The sub-film layer on the side of the buffer layer away from the substrate is a channel layer, and the channel layer and the barrier layer form a heterostructure.

10. The transistor structure according to claim 1, characterized in that, An insertion layer is provided between the buffer layer and the barrier layer. The material of the insertion layer includes aluminum nitride. The insertion layer located in the transistor module is electrically isolated from the insertion layer located in the clamping module.

11. The transistor structure according to claim 1, characterized in that, The electrical isolation between the transistor module and the clamping module is achieved by ion implantation or trench etching.

12. An electronic device, characterized in that, Includes the transistor structure as described in any one of claims 1-11.

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