A semiconductor device

Abstract

The application provides a semiconductor device, which comprises: a drift region of a first conductive type; a body region of a second conductive type, which is arranged in the drift region; a plurality of closed hexagonal trenches; the cross section of each hexagonal trench is a closed hexagonal contour; the hexagonal trench is filled with a conductive material and is electrically isolated from other structures of the semiconductor device; the hexagonal trenches are arranged adjacent to each other, and the adjacent edges of the adjacent hexagonal trenches are parallel to each other; a source region of a highly doped first conductive type, which is embedded in the body region and is located between the adjacent edges of the adjacent hexagonal trenches; and a contact region, which is arranged in the source region and is connected with a source electrode or an emitter electrode. The semiconductor device adopts a closed hexagonal unit form for the arrangement of the gate trench, and the active region is located between the adjacent hexagonal units. The layout can improve the power density, improve the controllability of the switch, and enhance the adjustability of the design.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device. Background Technology

[0002] Semiconductor power devices with trench gate structures include trench metal-oxide-semiconductor field-effect transistors (MOSFETs) and trench insulated-gate bipolar transistors (IGBTs). These devices have a gate contact that is electrically isolated from the rest of the transistor by a suitable insulating material (e.g., silicon dioxide) to control the device and switch it from a blocking state to a conducting state, or vice versa. The gate is formed in a trench region formed by processes such as etching. A highly conductive region, often called the source, is surrounded by the gate trench and contacts the main top metallization layer of the device. This allows the formation of a channel region in which charge carriers can flow, thereby conducting current. Key performance parameters for such power devices include the power loss generated during switching from a blocking state to a conducting state (or vice versa) under load, as well as the power loss generated during the conducting phase. However, many other design considerations exist, such as the controllability of the switching phase, dynamic overvoltages, and the robustness of the device to severe switching events or short-circuit events. To achieve appropriate performance in a given application, the device must be optimized within a wide design space.

[0003] Devices such as MOSFETs, IGBTs, or similar devices with active regions comprising multiple trench structures. The device includes a semiconductor substrate of a first conductivity type, with a region of a second conductivity type (body region) within which a highly doped region of the first conductivity type (source region) is formed. In some embodiments of the device, another layer of the first conductivity type (reinforcement region) may be included beneath the body region. Deep trenches are formed on either side of the body region and electrically isolated from the rest of the semiconductor material by a layer of insulating material (such as silicon dioxide). These trenches are then filled with a conductive material and connected to the gate electrode. Contacts may also be formed in the body region and connected to the emitter or source potential of the device. By adjusting the voltage on the gate electrode, the device can switch from an on state to an off state and vice versa. In the prior art, trenches are formed into stripes (such as US Patent Publication No. US8633510B2 and Chinese Patent Publication No. CN102044565A) or a grid layout, where a stripe or a square can be referred to as a unit. Examples of stripe layouts in the prior art are as follows: Figure 1 As shown in a and b, an example of a grid cell layout is as follows. Figure 1As shown in Figure c, the stripe pattern is the simplest possible way to combine a series of active cells to form the active region of a device, but this concept presents several challenges in terms of manufacturability and device performance. First, because wafers are typically fabricated to be very thin, they are highly sensitive to mechanical stress. When etching deep trenches with a stripe pattern into the wafer, all long trenches extend in the same direction on both the device and the wafer. When the trench density is too high, the wafer may begin to warp (or bend, deform), posing a challenge to wafer handling and limiting both trench density and channel density on the wafer. Second, signals are transmitted through relatively thin and resistive material in the trenches, which may degrade the switching performance of the device, and two adjacent trenches may not be tightly coupled, resulting in asymmetrical channel regions. Third, a contact region must be formed between the two gate trenches on the active mesa, which is a limitation of the mesa boundary size. Figure 1 While the mesh layout shown in Figure c solves some of the problems, particularly achieving better coupling between two adjacent trenches, manufacturability issues remain. Furthermore, because adjacent trenches are interconnected, it is not easy to incorporate dummy emitter bias trenches into the mesh layout, requiring considerable additional design effort. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor device in which the gate trench is arranged in the form of closed hexagonal cells and the active region is located between adjacent hexagonal cells. This layout can improve power density and switching controllability, and enhance the adjustability of the design.

[0005] To address the above problems, the present invention provides a semiconductor device comprising:

[0006] Drift region of the first conductivity type;

[0007] A body region of the second conductivity type is disposed within the drift region;

[0008] Multiple closed first regular hexagonal trenches extend from the upper surface of the semiconductor device into the body region; each first regular hexagonal trench has a closed regular hexagonal profile in cross-section; the first regular hexagonal trenches are filled with a conductive material, and the conductive material is electrically isolated from other structures of the semiconductor device through a dielectric layer; the conductive material is connected to a gate electrode; the first regular hexagonal trenches are arranged adjacent to each other, and the adjacent sides of adjacent first regular hexagonal trenches are parallel to each other;

[0009] A highly doped source region of the first conductivity type is embedded within the body region, and the source region is located between adjacent sides of an adjacent first regular hexagonal trench.

[0010] A contact region is provided in the source region, and the contact region is connected to the source electrode or the emitter electrode.

[0011] Preferably, it further includes: a first conductivity type enhancement region disposed below the body region; the first regular hexagonal trench extends from the upper surface of the semiconductor device into the body region and the enhancement region.

[0012] Preferably, the spacing between adjacent first regular hexagonal grooves includes a first spacing and a second spacing, the second spacing being greater than the first spacing, and the contact area is provided only between adjacent first regular hexagonal grooves with a spacing of the second spacing.

[0013] Preferably, in the region between adjacent first regular hexagonal grooves with a spacing of the second spacing, the source region does not extend to the adjacent first regular hexagonal grooves on both sides in the width direction; or in the region between adjacent first regular hexagonal grooves with a spacing of the second spacing, no source region is provided, only a contact region is provided, and the contact region is connected to the source region between adjacent first regular hexagonal grooves with a spacing of the first spacing.

[0014] Preferably, adjacent first hexagonal trenches are interconnected by an additional conductive layer, orthogonal trenches, or a combination of both, to transmit gate signals; the conductive layer is disposed above the body semiconductor material; the orthogonal trenches extend from the upper surface of the semiconductor device into the body region, and there are one or more orthogonal trenches; in the region where the conductive layer is disposed, the contact region is interrupted; in the region where the orthogonal trenches are disposed, the source region is interrupted, and no contact region is disposed.

[0015] Preferably, at least one first regular hexagonal trench surrounds a highly doped first floating p-well region of a second conductivity type, the depth of the first floating p-well region being greater than the depth of the first regular hexagonal trench, and the first floating p-well region being not electrically connected to the electrode.

[0016] Preferably, at least one first regular hexagonal trench has an emitter contact or a source contact inside.

[0017] Preferably, the source region is interrupted in any proportion. Similar to the appendix... Figure 1 As shown in Figure b, multiple interruption regions are provided in the middle of the source region to control the injection and reduce the short-circuit current. The ratio of the length of the interruption region to the length of the source region can be adjusted arbitrarily.

[0018] Preferably, at least one of the first regular hexagonal trenches has a second regular hexagonal trench inside; the cross-section of the second regular hexagonal trench is a closed regular hexagonal outline; the second regular hexagonal trench is concentric with the first regular hexagonal trench, and its side length is smaller than that of the first regular hexagonal trench; the side of the second regular hexagonal trench is parallel to the side of the first regular hexagonal trench; the second regular hexagonal trench extends from the upper surface of the semiconductor device into the body region and the reinforcement region.

[0019] Preferably, in at least one of the first regular hexagonal trenches, a second floating P-trap region is further provided in the region between the first regular hexagonal trench and the second regular hexagonal trench or in the region enclosed by the second regular hexagonal trench.

[0020] Preferably, in at least one of the first regular hexagonal trenches, an emitter contact or a source contact is provided in the region between the first regular hexagonal trench and the second regular hexagonal trench where the second floating P-well region is not provided, or in the region enclosed by the second regular hexagonal trench where the second floating P-well region is not provided.

[0021] Preferably, at least one of the second regular hexagonal trenches in the first regular hexagonal trench is connected to the emitter or source potential.

[0022] Preferably, the second regular hexagonal groove is in a floating state.

[0023] Preferably, the side lengths of each of the first regular hexagonal grooves are the same.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] The semiconductor device of the present invention includes gate trenches arranged not in a stripe or grid pattern, but in the form of closed hexagonal cells, with active regions located between adjacent hexagonal cells. The hexagonal cells can be closely arranged within the desired region to conduct specific currents. Compared to striped gate trenches, hexagonal gate trenches significantly reduce the total length of a single trench, and under given geometric constraints, the hexagonal layout achieves the highest channel density. Comparing the hexagonal gate trench arrangement with the striped arrangement, the hexagonal layout provides more active regions per unit area for the same active and inactive mesa dimensions.

[0026] Because wafers are typically fabricated to be very thin, they are highly sensitive to mechanical stress. A limitation of etching deep trenches into wafers is that when the trench density is too high, the wafer may begin to warp (or bend, deform). The semiconductor device of this invention, in which several regular hexagonal trenches are uniformly etched into the semiconductor material in different directions, greatly alleviates stress in the material.

[0027] The semiconductor device of this invention employs regular hexagonal gate trenches, allowing for more uniform distribution of the gate signal, and through appropriate layout, all trenches can be better coupled together. This offers significant advantages for very fast switching designs. Attached Figure Description

[0028] Figure 1 These are top views of conventional trench devices with striped layouts in the prior art, where a is a top view of a conventional trench device with striped layouts that includes a floating P-well region; b is a top view of a conventional trench device with striped layouts that includes a floating P-well region and an interrupt source region; and c is a top view of a conventional trench device with striped layouts that includes a floating P-well region, an interrupt source region, and a virtual trench.

[0029] Figure 2 This is a schematic diagram of the semiconductor device according to Embodiment 1 of the present invention, wherein a is a top view of the semiconductor device according to Embodiment 1 of the present invention; b is a longitudinal cross-sectional view obtained along the tangent line drawn in a (not drawn according to the relative proportions of the structure in a).

[0030] Figure 3 These are top views of the semiconductor device according to Embodiment 2 of the present invention, wherein a is a top view of an example of the semiconductor device according to Embodiment 2 of the present invention; and b is a top view of another example of the semiconductor device according to Embodiment 2 of the present invention.

[0031] Figure 4 These are top views of the semiconductor device according to Embodiment 4 of the present invention, wherein a is a top view of an example of the semiconductor device according to Embodiment 4 of the present invention; and b is a top view of another example of the semiconductor device according to Embodiment 4 of the present invention.

[0032] Figure 5 This is a schematic diagram of a semiconductor device according to Embodiment 3 of the present invention, wherein a is a top view of an example structure of the semiconductor device according to Embodiment 3 of the present invention; b and c are longitudinal cross-sectional views obtained by drawing tangents along the lines shown in a;

[0033] Figure 6 This is a schematic diagram of another example of the semiconductor device according to Embodiment 3 of the present invention, wherein a is a top view of another example structure of the semiconductor device according to Embodiment 3 of the present invention; b is a top view of an example structure of Embodiment 3 with a higher proportion of orthogonal trenches;

[0034] Figure 7 This is a schematic diagram of a third example of the semiconductor device according to Embodiment 3 of the present invention, wherein a is a top view of the third example structure of the semiconductor device according to Embodiment 3 of the present invention; b is a longitudinal section view obtained by drawing a tangent line shown in a;

[0035] Figure 8 This is a schematic diagram of an example structure of Embodiment 5 of the present invention, where a is a top view of an example structure of Embodiment 5 of the present invention; b is a longitudinal section view obtained by drawing the tangent line shown in a;

[0036] Figure 9 This is a schematic diagram of an example structure of Embodiment 6 of the present invention, where a is a top view of an example structure of Embodiment 6 of the present invention; b is a longitudinal section view obtained by drawing the tangent line shown in a;

[0037] Figure 10 This is a top view of the semiconductor device according to Embodiment 7 of the present invention, wherein a is a top view of an example of the semiconductor device according to Embodiment 7 of the present invention, and b is a top view of another example of the semiconductor device according to Embodiment 7 of the present invention.

[0038] Figure 11 This is a schematic diagram of another structural example of Embodiment 7 of the present invention, wherein a is a top view of another structural example of Embodiment 7 of the present invention, and b is a longitudinal section view obtained by drawing the tangent line shown in a.

[0039] Figure 12 A comparison of gate trenches arranged in regular hexagons and stripes;

[0040] Figure 13 These are top views of two examples of semiconductor devices in Embodiment 2 of the present invention, wherein a is a top view of one example of a semiconductor device in Embodiment 2 of the present invention, and b is a top view of another example of a semiconductor device in Embodiment 2 of the present invention.

[0041] Wherein: 1-body region; 2-reinforcement region; 3-first regular hexagonal trench; 4-source region; 5-contact region; 6-active region; 7-conductive layer; 8-orthogonal trench; 9-first floating p-well region; 10-emitter contact or source contact; 11-second regular hexagonal trench; 12-second floating p-well region; 13-emitter contact or source contact; 14-emitter / source contact; 15-emitter contact; 16-inactive region. Detailed Implementation

[0042] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. Example 1

[0043] like Figure 2 In this embodiment, a is a top view of the semiconductor device. Figure 2b is Figure 2 The longitudinal section view obtained by drawing the tangent line along the middle a (not in accordance with Figure 2 (Draw the relative proportions of the structure of 'a' in the middle).

[0044] A semiconductor device according to this embodiment includes:

[0045] Drift region of the first conductivity type;

[0046] The second type of conductivity, body region 1, is located within the drift region;

[0047] The first type of conductivity enhancement region 2 is located below the body region 1;

[0048] Multiple closed first regular hexagonal trenches 3 of the same size extend from the upper surface of the semiconductor device into the body region 1 and the enhancement region 2; the cross-section of each first regular hexagonal trench 3 is a closed regular hexagonal profile; the first regular hexagonal trenches 3 are filled with conductive material, and the conductive material is electrically isolated from other structures of the semiconductor device through a dielectric layer; the conductive material is connected to the gate electrode; the first regular hexagonal trenches 3 are arranged adjacent to each other, and the adjacent sides of adjacent first regular hexagonal trenches 3 are parallel to each other;

[0049] A highly doped source region 4 of the first conductivity type is embedded in the body region 1, and the source region 4 is located between adjacent sides of an adjacent first regular hexagonal trench 3.

[0050] Contact region 5 is located in source region 4 and is connected to source or emitter electrode.

[0051] In this embodiment of the semiconductor device, the gate trenches are not arranged in a stripe or grid pattern, but rather in the form of closed hexagonal cells, with the active region 6 located between adjacent hexagonal cells. The hexagonal cells can be closely arranged within the desired region to conduct specific currents. Compared to stripe-arranged gate trenches, hexagonal-arranged gate trenches significantly reduce the total length of a single trench, and under given geometric constraints, the hexagonal layout achieves the highest channel density. Figure 12 As shown, when comparing gate trenches arranged in a regular hexagonal pattern with those arranged in stripes, the hexagonal layout has more active areas per unit area when the active and inactive mesa sizes are the same.

[0052] Because wafers are typically fabricated to be very thin, they are highly sensitive to mechanical stress. When etching deep trenches into a wafer, excessive trench density can cause the wafer to warp (or bend, deform), which is a limitation. In the semiconductor device of this embodiment, several regular hexagonal trenches are uniformly etched into the semiconductor material in different directions, greatly alleviating stress in the material.

[0053] In the semiconductor device of this embodiment, a regular hexagon gate trench is adopted, and the gate signal can be more evenly distributed. The gate signal is input into the gate trench through the gate trace structure. Generally, not too many gate trace structures are arranged on the chip because this will reduce the effective area. In the classic strip layout, the coupling between adjacent trenches is very weak because the gate signal has to propagate a long distance to reach this point. In the regular hexagon layout of this embodiment, through the use of an appropriate layout, all trenches can be better coupled together. This is an obvious advantage for very fast switching designs. Embodiment 2

[0054] In the semiconductor device of this embodiment, a further improvement based on Embodiment 1 is that in the arrangement of multiple first regular hexagon trenches, the adjacent first regular hexagon trenches are separated by two different spacings (the spacing between adjacent first regular hexagon trenches refers to the distance between adjacent sides of adjacent regular hexagon trenches) the first spacing and the second spacing, the first spacing < the second spacing, and the contact region 5 is only arranged between adjacent first regular hexagon trenches 3 with a spacing of the second spacing.

[0055] As Figure 3 In a, it is a top view of a structural example of the semiconductor device of this embodiment. Among them, each hexagonal trench is separated by two different distances d1 and d2, and the ratio of the area of the region with a distance of d1 to the area of the region with a distance of d2 is 2:1. d1 < d2, and the contact region 5 is only formed at d2.

[0056] Figure 3 In b, it is a top view of another structural example of the semiconductor device of this embodiment. Each hexagonal trench is separated by two different distances d1 and d2, and the ratio of the area of the region with a distance of d1 to the area of the region with a distance of d2 is 1:2. d1 < d2, and the contact region 5 is only formed at d2.

[0057] The semiconductor device of this embodiment overcomes the critical dimension problem of the mesa caused by contact formation, and the spacing between two adjacent hexagonal trenches can be changed as shown in Figure 3 In a and b. The contact region can only be formed in the larger spacing region d2, while the channel modulation mainly occurs in the narrower region d1. The different spacings can be arranged in various ways and ratios to optimize the channel density.

[0058] A further improvement is that, as Figure 13 in a, in the region between adjacent first regular hexagon trenches with a spacing of the second spacing, the source region does not extend to the adjacent first regular hexagon trenches on both sides in the width direction, or as Figure 4In section b, the region between adjacent first regular hexagonal grooves with a spacing of the second spacing does not have a source region, but only a contact region. This contact region is connected to the source region between adjacent first regular hexagonal grooves with a spacing of the first spacing. That is, the source region is formed only on the small platform; otherwise, there would be active portions on two different platforms, which is not ideal. The contact region is only connected to the area where the small and large platforms intersect, i.e., connected to the source region. Example 3

[0059] A further improvement of the semiconductor device in this embodiment, based on Embodiment 1, is that adjacent first hexagonal trenches 3 are interconnected by one or a combination of an additional conductive layer 7 and orthogonal trenches 8 to transmit gate signals; the conductive layer 7 is disposed above the body semiconductor material; the orthogonal trenches 8 extend from the upper surface of the semiconductor device into the body region 1 and the enhancement region 2, and there are one or more orthogonal trenches 8; in the region where the conductive layer 7 is disposed, the contact region 5 is interrupted; in the region where the orthogonal trenches 8 are disposed, the source region 4 is interrupted, and no contact region 5 is disposed. In these regions, the source contacts are disconnected. However, a channel region can still be formed below the polysilicon gate trace, and current can be conducted through the source layer. The conductive layer can be doped polysilicon above the body semiconductor material.

[0060] like Figure 5 Image a is a top view of an example structure of the semiconductor device in this embodiment, wherein adjacent first regular hexagonal trenches 3 are interconnected by an additional conductive layer 7 to transmit gate signals. Figure 5 b and c are Figure 5 The longitudinal section view obtained by drawing the tangent shown in Figure a is shown. The conductive layer 7 is disposed above the host semiconductor material. In the active region extending along the x-direction, the contact region 5 is interrupted to accommodate the conductive connection between the regular hexagonal trenches so as to connect them to the gate potential.

[0061] like Figure 6 Image a is a top view of the second example structure of the semiconductor device in this embodiment, wherein adjacent first regular hexagonal trenches 3 are interconnected by two trenches that are parallel to each other and perpendicular to the sides of the regular hexagonal trenches, transmitting gate signals. In the region where the orthogonal trenches 8 are provided, the source region 4 is interrupted, and the contact region 5 is not provided. This connection serves to interrupt the source and connect the gate. Figure 6 Figure b shows an example of an orthogonal trench 8 with a higher proportion. Using dual trenches also creates a source interruption region, which can be used to control the minority carrier injection efficiency in the device.

[0062] like Figure 7 In Figure a, the third example structure of the semiconductor device in this embodiment is a top view, wherein adjacent first regular hexagonal trenches 3 are interconnected by an orthogonal trench to transmit gate signals. Figure 7 b is along Figure 7 The longitudinal section view obtained by drawing the tangent is shown in Figure a. In the area where the orthogonal groove 8 is set, the source region 4 is interrupted, and the contact region 5 is not set.

[0063] Furthermore, each hexagonal trench can be connected to 0-6 adjacent hexagonal trenches via any one of the three connections described above or a combination thereof. This allows for flexibility in device design to achieve the desired switching symmetry, source ratio, channel density, and contact area. Example 4

[0064] A further improvement of the semiconductor device in this embodiment, based on Embodiment 1, is that at least one first hexagonal trench 3 is surrounded by a highly doped first floating p-well region 9 of the second conductivity type. The depth of the first floating p-well region 9 is greater than the depth of the first hexagonal trench 3. The first floating p-well region 9 is not electrically connected to an electrode. Figure 4 As shown in Figure a.

[0065] Another embodiment, a further improvement on embodiment 1, is that at least one first regular hexagonal trench has an emitter contact or source contact 10 inside. For example... Figure 4 As shown in b.

[0066] The interior of a regular hexagonal trench can contain a floating P-well region for additional trench protection, or an emitter short-circuit structure to improve switch controllability. These additional design elements can also be selectively applied only to certain hexagonal trenches. Example 5

[0067] A further improvement of the semiconductor device in this embodiment, based on Embodiment 1, is that at least one first regular hexagonal trench 3 has a closed second regular hexagonal trench 11 inside; the cross-section of the second regular hexagonal trench 11 is a closed regular hexagonal outline, the second regular hexagonal trench 11 is concentric with the first regular hexagonal trench 3, and its side length is smaller than that of the first regular hexagonal trench 3; the sides of the second regular hexagonal trench 11 are parallel to the sides of the first regular hexagonal trench 3; the second regular hexagonal trench 11 extends from the upper surface of the semiconductor device into the body region 1 and the enhancement region 2. A second floating P-well region 12 is also provided in the region between the first regular hexagonal trench 3 and the second regular hexagonal trench 11 or in the region enclosed by the second regular hexagonal trench 11.

[0068] Figure 8 In the example shown in Figure 'a', a second floating P-trap region 12 is provided in the area enclosed by the second regular hexagonal groove 11 inside. Figure 8 b is Figure 8The longitudinal cross-sectional view obtained by drawing a tangent along line a is shown in the figure. The outer trench includes the active (gate) trench, and the inner hexagon is a dummy trench. The inner trench can be connected to the gate or emitter / source potential, which affects the switching behavior of the device. In addition, the interior of the inner hexagonal trench is filled with a floating P-well region. Example 6

[0069] A further improvement of the semiconductor device in this embodiment based on embodiment 5 is that, in at least one first regular hexagonal trench 3, in the region between the first regular hexagonal trench and the second regular hexagonal trench where the second floating P-well region 12 is not provided, or in the region enclosed by the second regular hexagonal trench where the second floating P-well region 12 is not provided, there is an emitter contact or a source contact 13.

[0070] like Figure 9 In this embodiment, 'a' represents a structural example using concentric hexagonal trench units. The outer regular hexagon serves as the active trench, and the inner regular hexagon serves as the virtual trench. Instead of a second floating P-well region 12, the concentric trench pairs form a contact 13, which acts as a conductive path for majority carriers. The inner hexagon is filled with the second floating P-well region 12. Figure 9 b is Figure 9 Draw the longitudinal section view obtained by drawing the tangent line shown in Figure a. Example 7

[0071] A further improvement of the semiconductor device in this embodiment, based on Embodiment 1, is that at least one first regular hexagonal trench 3 has a closed second regular hexagonal trench 11 inside; a second floating P-well region 12 is also provided in the region between the first regular hexagonal trench 3 and the second regular hexagonal trench 11. The outer hexagon serves as the active trench, and the inner hexagon serves as the virtual trench. Adjacent first regular hexagonal trenches 3 are interconnected by an additional conductive layer 7 to transmit gate signals. In the active region extending along the x-direction, the contact area is interrupted to accommodate the conductive connection between the hexagonal trenches so as to connect them to the gate potential.

[0072] Figure 10 In this embodiment, 'a' represents a structural example where a floating P-well region is formed between concentric hexagons.

[0073] Figure 10 In this embodiment, b is another structural example, and... Figure 10 The difference in a is that the emitter / source contact 14 is located inside the inner hexagon.

[0074] Figure 11 Figures a and b illustrate another structural example of this embodiment. Figure 10Based on the structure of b, an emitter contact 15 is also provided in the internal hexagonal trench to bias the virtual trench to the emitter / source potential.

[0075] In the embodiments disclosed in this invention, the design elements can be freely combined with each other, and any type of hexagonal unit disclosed can be arranged in any proportion or pattern in the same semiconductor device.

[0076] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, include: Drift region of the first conductivity type; A body region of the second conductivity type is disposed within the drift region; Multiple closed first regular hexagonal trenches extend from the upper surface of the semiconductor device into the body region; each first regular hexagonal trench has a closed regular hexagonal profile in cross-section; the first regular hexagonal trenches are filled with a conductive material, and the conductive material is electrically isolated from other structures of the semiconductor device through a dielectric layer; the conductive material is connected to a gate electrode; the first regular hexagonal trenches are arranged adjacent to each other, and adjacent sides of adjacent first regular hexagonal trenches are parallel to each other; the side lengths of the first regular hexagonal trenches are the same. A highly doped source region of the first conductivity type is embedded within the body region, and the source region is located between adjacent sides of an adjacent first regular hexagonal trench. A contact region is provided in the source region, and the contact region is connected to the source electrode or the emitter electrode; A first conductivity type enhancement region is disposed below the body region; The first regular hexagonal trench extends from the upper surface of the semiconductor device into the body region and the enhancement region; The spacing between adjacent first regular hexagonal grooves includes a first spacing and a second spacing, the second spacing being greater than the first spacing, and the contact area is provided only between adjacent first regular hexagonal grooves with a spacing of the second spacing; The region between adjacent first regular hexagonal trenches with a spacing of the second spacing, wherein the source region does not extend to the adjacent first regular hexagonal trenches on either side in the width direction; Alternatively, a source region may be provided in the area between adjacent first regular hexagonal grooves with a spacing of the second spacing, but only a contact region may be provided, and the contact region may be connected to the source region between adjacent first regular hexagonal grooves with a spacing of the first spacing.

2. The semiconductor device according to claim 1, characterized in that: Adjacent first hexagonal trenches are interconnected by an additional conductive layer, or one or a combination of orthogonal trenches, to transmit gate signals; the conductive layer is disposed above the body semiconductor material; the orthogonal trenches extend from the upper surface of the semiconductor device into the body region, and there are one or more orthogonal trenches; in the region where the conductive layer is disposed, the contact region is interrupted; in the region where the orthogonal trenches are disposed, the source region is interrupted, and no contact region is disposed.

3. The semiconductor device according to claim 1 or 2, characterized in that: At least one first regular hexagonal trench surrounds a highly doped first floating p-well region of a second conductivity type, the depth of the first floating p-well region being greater than the depth of the first regular hexagonal trench, and the first floating p-well region being not electrically connected to an electrode.

4. The semiconductor device according to claim 1 or 2, characterized in that: At least one first regular hexagonal trench has an emitter contact or a source contact inside.

5. The semiconductor device according to claim 1 or 2, characterized in that: The source region is interrupted at any ratio.

6. The semiconductor device according to claim 1 or 2, characterized in that: At least one of the first regular hexagonal grooves has a closed second regular hexagonal groove inside; the cross-section of the second regular hexagonal groove is a closed regular hexagonal outline, the second regular hexagonal groove is concentric with the first regular hexagonal groove, and its side length is smaller than that of the first regular hexagonal groove; the side of the second regular hexagonal groove is parallel to the side of the first regular hexagonal groove. The second regular hexagonal trench extends from the upper surface of the semiconductor device into the body region and the enhancement region.

7. The semiconductor device according to claim 6, characterized in that: In at least one of the first regular hexagonal trenches, a second floating P-trap region is further provided in the region between the first regular hexagonal trench and the second regular hexagonal trench or in the region enclosed by the second regular hexagonal trench.

8. The semiconductor device according to claim 7, characterized in that: In at least one of the first regular hexagonal trenches, an emitter contact or a source contact is provided in the region between the first regular hexagonal trench and the second regular hexagonal trench where the second floating P-well region is not provided, or in the region enclosed by the second regular hexagonal trench where the second floating P-well region is not provided.

9. The semiconductor device according to claim 6, characterized in that: At least one of the second regular hexagonal trenches in the first regular hexagonal trench is connected to the emitter or source potential.

10. The semiconductor device according to claim 6, characterized in that: The second regular hexagonal groove is in a floating state.

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