Power semiconductor device and method for producing power semiconductor device

Abstract

The invention relates to a power semiconductor device and a method of producing a power semiconductor device. The power semiconductor diode includes: a semiconductor body having a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to an anode region of the second conductivity type, the anode region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to both a cathode region of the first conductivity type and a shorting region of the second conductivity type of a doped region arranged in the semiconductor body and coupled to the drift region. The diode is configured to conduct a load current between the first and second load terminals, a first path thereof passing through each of the anode, drift and cathode regions, and a second path thereof passing through each of the anode, drift and short circuit regions. At least one resistive element is arranged outside the semiconductor body within the second load current path, exhibiting a resistance having a positive temperature coefficient.

Description

Technical Field

[0001] The present description relates to embodiments of a power semiconductor device and to embodiments of a method of producing a power semiconductor device. Background Art

[0002] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes, to name a few, have been used in a variety of applications including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device typically includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region that is terminated by the edge of the chip.

[0004] In the case of a controllable power semiconductor device (e.g. a transistor), the load current path can be controlled by means of an insulated electrode (usually referred to as a gate electrode). For example, upon receiving a corresponding control signal (e.g. from a driver unit via a control terminal of the device), the control electrode can set the power semiconductor device in one of a forward conducting state and a blocking state.

[0005] In addition, some devices provide reverse load current capability; that is, the active area of ​​the semiconductor body is further configured to conduct reverse load current along a reverse load current path between two load terminals of the device. For example, the RC (reverse current) IGBT is a representative of such a device. In the RC IGBT, a single chip combines the IGBT structure and the diode structure together.

[0006] Regardless of whether the device exhibits an RC configuration or not, the goal is generally to design a power semiconductor device such that it exhibits high robustness, ie, high robustness in handling overload conditions during which the load current temporarily exceeds the nominal load current, e.g. due to a short circuit condition or the like.

[0007] To this end, the goal is generally to provide devices with a more uniform temperature distribution. It has been observed that laterally non-uniform temperature distribution during operation (self-heating) may lead to reduced switching robustness behavior and / or power cycling stability. Non-uniform temperature dependence may also reduce the short-circuit robustness of transistors and the surge current robustness of diodes. Such negative effects are amplified in the presence of solder voids. Furthermore, with regard to SiC-based MOSFETs, non-uniform temperature distribution may amplify bipolar degradation. Summary of the invention

[0008] The subject matter of the independent claims is set out. Features of the exemplary embodiments are defined in the dependent claims.

[0009] According to an embodiment, a power semiconductor diode comprises: a semiconductor body having a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to an anode region of a second conductivity type, the anode region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to a cathode region of a first conductivity type and a short circuit region of a second conductivity type of a doped region, the doped region being arranged in the semiconductor body and coupled to the drift region, whereby the drift region may optionally include a buffer layer of the first conductivity type. The power semiconductor diode is configured to conduct a load current between the first load terminal and the second load terminal. The first path of the load current passes through each of the anode region, the drift region, and the cathode region. The second path of the load current passes through each of the anode region, the drift region, and the short circuit region. At least one resistive element is arranged outside the semiconductor body within the second load current path, wherein the at least one resistive element exhibits a resistance having a nonlinear positive temperature coefficient.

[0010] According to another embodiment, a power semiconductor diode includes: a semiconductor body having a drift region of a first conductivity type, whereby the drift region may optionally include a buffer layer of the first conductivity type; a first stack having a first load terminal, the first load terminal being at a first side of the semiconductor body and coupled to an anode region of a second conductivity type, the anode region being arranged in the semiconductor body and above the drift region; a second stack at a second side of the semiconductor body, wherein the second stack includes a second load terminal and at least one resistive element arranged outside the semiconductor body, wherein the power semiconductor diode is configured to conduct a load current between the first load terminal and the second load terminal; a doped region in the semiconductor body and below the drift region, the doped region including a cathode region of the first conductivity type and a short-circuit region of the second conductivity type in contact with the second stack. The at least one resistive element exhibits a resistance having a positive temperature coefficient greater than a positive temperature coefficient of the second load terminal. At least one of the short-circuit regions is coupled to the second load terminal via the at least one resistive element.

[0011] According to a further embodiment, a power semiconductor circuit comprises a power semiconductor diode and a power semiconductor transistor as described above, wherein the power semiconductor diode is connected in anti-parallel with the power semiconductor transistor to form a freewheeling diode.

[0012] In yet another embodiment, a power semiconductor device includes, in an active region surrounded by an edge termination region: a semiconductor body having a drift region of a first conductivity type, whereby the drift region may optionally include a buffer layer of the first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to a body region of a second conductivity type, the body region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to a doped region, the doped region being arranged in the semiconductor body and coupled to the drift region. The power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal, wherein a path of the load current passes through each of the body region, the drift region, and the doped region. At least one resistive element is arranged outside the semiconductor body within the load current path, wherein the at least one resistive element exhibits a resistance having a greater positive temperature coefficient than the second load terminal.

[0013] According to a further embodiment, a method of producing a power semiconductor diode includes forming the following components: a semiconductor body having a drift region of a first conductivity type, whereby the drift region may optionally include a buffer layer of the first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to an anode region of a second conductivity type, the anode region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to both a cathode region of a first conductivity type and a short circuit region of a doped region, the doped region being arranged in the semiconductor body and coupled to the drift region. The power semiconductor diode is configured to conduct a load current between the first load terminal and the second load terminal. A first path of the load current passes through each of the anode region, the drift region, and the cathode region. A second path of the load current passes through each of the anode region, the drift region, and the short circuit region. At least one resistive element is arranged outside the semiconductor body within the second load current path, wherein the at least one resistive element exhibits a resistance having a positive temperature coefficient.

[0014] According to a further embodiment, a method for producing a power semiconductor diode comprises forming the following components: a semiconductor body having a drift region of a first conductivity type, whereby the drift region may optionally include a buffer layer of the first conductivity type; a first stack having a first load terminal, the first load terminal being at a first side of the semiconductor body and coupled to an anode region of a second conductivity type, the anode region being arranged in the semiconductor body and above the drift region; a second stack at a second side of the semiconductor body, wherein the second stack comprises a second load terminal and at least one resistive element arranged outside the semiconductor body, wherein the power semiconductor diode is configured to conduct a load current between the first load terminal and the second load terminal; a doped region within the semiconductor body and below the drift region, the doped region comprising a cathode region of the first conductivity type and a short-circuit region of the second conductivity type in contact with the second stack. The at least one resistive element exhibits a resistance having a positive temperature coefficient greater than a positive temperature coefficient of the second load terminal. At least one of the short-circuit regions is coupled to the second load terminal via the at least one resistive element.

[0015] According to a further embodiment, a method of producing a power semiconductor device includes forming the following components in an active area surrounded by an edge termination region: a semiconductor body having a drift region of a first conductivity type, whereby the drift region may optionally include a buffer layer of the first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to a body region of a second conductivity type, the body region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to a doped region, the doped region being arranged in the semiconductor body and coupled to the drift region. The power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal, wherein a path of the load current passes through each of the body region, the drift region, and the doped region. At least one resistive element is arranged outside the semiconductor body within the load current path, wherein the at least one resistive element exhibits a resistance having a greater positive temperature coefficient than the second load terminal.

[0016] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The parts in the figures are not necessarily drawn to scale, but the emphasis is placed on illustrating the principles of the present invention. In addition, in the figures, similar reference numerals designate corresponding parts. In the drawings:

[0018] Figure 1 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to an example;

[0019] Figure 2 and Figure 3 both schematically and exemplarily illustrate a portion of a vertical cross-section of a respective power semiconductor device according to one or more embodiments;

[0020] Figure 4 and Figure 5 each schematically and exemplarily illustrates a portion of a vertical cross-section of a respective power semiconductor diode according to one or more embodiments; and

[0021] Figure 6 Power semiconductor circuits according to some embodiments are schematically and exemplarily illustrated. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0023] In this regard, directional terms, such as "top", "bottom", "below", "front", "rear", "back", "in front of", "trailing", "above", etc., may be used with reference to the orientation of the figures being described. Because portions of the embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be read in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0024] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided as an explanation and is not meant to be limiting of the invention. For example, a feature illustrated or described as part of one embodiment may be used on or in combination with other embodiments to produce yet another embodiment. It is intended that the invention include such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The figures are not drawn to scale and are for illustration purposes only. For clarity, the same elements or manufacturing steps have been designated by the same reference numerals in different figures unless otherwise stated.

[0025] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, a surface of a semiconductor wafer or die or chip. For example, the first lateral direction X and the second lateral direction Y mentioned below may both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0026] The term "vertical" as used in this specification is intended to describe an orientation that is arranged substantially perpendicular to a horizontal surface (i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die). For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z".

[0027] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be employed, such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0028] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, parts, zones, locations or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a part or component of a semiconductor device, where "low ohmic" may mean that the characteristics of the respective contact are substantially unaffected by ohmic resistance. Furthermore, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0029] Additionally, in the context of this specification, if not stated otherwise, the term "electrically insulated" is used in the context in which it is generally understood, and is therefore intended to describe that two or more components are located separately from each other and there is no ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, such as mechanically and / or capacitively and / or inductively and / or electrostatically (e.g., in the case of a junction). For example, two electrodes of a capacitor can be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, such as with the aid of an insulator (e.g., a dielectric).

[0030] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in an embodiment, such a power semiconductor device can be configured to carry a load current to be fed to a load, and / or, correspondingly, to carry a load current provided by a power supply. For example, a power semiconductor device may include one or more active power semiconductor unit cells, such as a monolithic integrated diode cell, a derivative of a monolithic integrated diode cell, a monolithic integrated transistor cell (e.g., a monolithic integrated IGBT or MOSFET cell) and / or its derivatives. Such a diode / transistor cell can be integrated in a single chip. A plurality of such cells can constitute a cell field arranged in an active region of the power semiconductor device.

[0031] The term "blocking state" of a power semiconductor device may refer to a condition when the power semiconductor is in a state configured to block the flow of a load current while an external voltage is applied. More particularly, the power semiconductor device may be configured to block a forward load current through the power semiconductor device while a forward voltage bias is applied. In comparison, a power semiconductor device may be configured to conduct a forward load current in a "conducting state" of the power semiconductor device while a forward voltage bias is applied. The transition between the blocking state and the conducting state may be controlled by controlling the electrode, or more particularly, the potential of the control electrode. Of course, the electrical characteristics may only be applicable within a predetermined operating range of an external voltage and current density within the power semiconductor device. Therefore, the term "forward biased blocking state" may refer to a condition in which a power semiconductor device is in a blocking state while a forward voltage bias is applied.

[0032] The term "power semiconductor device" as used in this specification is intended to describe a power semiconductor device on a single chip having a high voltage blocking and / or high current carrying capability. In other words, such a power semiconductor device is intended for: high currents, typically in the ampere range, such as up to tens or hundreds of amperes; and / or high voltages, typically above 15V, more typically 100V and higher, such as up to at least 400V or even higher, such as up to at least 3kV, or even up to 10kV or higher, depending on the respective application.

[0033] For example, the term "power semiconductor device" as used in this specification does not refer to a logic semiconductor device used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0034] For example, the power semiconductor device described below may be a single semiconductor chip exhibiting, for example, a stripe cell configuration (or honeycomb / pin cell configuration) and may be configured for use as a power component in low voltage applications, medium voltage applications, and / or high voltage applications.

[0035] Figure 1 Schematically and exemplarily a portion of a vertical cross section of a power semiconductor device 1 according to one or more embodiments is illustrated. The power semiconductor device 1, also referred to herein as a "device", comprises in a single chip: a semiconductor body 10 configured to conduct a load current between a first load terminal 11 at a first side 110 of the semiconductor body 10 and a second load terminal 12 at a second side 120 of the semiconductor body 10.

[0036] The first side 110 and the second side 120 may be arranged opposite to each other. For example, the first side 110 is the front side of the device 1, and the second side 120 is the back side of the device 1. Therefore, the device 1 may exhibit a vertical configuration, according to which the load current in the device 1 follows a path parallel to the vertical direction Z.

[0037] The device 1 further comprises a drift region 100 of the first conductivity type within the semiconductor body 10. In this document, the term "drift region" is used in the sense that a person skilled in the art typically associates with it in the field of power semiconductor devices. For example, the vertical extension of the drift region 100 and its doping level affect the voltage blocking capability of the device 1.

[0038] The device 1 further comprises trenches 14 extending from the first side 110 towards the second side 120 , for example along a vertical direction Z. Each trench 14 comprises a trench electrode 141 separated from the semiconductor body 10 by a trench insulator 142 .

[0039] The trench 14 may be a control trench, wherein each trench electrode 141 is electrically insulated from the first load terminal 11 and is configured to receive a control signal. To this end, according to an embodiment, each trench electrode 141 may be electrically connected to a (not illustrated) control terminal of the device 1. In this document, the trench 14 is also referred to as a "control trench", and the corresponding trench electrode 141 is also referred to as a "control trench electrode".

[0040] The control trench 14 laterally limits the mesa portion of the semiconductor body 10. For example, each mesa portion is electrically connected to the first load terminal 11, for example by means of a corresponding contact plug extending from the first load terminal 11 into the semiconductor body 10, as illustrated. Alternatively, a planar contact can be adopted. Each mesa portion can be configured for load current conduction. For example, each mesa portion includes a semiconductor body region 102 of a second conductivity type electrically connected to the first load terminal 11, and optionally includes a semiconductor source region 101 of a first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is isolated from the drift region 100 by at least the semiconductor body region 102. The adjacent control trench electrode 141 can be configured to induce an inversion channel in the semiconductor body region 102 when subjected to a corresponding ON control signal. This process can set the device 1 to a forward conduction state. The adjacent control trench electrode 141 can be configured to cut off the inversion channel in the semiconductor body region 102 when subjected to a corresponding OFF control signal, which can set the device 1 to a forward blocking state.

[0041] The above-mentioned features of the power semiconductor device 1 may allow different trench mesa patterns to be designed at the first side 110. Such patterns may include additional trench types and / or additional mesa types, for example, a source trench whose trench electrode is electrically connected to the first load terminal 11, a floating trench whose trench electrode is not connected to a defined potential, or a second type of control trench whose trench electrode is connected to a different control terminal compared to the control trench electrode 141 to achieve a dual-gate or multi-gate configuration, etc. Other types of mesa portions may also be implemented, such as mesa portions with different threshold voltages, dummy mesa portions, etc.

[0042] A doped region 109 of the semiconductor body 10 below the drift region 100 adjacent to the second load terminal 12 at the second side 120 may be configured according to specified characteristics of the device 1. For example, if the device 1 is to exhibit an IGBT configuration, the doped region 109 may be an emitter region of the second conductivity type. The emitter region is arranged in contact with the second load terminal 12. In addition, a field stop region (not illustrated) of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region exhibits a greater dopant concentration than the drift region 100. If the device 1 is to exhibit a MOSFET configuration, the emitter region is omitted, so that the field stop region (or another highly doped region of the first conductivity type) will be adjacent to the second load terminal 12. If the device 1 is to exhibit an RC IGBT configuration, the emitter region may exhibit a sub-portion of the first conductivity type, as known to the person skilled in the art.

[0043] The above components of the power semiconductor device 1 are arranged in an active area 1-2 of the device 1, which is surrounded by an edge termination area 1-3. In the active area 1-2, the trench 14 and the associated mesa portion can form a cell field, which can exhibit a honeycomb / needle cell configuration or a strip cell configuration. The edge termination area 1-3 is typically not used for load current conduction, as known to those skilled in the art. The edge termination area 1-3 is terminated by the chip edge 1-4.

[0044] The path of the load current between the first load terminal 11 and the second load terminal 12 passes through each of the body region 102 , the drift region 100 , and the doped region 109 .

[0045] The temperature distribution within the device 1 depends on the distribution of the load current. In the following, a feature is presented which allows designing a device 1 with a beneficial temperature distribution, especially for high ambient temperatures.

[0046] Reference diagram with Figure 1 Similar structures Figure 2 It is proposed to include a resistive element 13 within the load current path but outside the semiconductor body, the resistive element 13 exhibiting a resistance with a positive temperature coefficient, for example, greater than the positive temperature coefficient of the second load terminal 12. For example, the resistance of the resistive element 13 exhibits a positive temperature coefficient of at least 2 times or even at least 10 times the positive temperature coefficient of the second load terminal 12.

[0047] like Figure 2 As illustrated, the resistive element 13 may be provided both at the first side 110 (eg, the front side) and at the second side 120 (eg, the back side). In other embodiments, the resistive element 13 is provided at the first side 110 or at the second side.

[0048] In an embodiment, the at least one resistive element 13 is arranged in a central portion of the active region 1-2 relative to the lateral extension of the active region 1-2. For example, due to the resistance of the at least one resistive element 13, in case of high ambient / operating temperatures, this may result in a load current concentration that is reduced in the central portion of the active region 1-2 and increased in the peripheral portion of the active region 1-2 (closer to the edge termination region 1-3). Thus, a more beneficial temperature distribution within the semiconductor body 10 may be achieved.

[0049] The exact dimensioning and positioning of the at least one resistive element 13 may be adapted to the configuration of the cell field within the active region 1-2. For example, the at least one resistive element 13 exhibits a total lateral cross-sectional area of ​​at least 20% of the total lateral cross-sectional area of ​​the active region 1-2.

[0050] In addition, if Figure 2As illustrated, at least one resistive element 13 may be arranged in contact with the semiconductor body 10, thereby forming an interface layer between the semiconductor body 10 and at least one of the first load terminal 11 and the second load terminal 12. Figure 3 As shown, at least one resistor element 13 is coupled to the semiconductor body 10 via an intermediate layer 135. For example, the intermediate layer 135 comprises one or more of Al, AlSi, AlSiCu and Ti. Furthermore, the intermediate layer 35 may exhibit a thickness in the vertical direction Z of at least 3 nm and at most 3 μm.

[0051] The intermediate layer 135 may be a highly conductive layer, for example, exhibiting the same lower resistance as the at least one resistive element 13 .

[0052] According to an embodiment, the device 1 comprises a first stack of different material layers at a first side 110 of the semiconductor body 10, the different material layers in particular forming a first load terminal and optionally comprising at least one of the at least one resistive element 13. Furthermore, according to an embodiment, the device 1 comprises a second stack of different material layers at a second side 120 of the semiconductor body 10, the different material layers in particular forming a second load terminal 12 and optionally comprising at least one of the at least one resistive element 13. For example, the first stack and the second stack are configured such that the device 1 can be mounted within an application, for example such that the second stack can be mounted within a module and such that bonding wires can be connected to the first stack.

[0053] The at least one element 13 may thus be integrated in the power semiconductor device 1 by being included in at least one of the first stack and the second stack.

[0054] As mentioned above, Figure 2 The device 1 illustrated in may exhibit a MOSFET or an IGBT configuration. Its semiconductor body 10 is based on silicon, for example, or alternatively on a wide bandgap material such as SiC or GaN.

[0055] According to the embodiments described herein, it is also proposed to equip a power semiconductor device with a diode configuration using such a resistor element 13 .

[0056] For example, an exemplary embodiment of such a diode 1 is Figure 4 and Figure 5 In the diagram, we will now refer to Figure 4 and Figure 5 .

[0057] Figure 4 The power semiconductor devices are configured similar to Figure 2 and Figure 3 A power semiconductor device 1. Figure 4The power semiconductor device 1 has a diode configuration (rather than a transistor configuration) and will therefore be referred to as a diode 1. The diode 1 includes: a semiconductor body 10 having a drift region 100 of a first conductivity type; a first load terminal 11, which is at a first side 110 of the semiconductor body 10 and coupled to an anode region 102 of a second conductivity type, the anode region 102 being arranged in the semiconductor body 10 and coupled to the drift region 100; a second load terminal 12, which is at a second side 120 of the semiconductor body 10 and coupled to both a cathode region 107 of a first conductivity type and a short-circuit region 108 of a second conductivity type of a doped region 109. The doped region 109 is arranged in the semiconductor body 10 and coupled to the drift region 100. The power semiconductor diode 1 is configured to conduct a load current between the first load terminal 11 and the second load terminal 12. A first path of the load current passes through each of the anode region 102, the drift region 100, and the cathode region 107. A second path of the load current passes through each of the anode region 102, the drift region 100, and the short-circuit region 108. At least one resistance element 13 is arranged outside the semiconductor body 10 within the second load current path, wherein the at least one resistance element 13 exhibits a resistance having a positive temperature coefficient.

[0058] In this context, it should be noted that the term "load current" refers to all kinds of load currents occurring within the semiconductor body 10, not only the nominal forward load current, but also the current occurring during the switching process or other transient conditions (such as the change between the blocking state and the conducting state), as well as the associated currents and current paths. For example, in the short-circuit region 108, the load current is observed only during the turn-off process.

[0059] For example, as described above, the first load terminal 11 is part of a first stack at the first side 110 of the semiconductor body 10 of the diode 1. For example, the anode region 102 is arranged in the semiconductor body 10 and above the drift region 100. A second stack at the second side 120 of the semiconductor body 10 may be provided, wherein the second stack comprises a second load terminal 12. For example, the second stack further comprises at least one resistive element 13 arranged outside the semiconductor body 10. Furthermore, a doped region 109 within the semiconductor body 10 may be arranged below the drift region 100. As explained, the doped region 109 may include a cathode region 107 of a first conductivity type and a short-circuit region 108 of a second conductivity type, wherein both the cathode region 107 and the short-circuit region 108 may be arranged in contact with the second stack.

[0060] The at least one resistive element may exhibit a resistance having a positive temperature coefficient greater than a positive temperature coefficient of the second load terminal 12 .

[0061] Furthermore, according to an embodiment, at least one of the short-circuit regions 108 is coupled to the second load terminal 12 via at least one resistive element 13 .

[0062] In an embodiment, at least one resistive element 13 is integrated with the power semiconductor diode 1 , for example by forming a part of the first stack and / or the second stack.

[0063] For example, at least one resistive element 13 is coupled to at least one of the short-circuit regions 108. It can also be provided that there is one resistive element for each short-circuit region 108. In an embodiment, for each of at least 90% of the number of short-circuit regions 109, the diode 1 comprises at least one resistive element 13. Alternatively, several or all of the short-circuit regions 108 share the same resistive element 13.

[0064] As mentioned above Figure 2 and Figure 3 As explained, the at least one resistance element may directly adjoin the semiconductor body 10 (ie be arranged in contact with a portion of the semiconductor body 10 ) or be coupled to the semiconductor body 10 via the intermediate layer 135 .

[0065] For example, at least one resistor element 13 is arranged to contact at least one of the short-circuit regions 108. Alternatively, at least one resistor element 13 is coupled to at least one of the short-circuit regions 108 via an intermediate layer 135. The intermediate layer 135 in the diode 1 may be as described above with respect to Figure 3 Configure as described.

[0066] like Figure 4 As illustrated, the short-circuit regions 108 and the cathode regions 109 are alternately arranged next to each other along the first lateral direction X. Both the short-circuit regions 108 and the cathode regions 109 are arranged in contact with a second stack comprising a second load terminal and at least one resistive element 13. The at least one resistive element 13 may be arranged to completely or at least partially laterally overlap at least one of the short-circuit regions 108.

[0067] In an embodiment, the doped region 109 further includes a deep region 1081 of the second conductivity type, which is arranged to be in contact with and above the short-circuit region 108, such as Figure 4 These deep regions 1081 may exhibit the same greater dopant concentration as the shorting regions 108 .

[0068] Regarding all embodiments described herein, the semiconductor body 10 may of course include additional and / or other doped regions as described and illustrated. For example, a highly doped contact region may be provided within the anode / body region 102. Furthermore, barrier regions and / or damaged regions may be present, depending on the configuration of the device.

[0069] With respect to all embodiments described herein, it can be provided, for example, that each of the at least one resistive element 13 has a first resistance in the low temperature range that is less than twice the resistance of the second load terminal 12, and has a second resistance in the high temperature range that is at least 3 times, or at least 5 times, or even at least 10 times the first resistance. For example, the first temperature range includes temperatures between -50°C and 100°C, and the second temperature range includes temperatures between 120°C and 300°C. For example, for Si (silicon) based power semiconductor devices, the second temperature range includes temperatures between 120°C and 200°C. For example, for SiC (silicon carbide) based power semiconductor devices, the second temperature range includes temperatures between 200°C and 300°C. The first temperature can be oriented to room temperature or a standard temperature. The second temperature can be oriented to or equal to the (maximum) specified operating temperature of the power semiconductor device.

[0070] Furthermore, with respect to all embodiments described herein, the at least one resistive element 13 is configured to reduce injection of holes into the semiconductor body 10 at high operating temperatures, for example operating temperatures within the second temperature range. For example, thereby, lower switching losses at high temperatures may be achieved.

[0071] Still with respect to all embodiments described herein, the at least one resistive element 13 may include at least one of doped barium titanate, doped titanium, and platinum.

[0072] As described above, the device 1, regardless of having a transistor configuration (see Figure 2 and Figure 3 ) or a diode configuration (see Figure 4 and Figure 5 ), are intended for power applications (not for data storage or computing / logic applications). For example, the device has a nominal load current of at least 1A and a blocking voltage of at least 400V.

[0073] about Figure 6 According to an embodiment, a diode 1 as exemplarily described above can be integrated into a power semiconductor circuit 200. Such a circuit 200 may include a power semiconductor transistor 2 (e.g., an IGBT), and the diode 1 may be connected in anti-parallel with the transistor and act as a freewheeling diode. In particular in such applications, it may be beneficial to equip the diode with at least one resistive element 13 described above, for example, to avoid local overheating in the diode 1.

[0074] A method for producing a power semiconductor device is also proposed in this article.

[0075] For example, according to another embodiment, a method of producing a power semiconductor diode includes forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to an anode region of a second conductivity type, the anode region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to a cathode region of a first conductivity type and a short circuit region of a second conductivity type of a doped region, the doped region being arranged in the semiconductor body and coupled to the drift region. The power semiconductor diode is configured to conduct a load current between the first load terminal and the second load terminal. The first path of the load current passes through each of the anode region, the drift region, and the cathode region. The second path of the load current passes through each of the anode region, the drift region, and the short circuit region. At least one resistive element is arranged outside the semiconductor body within the second load current path, wherein the at least one resistive element exhibits a resistance having a positive temperature coefficient.

[0076] According to a further embodiment, a method for producing a power semiconductor diode comprises forming the following components: a semiconductor body having a drift region of a first conductivity type; a first stack having a first load terminal, the first load terminal being at a first side of the semiconductor body and coupled to an anode region of a second conductivity type, the anode region being arranged in the semiconductor body and above the drift region; a second stack at a second side of the semiconductor body, wherein the second stack comprises a second load terminal and at least one resistive element arranged outside the semiconductor body, wherein the power semiconductor diode is configured to conduct a load current between the first load terminal and the second load terminal; a doped region within the semiconductor body and below the drift region, the doped region comprising a cathode region of the first conductivity type and a short-circuit region of the second conductivity type in contact with the second stack. The at least one resistive element exhibits a resistance having a positive temperature coefficient greater than a positive temperature coefficient of the second load terminal. At least one of the short-circuit regions is coupled to the second load terminal via the at least one resistive element.

[0077] According to a further embodiment, a method of producing a power semiconductor device includes forming the following components in an active area surrounded by an edge termination region: a semiconductor body having a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body and coupled to a body region of a second conductivity type, the body region being arranged in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body and coupled to a doped region, the doped region being arranged in the semiconductor body and coupled to the drift region. The power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal, wherein a path of the load current passes through each of the body region, the drift region, and the doped region. At least one resistive element is arranged outside the semiconductor body within the load current path, wherein the at least one resistive element exhibits a resistance having a greater positive temperature coefficient than the second load terminal.

[0078] The embodiments of the method described above correspond to the embodiments of the power semiconductor device / diode 1 described above. Therefore, these embodiments of the method will not be described verbatim in this text, but reference is made to the above.

[0079] For example, about Figure 4 In the illustrated embodiment, in an exemplary method, before depositing the backside metallization to form the second load terminal 12, the "metal to insulator" material can be deposited on the backside of the wafer and structured using lithography and etching so that the resistor element 13 remains only on the area where the short-circuit area 108 is located in the active area 1-2 (for example, with a certain overlap with the cathode area 107 to cover process variations). Thereafter, the backside metal can be deposited. In this way, the electrical contact of the short-circuit area 108 is temperature-dependent, so that the injection of holes from the short-circuit area 108 will be reduced at high temperatures. Therefore, the turn-off losses can be significantly reduced at high temperatures and the softness will be optimized. At room temperature, the softness behaves like in the reference device without the "metal to insulator" material, but at higher temperatures, the injection from the p-short is reduced, which results in lower turn-off losses compared to the reference structure without the "metal to insulator" material (resistive element 13). Furthermore, the risk that dynamic avalanche will occur at high temperatures will also be reduced, since hole injection from the back side will be reduced. As mentioned above, possible materials for forming the resistor element 13 may be doped barium titanate, doped titanium or platinum based resistors.

[0080] In the above, embodiments concerning a power semiconductor device and a corresponding production method were explained.

[0081] For example, these power semiconductor devices are based on silicon (Si). Therefore, a single crystal semiconductor region or layer, such as a semiconductor body and a region / region thereof, such as a region, etc., can be a single crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0082] However, it should be understood that the semiconductor body and its regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, basic semiconductor materials such as silicon (Si) or germanium (Ge), IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are currently used.

[0083] For ease of description, spatial relative terms such as "below", "below", "lower", "above", "above", etc. are used to explain the positioning of one element relative to a second element. In addition to orientations different from those depicted in the figures, these terms are also intended to cover different orientations of the corresponding devices. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the description, similar terms may refer to similar elements.

Claims

1. A power semiconductor diode (1), comprising: - a semiconductor body (10) having a drift region (100) of a first conductivity type; a first load terminal (11) at a first side (110) of the semiconductor body (10) and coupled to an anode region (102) of a second conductivity type, the anode region (102) being arranged in the semiconductor body (10) and coupled to the drift region (100); a second load terminal (12) at a second side (120) of the semiconductor body (10) and coupled to both a cathode region (107) of the first conductivity type and a short-circuit region (108) of the second conductivity type of a doped region (109) arranged in the semiconductor body (10) and coupled to the drift region (100); ○ The power semiconductor diode (1) is configured to conduct a load current between the first load terminal (11) and the second load terminal (12); o a first path of the load current passes through each of the anode region (102), the drift region (100), and the cathode region (107); o the second path of the load current passes through each of the anode region (102), the drift region (100) and the short-circuit region (108); - at least one resistance element (13) arranged outside the semiconductor body (10) in the second load current path, wherein the at least one resistance element (13) exhibits a resistance with a nonlinear positive temperature coefficient.

2. A power semiconductor diode (1), comprising: - a semiconductor body (10) having a drift region (100) of a first conductivity type; a first stack having a first load terminal (11) at a first side (110) of the semiconductor body (10) and coupled to an anode region (102) of a second conductivity type, the anode region (102) being arranged in the semiconductor body and above the drift region (100); a second stack at a second side (120) of the semiconductor body (10), wherein the second stack comprises a second load terminal (12) and at least one resistive element (13) arranged outside the semiconductor body (10), wherein the power semiconductor diode (1) is configured to conduct a load current between the first load terminal (11) and the second load terminal (12); - a doped region (109) within the semiconductor body (10) and below the drift region (100), the doped region (109) comprising: - a cathode region (107) of a first conductivity type, and - a short-circuit region (108) of a second conductivity type in contact with the second stack; and -in: o the at least one resistive element (13) exhibits a resistance having a positive temperature coefficient greater than a positive temperature coefficient of the second load terminal (12), and o Wherein, at least one of the short-circuit regions (108) is coupled to the second load terminal (12) via the at least one resistive element (13).

3. The power semiconductor diode (1) according to claim 1 or 2, wherein: The at least one resistor element (13) is integrated with the power semiconductor diode (1).

4. The power semiconductor diode (1) according to one of the preceding claims, wherein: The at least one resistive element (13) is coupled to at least one of the short-circuit regions (108).

5. The power semiconductor diode (1) according to one of the preceding claims, wherein: The at least one resistive element (13) is arranged in contact with at least one of the short-circuit regions (108).

6. The power semiconductor diode (1) according to one of the preceding claims 1 to 4, wherein: The at least one resistive element (13) is coupled to at least one of the short-circuit regions (108) via an intermediate layer (135).

7. The power semiconductor diode (1) according to claim 6, wherein: The intermediate layer (135) comprises Al, AlSi, AlSiCu, Ti and / or exhibits a thickness in the vertical direction (Z) of at least 3 nm and at most 3 μm.

8. The power semiconductor diode (1) according to one of the preceding claims, wherein: The at least one resistor element (13) at least partially laterally overlaps at least one of the short-circuit regions (108).

9. The power semiconductor diode (1) according to one of the preceding claims, wherein: The short-circuit regions (108) and the cathode regions (109) are arranged alternately next to each other along a first transverse direction (X).

10. The power semiconductor diode (1) according to one of the preceding claims, comprising at least one resistance element (13) for each of at least 90% of the number of short-circuit regions (109).

11. The power semiconductor diode (1) according to one of the preceding claims, wherein Each of the at least one resistive element (13) has a first resistance less than twice the resistance of the second load terminal (12) in a low temperature range and a second resistance at least ten times the first resistance in a high temperature range, wherein, for example, the first temperature range includes temperatures between -50°C and 100°C, and wherein the second temperature range includes temperatures between 150°C and 300°C.

12. The power semiconductor diode (1) according to one of the preceding claims, wherein: The doped region (109) further comprises a deep region (1081) of the second conductivity type, the deep region (1081) being arranged in contact with and above the short-circuit region (108).

13. The power semiconductor diode (1) according to one of the preceding claims, wherein: The at least one resistive element (13) is configured to reduce injection of holes into the semiconductor body (10) at high operating temperatures.

14. The power semiconductor diode (1) according to one of the preceding claims, wherein: The at least one resistor element (13) includes at least one of doped barium titanate, doped titanium, and platinum-based resistors.

15. The power semiconductor diode (1) according to one of the preceding claims, wherein The power semiconductor diode (1) is configured for a maximum blocking voltage of at least 400V and / or a nominal load current of at least 1A.

16. A power semiconductor circuit (200) comprising a power semiconductor diode (1) and a power semiconductor transistor (2) according to one of the preceding claims, wherein: The power semiconductor diode (1) is connected in anti-parallel with the power semiconductor transistor to form a freewheeling diode.

17. A power semiconductor device (1), comprising, in an active area (1-2) surrounded by an edge termination area (1-3): - a semiconductor body (10) having a drift region (100) of a first conductivity type; a first load terminal (11) at a first side (110) of the semiconductor body (10) and coupled to a body region (102) of a second conductivity type, the body region (102) being arranged in the semiconductor body (10) and coupled to the drift region (100); - a second load terminal (12) at a second side (120) of the semiconductor body (10) and coupled to a doped region (109) arranged in the semiconductor body (10) and coupled to the drift region (100); wherein The power semiconductor diode (1) is configured to conduct a load current between the first load terminal (11) and the second load terminal (12), wherein a path of the load current passes through each of the body region (102), the drift region (100) and the doped region (109); - at least one resistance element (13) arranged outside the semiconductor body (10) within the load current path, wherein the at least one resistance element (13) exhibits a resistance having a greater positive temperature coefficient than the second load terminal (12).

18. The power semiconductor device (1) according to claim 16, wherein: The at least one resistor element (13) is arranged in a central portion of the active area (1-2) relative to a lateral extension of the active area (1-2).

19. The power semiconductor device (1) according to one of the preceding claims 16 to 18, wherein: The at least one resistive element (13) exhibits a total lateral cross-sectional area amounting to at least 20% of the total lateral cross-sectional area of ​​the active area (1-2).

20. The power semiconductor device (1) according to one of the preceding claims 16 to 19, wherein: The semiconductor body is based on a wide bandgap semiconductor material, such as SiC or GaN.

Images